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| REJ09B0466-0100 16 H8S/2426, H8S/2426R, H8S/2424 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series H8S/2426 H8S/2426R H8S/2424 R4F2426 R4S2426 R4F2426R R4S2426R R4F2424 R4S2424 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.1.00 Revision Date: Sep. 19, 2008 Rev. 1.00 Sep. 19, 2008 Page ii of xxviii Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 1.00 Sep. 19, 2008 Page iii of xxviii General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Rev. 1.00 Sep. 19, 2008 Page iv of xxviii How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8S/2426, H8S/2426R, H8S/2424 Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Data Sheet Hardware Manual Contents Document Title Document No. This manual Overview of hardware and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation Detailed descriptions of the CPU and instruction set Examples of applications and sample programs Preliminary report on the specifications of a product, document, etc. H8S/2426, H8S/2426R, H8S/2424 Group Hardware Manual Software Manual H8S/2600 Series REJ09B0139 H8S/2000 Series Software Manual The latest versions are available from our web site. Application Note Renesas Technical Update Rev. 1.00 Sep. 19, 2008 Page v of xxviii 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. Rev. 1.00 Sep. 19, 2008 Page vi of xxviii 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Table of Bits] (1) Bit 15 14 13 to 11 10 9 (2) Bit Name - - ASID2 to ASID0 - - - (3) (4) Description Reserved These bits are always read as 0. Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. (5) Initial Value R/W 0 0 All 0 0 1 0 R R R/W R R Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "-". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 -: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing. Rev. 1.00 Sep. 19, 2008 Page vii of xxviii 4. Description of Abbreviations The abbreviations used in this manual are listed below. * Abbreviations specific to this product Description Bus controller Clock pulse generator Interrupt controller Serial communication interface 8-bit timer 16-bit timer pulse unit Watchdog timer Abbreviation BSC CPG INT SCI TMR TPU WDT * Abbreviations other than those listed above Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Description Asynchronous communication interface adapter Bits per second Cyclic redundancy check Direct memory access Direct memory access controller Global System for Mobile Communications High impedance Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) Input/output Infrared Data Association Least significant bit Most significant bit No connection Phase-locked loop Pulse width modulation Special function register Subscriber Identity Module Universal asynchronous receiver/transmitter Voltage-controlled oscillator All trademarks and registered trademarks are the property of their respective owners. Rev. 1.00 Sep. 19, 2008 Page viii of xxviii Contents Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.1.1 Applications.............................................................................................................. 1 1.1.2 Overview of Specifications....................................................................................... 1 List of Products...................................................................................................................... 8 Block Diagrams ..................................................................................................................... 9 Pin Description .................................................................................................................... 11 1.4.1 Pin Assignments ..................................................................................................... 11 1.4.2 Pin Assignments in Each Operating Mode ............................................................. 14 1.4.3 Pin Functions .......................................................................................................... 28 1.2 1.3 1.4 Section 2 CPU......................................................................................................41 2.1 Features................................................................................................................................ 41 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 42 2.1.2 Differences from H8/300 CPU ............................................................................... 43 2.1.3 Differences from H8/300H CPU ............................................................................ 44 CPU Operating Modes......................................................................................................... 45 2.2.1 Normal Mode.......................................................................................................... 45 2.2.2 Advanced Mode...................................................................................................... 47 Address Space...................................................................................................................... 49 Registers .............................................................................................................................. 50 2.4.1 General Registers.................................................................................................... 51 2.4.2 Program Counter (PC) ............................................................................................ 52 2.4.3 Extended Register (EXR) ....................................................................................... 52 2.4.4 Condition-Code Register (CCR)............................................................................. 53 2.4.5 Multiply-Accumulate Register (MAC)................................................................... 54 2.4.6 Initial Values of CPU Internal Registers................................................................. 54 Data Formats........................................................................................................................ 55 2.5.1 General Register Data Formats............................................................................... 55 2.5.2 Memory Data Formats ............................................................................................ 57 Instruction Set ...................................................................................................................... 58 2.6.1 Table of Instructions Classified by Function .......................................................... 59 2.6.2 Basic Instruction Formats ....................................................................................... 68 Addressing Modes and Effective Address Calculation........................................................ 69 2.7.1 Register Direct--Rn ............................................................................................... 70 2.7.2 Register Indirect--@ERn....................................................................................... 70 2.2 2.3 2.4 2.5 2.6 2.7 Rev. 1.00 Sep. 19, 2008 Page ix of xxviii 2.8 2.9 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn)................. 70 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn..... 71 2.7.5 Absolute Address--@aa:8 /@aa:16 / @aa:24 /@aa:32.......................................... 71 2.7.6 Immediate--#xx:8 / #xx:16/ #xx:32....................................................................... 72 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) ...................................... 72 2.7.8 Memory Indirect--@@aa:8 ................................................................................... 72 2.7.9 Effective Address Calculation ................................................................................ 74 Processing States.................................................................................................................. 76 Usage Note........................................................................................................................... 78 2.9.1 Usage Notes on Bit-wise Operation Instructions .................................................... 78 Section 3 MCU Operating Modes .......................................................................79 3.1 3.2 Operating Mode Selection ................................................................................................... 79 Register Descriptions ........................................................................................................... 80 3.2.1 Mode Control Register (MDCR) ............................................................................ 80 3.2.2 System Control Register (SYSCR)......................................................................... 80 Operating Mode Descriptions .............................................................................................. 82 3.3.1 Mode 1.................................................................................................................... 82 3.3.2 Mode 2.................................................................................................................... 82 3.3.3 Mode 3.................................................................................................................... 82 3.3.4 Mode 4.................................................................................................................... 83 3.3.5 Mode 7.................................................................................................................... 83 3.3.6 Pin Functions .......................................................................................................... 84 Memory Map in Each Operating Mode ............................................................................... 84 3.3 3.4 Section 4 Exception Handling ............................................................................. 91 4.1 4.2 4.3 Exception Handling Types and Priority............................................................................... 91 Exception Sources and Exception Vector Table .................................................................. 92 Reset .................................................................................................................................... 94 4.3.1 Reset Exception Handling ...................................................................................... 94 4.3.2 Interrupts after Reset............................................................................................... 96 4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 96 Trace Exception Handling ................................................................................................... 97 Interrupt Exception Handling .............................................................................................. 97 Trap Instruction Exception Handling................................................................................... 98 Illegal Instruction Exception Handling ................................................................................ 99 Stack Status after Exception Handling............................................................................... 100 Usage Note......................................................................................................................... 101 4.4 4.5 4.6 4.7 4.8 4.9 Rev. 1.00 Sep. 19, 2008 Page x of xxviii Section 5 Interrupt Controller ............................................................................103 5.1 5.2 5.3 Features.............................................................................................................................. 103 Input/Output Pins............................................................................................................... 105 Register Descriptions ......................................................................................................... 106 5.3.1 Interrupt Control Register (INTCR) ..................................................................... 107 5.3.2 Interrupt Priority Registers A to N (IPRA to IPRN)............................................. 108 5.3.3 IRQ Enable Register (IER) ................................................................................... 110 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 112 5.3.5 IRQ Status Register (ISR)..................................................................................... 118 5.3.6 IRQ Pin Select Register (ITSR)............................................................................ 119 5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 122 Interrupt Sources................................................................................................................ 123 5.4.1 External Interrupts ................................................................................................ 123 5.4.2 Internal Interrupts ................................................................................................. 124 Interrupt Exception Handling Vector Table....................................................................... 125 Interrupt Control Modes and Interrupt Operation .............................................................. 132 5.6.1 Interrupt Control Mode 0...................................................................................... 133 5.6.2 Interrupt Control Mode 2...................................................................................... 135 5.6.3 Interrupt Exception Handling Sequence ............................................................... 137 5.6.4 Interrupt Response Times ..................................................................................... 139 5.6.5 DTC and DMAC Activation by Interrupt ............................................................. 140 Usage Notes ....................................................................................................................... 141 5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 141 5.7.2 Instructions that Disable Interrupts....................................................................... 142 5.7.3 Times when Interrupts are Disabled ..................................................................... 142 5.7.4 Interrupts during Execution of EEPMOV Instruction .......................................... 142 5.7.5 Change of IRQ Pin Select Register (ITSR) Setting .............................................. 142 5.7.6 IRQ Status Register (ISR)..................................................................................... 143 5.4 5.5 5.6 5.7 Section 6 Bus Controller (BSC).........................................................................145 6.1 6.2 6.3 Features.............................................................................................................................. 145 Input/Output Pins............................................................................................................... 148 Register Descriptions ......................................................................................................... 151 6.3.1 Bus Width Control Register (ABWCR)................................................................ 152 6.3.2 Access State Control Register (ASTCR) .............................................................. 152 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) ........................................... 153 6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................. 159 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL).................... 161 Rev. 1.00 Sep. 19, 2008 Page xi of xxviii 6.4 6.5 6.6 6.7 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 163 6.3.7 Bus Control Register (BCR) ................................................................................. 164 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 166 6.3.9 DRAM Control Register (DRAMCR) .................................................................. 167 6.3.10 DRAM Access Control Register (DRACCR)....................................................... 175 6.3.11 Refresh Control Register (REFCR) ...................................................................... 178 6.3.12 Refresh Timer Counter (RTCNT)......................................................................... 181 6.3.13 Refresh Time Constant Register (RTCOR) .......................................................... 181 Bus Control........................................................................................................................ 182 6.4.1 Area Division........................................................................................................ 182 6.4.2 Bus Specifications ................................................................................................ 183 6.4.3 Memory Interfaces................................................................................................ 185 6.4.4 Chip Select Signals ............................................................................................... 187 Basic Bus Interface ............................................................................................................ 188 6.5.1 Data Size and Data Alignment.............................................................................. 188 6.5.2 Valid Strobes ........................................................................................................ 189 6.5.3 Basic Timing......................................................................................................... 190 6.5.4 Wait Control ......................................................................................................... 198 6.5.5 Read Strobe (RD) Timing..................................................................................... 199 6.5.6 Extension of Chip Select (CS) Assertion Period................................................... 201 Address/Data Multiplexed I/O Interface............................................................................ 202 6.6.1 Setting Address/Data Multiplexed I/O Space ....................................................... 202 6.6.2 Address/Data Multiplexing................................................................................... 202 6.6.3 Data Bus ............................................................................................................... 203 6.6.4 Address Hold Signal ............................................................................................. 203 6.6.5 Basic Timing......................................................................................................... 203 6.6.6 Wait Control ......................................................................................................... 212 6.6.7 Read Strobe (RD) Timing..................................................................................... 213 6.6.8 Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 214 DRAM Interface ................................................................................................................ 216 6.7.1 Setting DRAM Space............................................................................................ 216 6.7.2 Address Multiplexing ........................................................................................... 216 6.7.3 Data Bus ............................................................................................................... 217 6.7.4 Pins Used for DRAM Interface............................................................................. 218 6.7.5 Basic Timing......................................................................................................... 219 6.7.6 Column Address Output Cycle Control ................................................................ 221 6.7.7 Row Address Output State Control....................................................................... 222 6.7.8 Precharge State Control ........................................................................................ 224 6.7.9 Wait Control ......................................................................................................... 225 6.3.6 Rev. 1.00 Sep. 19, 2008 Page xii of xxviii 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.7.10 Byte Access Control ............................................................................................. 228 6.7.11 Burst Operation..................................................................................................... 229 6.7.12 Refresh Control..................................................................................................... 234 6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 240 Synchronous DRAM Interface........................................................................................... 243 6.8.1 Setting Continuous Synchronous DRAM Space................................................... 243 6.8.2 Address Multiplexing ........................................................................................... 244 6.8.3 Data Bus ............................................................................................................... 245 6.8.4 Pins Used for Synchronous DRAM Interface....................................................... 245 6.8.5 Synchronous DRAM Clock .................................................................................. 247 6.8.6 Basic Timing......................................................................................................... 247 6.8.7 CAS Latency Control............................................................................................ 249 6.8.8 Row Address Output State Control....................................................................... 251 6.8.9 Precharge State Count........................................................................................... 252 6.8.10 Bus Cycle Control in Write Cycle ........................................................................ 254 6.8.11 Byte Access Control ............................................................................................. 255 6.8.12 Burst Operation..................................................................................................... 258 6.8.13 Refresh Control..................................................................................................... 261 6.8.14 Mode Register Setting of Synchronous DRAM.................................................... 268 6.8.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface ............................................................................. 269 Burst ROM Interface.......................................................................................................... 274 6.9.1 Basic Timing......................................................................................................... 274 6.9.2 Wait Control ......................................................................................................... 276 6.9.3 Write Access......................................................................................................... 276 Idle Cycle........................................................................................................................... 277 6.10.1 Operation .............................................................................................................. 277 6.10.2 Pin States in Idle Cycle......................................................................................... 296 Write Data Buffer Function ............................................................................................... 297 Bus Release........................................................................................................................ 298 6.12.1 Operation .............................................................................................................. 298 6.12.2 Pin States in External Bus Released State ............................................................ 299 6.12.3 Transition Timing ................................................................................................. 300 Bus Arbitration .................................................................................................................. 302 6.13.1 Operation .............................................................................................................. 302 6.13.2 Bus Transfer Timing............................................................................................. 303 Bus Controller Operation in Reset ..................................................................................... 304 Usage Notes ....................................................................................................................... 305 6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 305 6.15.2 External Bus Release Function and Software Standby ......................................... 305 Rev. 1.00 Sep. 19, 2008 Page xiii of xxviii 6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 305 6.15.4 BREQO Output Timing ........................................................................................ 306 6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 306 Section 7 DMA Controller (DMAC).................................................................307 7.1 7.2 7.3 Features.............................................................................................................................. 307 Input/Output Pins............................................................................................................... 309 Register Descriptions ......................................................................................................... 310 7.3.1 Memory Address Registers (MARA and MARB)................................................ 312 7.3.2 I/O Address Registers (IOARA and IOARB)....................................................... 313 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 313 7.3.4 DMA Control Registers (DMACRA and DMACRB) .......................................... 315 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 323 7.3.6 DMA Write Enable Register (DMAWER)........................................................... 334 7.3.7 DMA Terminal Control Register (DMATCR) ..................................................... 336 Activation Sources............................................................................................................. 337 7.4.1 Activation by Internal Interrupt Request .............................................................. 338 7.4.2 Activation by Auto-Request ................................................................................. 339 Operation ........................................................................................................................... 339 7.5.1 Transfer Modes..................................................................................................... 339 7.5.2 Sequential Mode ................................................................................................... 342 7.5.3 Idle Mode.............................................................................................................. 345 7.5.4 Repeat Mode......................................................................................................... 348 7.5.5 Single Address Mode............................................................................................ 352 7.5.6 Normal Mode........................................................................................................ 355 7.5.7 Block Transfer Mode ............................................................................................ 359 7.5.8 Basic Bus Cycles .................................................................................................. 365 7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles................................................ 366 7.5.10 DMA Transfer (Single Address Mode) Bus Cycles ............................................. 374 7.5.11 Write Data Buffer Function .................................................................................. 380 7.5.12 Multi-Channel Operation...................................................................................... 381 7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC ............................................................................ 383 7.5.14 DMAC and NMI Interrupts .................................................................................. 384 7.5.15 Forced Termination of DMAC Operation ............................................................ 385 7.5.16 Clearing Full Address Mode................................................................................. 386 Interrupt Sources................................................................................................................ 387 Usage Notes ....................................................................................................................... 388 7.4 7.5 7.6 7.7 Rev. 1.00 Sep. 19, 2008 Page xiv of xxviii Section 8 EXDMA Controller (EXDMAC) ......................................................393 8.1 8.2 8.3 Features.............................................................................................................................. 393 Input/Output Pins............................................................................................................... 395 Register Descriptions ......................................................................................................... 396 8.3.1 EXDMA Source Address Register (EDSAR)....................................................... 396 8.3.2 EXDMA Destination Address Register (EDDAR)............................................... 397 8.3.3 EXDMA Transfer Count Register (EDTCR)........................................................ 397 8.3.4 EXDMA Mode Control Register (EDMDR) ........................................................ 399 8.3.5 EXDMA Address Control Register (EDACR) ..................................................... 404 Operation ........................................................................................................................... 408 8.4.1 Transfer Modes..................................................................................................... 408 8.4.2 Address Modes ..................................................................................................... 409 8.4.3 DMA Transfer Requests ....................................................................................... 413 8.4.4 Bus Modes ............................................................................................................ 414 8.4.5 Transfer Modes..................................................................................................... 416 8.4.6 Repeat Area Function ........................................................................................... 418 8.4.7 Registers during DMA Transfer Operation .......................................................... 421 8.4.8 Channel Priority Order.......................................................................................... 425 8.4.9 EXDMAC Bus Cycles (Dual Address Mode) ...................................................... 428 8.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 435 8.4.11 Examples of Operation Timing in Each Mode ..................................................... 440 8.4.12 Ending DMA Transfer .......................................................................................... 454 8.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 455 Interrupt Sources................................................................................................................ 456 Usage Notes ....................................................................................................................... 458 8.4 8.5 8.6 Section 9 Data Transfer Controller (DTC) ........................................................461 9.1 9.2 Features.............................................................................................................................. 461 Register Descriptions ......................................................................................................... 463 9.2.1 DTC Mode Register A (MRA) ............................................................................. 463 9.2.2 DTC Mode Register B (MRB).............................................................................. 465 9.2.3 DTC Source Address Register (SAR)................................................................... 465 9.2.4 DTC Destination Address Register (DAR)........................................................... 465 9.2.5 DTC Transfer Count Register A (CRA) ............................................................... 466 9.2.6 DTC Transfer Count Register B (CRB)................................................................ 466 9.2.7 DTC Enable Registers A to I (DTCERA to DTCERI) ......................................... 467 9.2.8 DTC Vector Register (DTVECR)......................................................................... 467 9.2.9 DTC Control Register (DTCCR) .......................................................................... 468 Activation Sources............................................................................................................. 469 Rev. 1.00 Sep. 19, 2008 Page xv of xxviii 9.3 9.4 9.5 9.6 9.7 9.8 Location of Register Information and DTC Vector Table ................................................. 471 Operation ........................................................................................................................... 475 9.5.1 Normal Mode........................................................................................................ 478 9.5.2 Repeat Mode......................................................................................................... 479 9.5.3 Block Transfer Mode ............................................................................................ 480 9.5.4 Chain Transfer ...................................................................................................... 481 9.5.5 Interrupt Sources................................................................................................... 482 9.5.6 Operation Timing.................................................................................................. 482 9.5.7 Number of DTC Execution States ........................................................................ 483 Procedures for Using DTC................................................................................................. 485 9.6.1 Activation by Interrupt.......................................................................................... 485 9.6.2 Activation by Software ......................................................................................... 485 Examples of Use of the DTC ............................................................................................. 486 9.7.1 Normal Mode........................................................................................................ 486 9.7.2 Chain Transfer ...................................................................................................... 487 9.7.3 Chain Transfer when Counter = 0......................................................................... 488 9.7.4 Software Activation .............................................................................................. 490 Usage Notes ....................................................................................................................... 491 9.8.1 Module Stop Mode Setting ................................................................................... 491 9.8.2 On-Chip RAM ...................................................................................................... 491 9.8.3 DTCE Bit Setting.................................................................................................. 491 9.8.4 DMAC Transfer End Interrupt.............................................................................. 491 9.8.5 Chain Transfer ...................................................................................................... 491 Section 10 I/O Ports........................................................................................... 493 10.1 Port 1.................................................................................................................................. 502 10.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 502 10.1.2 Port 1 Data Register (P1DR)................................................................................. 503 10.1.3 Port 1 Register (PORT1)....................................................................................... 503 10.1.4 Port 1 Open Drain Control Register (P1ODR) ..................................................... 504 10.1.5 Pin Functions ........................................................................................................ 504 10.2 Port 2.................................................................................................................................. 528 10.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 528 10.2.2 Port 2 Data Register (P2DR)................................................................................. 529 10.2.3 Port 2 Register (PORT2)....................................................................................... 529 10.2.4 Port 2 Open Drain Control Register (P2ODR) ..................................................... 530 10.2.5 Pin Functions ........................................................................................................ 531 10.3 Port 3.................................................................................................................................. 549 10.3.1 Port 3 Data Direction Register (P3DDR).............................................................. 549 10.3.2 Port 3 Data Register (P3DR)................................................................................. 550 Rev. 1.00 Sep. 19, 2008 Page xvi of xxviii 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.3.3 Port 3 Register (PORT3)....................................................................................... 550 10.3.4 Port 3 Open Drain Control Register (P3ODR) ..................................................... 551 10.3.5 Pin Functions ........................................................................................................ 551 Port 4.................................................................................................................................. 555 10.4.1 Port 4 Register (PORT4)....................................................................................... 555 10.4.2 Pin Functions ........................................................................................................ 555 Port 5.................................................................................................................................. 557 10.5.1 Port 5 Data Direction Register (P5DDR).............................................................. 557 10.5.2 Port 5 Data Register (P5DR)................................................................................. 557 10.5.3 Port 5 Register (PORT5)....................................................................................... 558 10.5.4 Port 5 Open Drain Control Register (P5ODR) ..................................................... 558 10.5.5 Pin Functions ........................................................................................................ 559 Port 6.................................................................................................................................. 566 10.6.1 Port 6 Data Direction Register (P6DDR).............................................................. 566 10.6.2 Port 6 Data Register (P6DR)................................................................................. 567 10.6.3 Port 6 Register (PORT6)....................................................................................... 567 10.6.4 Port 6 Open Drain Control Register (P6ODR) ..................................................... 568 10.6.5 Pin Functions ........................................................................................................ 568 Port 8.................................................................................................................................. 572 10.7.1 Port 8 Data Direction Register (P8DDR).............................................................. 572 10.7.2 Port 8 Data Register (P8DR)................................................................................. 573 10.7.3 Port 8 Register (PORT8)....................................................................................... 573 10.7.4 Port 8 Open Drain Control Register (P8ODR) ..................................................... 574 10.7.5 Pin Functions ........................................................................................................ 574 Port 9.................................................................................................................................. 584 10.8.1 Port 9 Register (PORT9)....................................................................................... 584 10.8.2 Pin Functions ........................................................................................................ 585 Port A................................................................................................................................. 587 10.9.1 Port A Data Direction Register (PADDR)............................................................ 588 10.9.2 Port A Data Register (PADR)............................................................................... 589 10.9.3 Port A Register (PORTA)..................................................................................... 589 10.9.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................. 590 10.9.5 Port A Open Drain Control Register (PAODR).................................................... 590 10.9.6 Pin Functions ........................................................................................................ 591 10.9.7 Port A Input Pull-Up MOS States......................................................................... 600 Port B ................................................................................................................................. 601 10.10.1 Port B Data Direction Register (PBDDR) ............................................................ 601 10.10.2 Port B Data Register (PBDR) ............................................................................... 602 10.10.3 Port B Register (PORTB) ..................................................................................... 602 10.10.4 Port B Pull-Up MOS Control Register (PBPCR) ................................................. 603 Rev. 1.00 Sep. 19, 2008 Page xvii of xxviii 10.11 10.12 10.13 10.14 10.15 10.10.5 Port B Open Drain Control Register (PBODR) .................................................... 603 10.10.6 Pin Functions ........................................................................................................ 604 10.10.7 Port B Input Pull-Up MOS States......................................................................... 612 Port C ................................................................................................................................. 613 10.11.1 Port C Data Direction Register (PCDDR) ............................................................ 613 10.11.2 Port C Data Register (PCDR) ............................................................................... 614 10.11.3 Port C Register (PORTC) ..................................................................................... 614 10.11.4 Port C Pull-Up MOS Control Register (PCPCR) ................................................. 615 10.11.5 Port C Open Drain Control Register (PCODR) .................................................... 615 10.11.6 Pin Functions ........................................................................................................ 616 10.11.7 Port C Input Pull-Up MOS States......................................................................... 624 Port D................................................................................................................................. 625 10.12.1 Port D Data Direction Register (PDDDR)............................................................ 625 10.12.2 Port D Data Register (PDDR)............................................................................... 626 10.12.3 Port D Register (PORTD)..................................................................................... 626 10.12.4 Port D Pull-Up MOS Control Register (PDPCR) ................................................. 627 10.12.5 Port D Open Drain Control Register (PDODR).................................................... 627 10.12.6 Pin Functions ........................................................................................................ 628 10.12.7 Port D Input Pull-Up MOS States......................................................................... 628 Port E ................................................................................................................................. 629 10.13.1 Port E Data Direction Register (PEDDR)............................................................. 629 10.13.2 Port E Data Register (PEDR)................................................................................ 630 10.13.3 Port E Register (PORTE)...................................................................................... 630 10.13.4 Port E Pull-Up MOS Control Register (PEPCR).................................................. 631 10.13.5 Port E Open Drain Control Register (PEODR) .................................................... 631 10.13.6 Pin Functions ........................................................................................................ 632 10.13.7 Port E Input Pull-Up MOS States ......................................................................... 632 Port F ................................................................................................................................. 633 10.14.1 Port F Data Direction Register (PFDDR) ............................................................. 634 10.14.2 Port F Data Register (PFDR) ................................................................................ 635 10.14.3 Port F Register (PORTF) ...................................................................................... 635 10.14.4 Port F Open Drain Control Register (PFODR) ..................................................... 636 10.14.5 Pin Functions ........................................................................................................ 636 Port G................................................................................................................................. 647 10.15.1 Port G Data Direction Register (PGDDR)............................................................ 647 10.15.2 Port G Data Register (PGDR)............................................................................... 648 10.15.3 Port G Register (PORTG)..................................................................................... 648 10.15.4 Port G Open Drain Control Register (PGODR).................................................... 649 10.15.5 Pin Functions ........................................................................................................ 650 Rev. 1.00 Sep. 19, 2008 Page xviii of xxviii 10.16 Port H................................................................................................................................. 654 10.16.1 Port H Data Direction Register (PHDDR)............................................................ 654 10.16.2 Port H Data Register (PHDR)............................................................................... 656 10.16.3 Port H Register (PORTH)..................................................................................... 656 10.16.4 Port H Open Drain Control Register (PHODR).................................................... 657 10.16.5 Pin Functions ........................................................................................................ 658 10.17 Port J .................................................................................................................................. 661 10.17.1 Port J Data Direction Register (PJDDR)............................................................... 661 10.17.2 Port J Data Register (PJDR) ................................................................................. 661 10.17.3 Port J Register (PORTJ) ....................................................................................... 662 10.17.4 Port J Open Drain Control Register (PJODR) ...................................................... 662 10.17.5 Pin Functions ........................................................................................................ 663 10.18 Port Function Control Registers......................................................................................... 664 10.18.1 Port Function Control Register 0 (PFCR0)........................................................... 664 10.18.2 Port Function Control Register 1 (PFCR1)........................................................... 665 10.18.3 Port Function Control Register 2 (PFCR2)........................................................... 667 10.18.4 Port Function Control Register 3 (PFCR3)........................................................... 668 10.18.5 Port Function Control Register 4 (PFCR4)........................................................... 669 10.18.6 Port Function Control Register 5 (PFCR5)........................................................... 671 Section 11 16-Bit Timer Pulse Unit (TPU) .......................................................673 11.1 Features.............................................................................................................................. 673 11.2 Input/Output Pins............................................................................................................... 680 11.3 Register Descriptions ......................................................................................................... 683 11.3.1 Timer Control Register (TCR).............................................................................. 688 11.3.2 Timer Mode Register (TMDR)............................................................................. 693 11.3.3 Timer I/O Control Register (TIOR)...................................................................... 694 11.3.4 Timer Interrupt Enable Register (TIER)............................................................... 712 11.3.5 Timer Status Register (TSR)................................................................................. 714 11.3.6 Timer Counter (TCNT)......................................................................................... 717 11.3.7 Timer General Register (TGR) ............................................................................. 717 11.3.8 Timer Start Register (TSTR) ................................................................................ 717 11.3.9 Timer Synchronous Register (TSYR)................................................................... 718 11.3.10 Timer Start Register B (TSTRB) .......................................................................... 719 11.3.11 Timer Synchronous Register B (TSYRB) ............................................................ 720 11.4 Operation ........................................................................................................................... 721 11.4.1 Basic Functions..................................................................................................... 721 11.4.2 Synchronous Operation......................................................................................... 728 11.4.3 Buffer Operation................................................................................................... 731 11.4.4 Cascaded Operation .............................................................................................. 735 Rev. 1.00 Sep. 19, 2008 Page xix of xxviii 11.5 11.6 11.7 11.8 11.9 11.10 11.4.5 PWM Modes......................................................................................................... 737 11.4.6 Phase Counting Mode......................................................................................... 743 Interrupt Sources................................................................................................................ 750 DTC Activation.................................................................................................................. 753 DMAC Activation.............................................................................................................. 753 A/D Converter Activation.................................................................................................. 754 Operation Timing............................................................................................................... 754 11.9.1 Input/Output Timing ........................................................................................... 754 11.9.2 Interrupt Signal Timing ...................................................................................... 758 Usage Notes ....................................................................................................................... 762 11.10.1 Module Stop Mode Setting ................................................................................. 762 11.10.2 Input Clock Restrictions ..................................................................................... 762 11.10.3 Caution on Cycle Setting .................................................................................... 763 11.10.4 Contention between TCNT Write and Clear Operations .................................... 763 11.10.5 Contention between TCNT Write and Increment Operations............................. 764 11.10.6 Contention between TGR Write and Compare Match ........................................ 765 11.10.7 Contention between Buffer Register Write and Compare Match ....................... 766 11.10.8 Contention between TGR Read and Input Capture............................................. 767 11.10.9 Contention between TGR Write and Input Capture............................................ 768 11.10.10 Contention between Buffer Register Write and Input Capture ........................... 769 11.10.11 Contention between Overflow/Underflow and Counter Clearing....................... 770 11.10.12 Contention between TCNT Write and Overflow/Underflow.............................. 771 11.10.13 Multiplexing of I/O Pins ..................................................................................... 771 11.10.14 Interrupts and Module Stop Mode ...................................................................... 771 Section 12 Programmable Pulse Generator (PPG) ............................................ 773 12.1 Features.............................................................................................................................. 773 12.2 Input/Output Pins............................................................................................................... 775 12.3 Register Descriptions ......................................................................................................... 775 12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ....................................... 776 12.3.2 Output Data Registers H, L (PODRH, PODRL)................................................. 777 12.3.3 Next Data Registers H, L (NDRH, NDRL) ........................................................ 778 12.3.4 PPG Output Control Register (PCR) .................................................................. 781 12.3.5 PPG Output Mode Register (PMR) .................................................................... 782 12.4 Operation ........................................................................................................................... 784 12.4.1 Output Timing .................................................................................................... 785 12.4.2 Sample Setup Procedure for Normal Pulse Output............................................. 786 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)......... 787 12.4.4 Non-Overlapping Pulse Output........................................................................... 788 12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ............................. 790 Rev. 1.00 Sep. 19, 2008 Page xx of xxviii 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) .................. 791 12.4.7 Inverted Pulse Output ........................................................................................... 793 12.4.8 Pulse Output Triggered by Input Capture ............................................................. 794 12.5 Usage Notes ....................................................................................................................... 795 12.5.1 Module Stop Mode Setting ................................................................................... 795 12.5.2 Operation of Pulse Output Pins............................................................................. 795 Section 13 8-Bit Timers (TMR).........................................................................797 13.1 Features.............................................................................................................................. 797 13.2 Input/Output Pins............................................................................................................... 799 13.3 Register Descriptions ......................................................................................................... 799 13.3.1 Timer Counter (TCNT)......................................................................................... 800 13.3.2 Time Constant Register A (TCORA).................................................................... 800 13.3.3 Time Constant Register B (TCORB) .................................................................... 800 13.3.4 Timer Control Register (TCR).............................................................................. 801 13.3.5 Timer Counter Control Register (TCCR) ............................................................. 802 13.3.6 Timer Control/Status Register (TCSR)................................................................. 804 13.4 Operation ........................................................................................................................... 808 13.4.1 Pulse Output.......................................................................................................... 808 13.4.2 Reset Input ............................................................................................................ 809 13.5 Operation Timing............................................................................................................... 810 13.5.1 TCNT Incrementation Timing .............................................................................. 810 13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 811 13.5.3 Timing of Timer Output when Compare-Match Occurs....................................... 812 13.5.4 Timing of Compare Match Clear.......................................................................... 812 13.5.5 Timing of TCNT External Reset........................................................................... 813 13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 813 13.6 Operation with Cascaded Connection................................................................................ 814 13.6.1 16-Bit Counter Mode ............................................................................................ 814 13.6.2 Compare Match Count Mode................................................................................ 814 13.7 Interrupt Sources................................................................................................................ 815 13.7.1 Interrupt Sources and DTC Activation ................................................................. 815 13.7.2 A/D Converter Activation..................................................................................... 815 13.8 Usage Notes ....................................................................................................................... 816 13.8.1 Contention between TCNT Write and Clear......................................................... 816 13.8.2 Contention between TCNT Write and Increment ................................................. 817 13.8.3 Contention between TCOR Write and Compare Match ....................................... 818 13.8.4 Contention between Compare Matches A and B .................................................. 819 13.8.5 Switching of Internal Clocks and TCNT Operation ............................................. 819 Rev. 1.00 Sep. 19, 2008 Page xxi of xxviii 13.8.6 Mode Setting with Cascaded Connection ............................................................. 821 13.8.7 Module Stop Mode Setting ................................................................................... 821 13.8.8 Interrupts in Module Stop Mode........................................................................... 821 Section 14 Watchdog Timer (WDT) ................................................................. 823 14.1 Features.............................................................................................................................. 823 14.2 Input/Output Pin ................................................................................................................ 824 14.3 Register Descriptions ......................................................................................................... 825 14.3.1 Timer Counter (TCNT)......................................................................................... 825 14.3.2 Timer Control/Status Register (TCSR)................................................................. 825 14.3.3 Reset Control/Status Register (RSTCSR)............................................................. 827 14.4 Operation ........................................................................................................................... 828 14.4.1 Watchdog Timer Mode......................................................................................... 828 14.4.2 Interval Timer Mode............................................................................................. 829 14.5 Interrupt Source ................................................................................................................. 831 14.6 Usage Notes ....................................................................................................................... 831 14.6.1 Notes on Register Access ..................................................................................... 831 14.6.2 Contention between Timer Counter (TCNT) Write and Increment ...................... 833 14.6.3 Changing Value of CKS2 to CKS0 ...................................................................... 833 14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 833 14.6.5 Internal Reset in Watchdog Timer Mode.............................................................. 834 14.6.6 System Reset by WDTOVF Signal....................................................................... 834 Section 15 Serial Communication Interface (SCI, IrDA) ................................. 835 15.1 Features.............................................................................................................................. 835 15.2 Input/Output Pins............................................................................................................... 838 15.3 Register Descriptions ......................................................................................................... 839 15.3.1 Receive Shift Register (RSR) ............................................................................... 840 15.3.2 Receive Data Register (RDR)............................................................................... 840 15.3.3 Transmit Data Register (TDR).............................................................................. 841 15.3.4 Transmit Shift Register (TSR) .............................................................................. 841 15.3.5 Serial Mode Register (SMR) ................................................................................ 841 15.3.6 Serial Control Register (SCR) .............................................................................. 845 15.3.7 Serial Status Register (SSR) ................................................................................. 850 15.3.8 Smart Card Mode Register (SCMR)..................................................................... 858 15.3.9 Bit Rate Register (BRR) ....................................................................................... 859 15.3.10 IrDA Control Register (IrCR)............................................................................... 866 15.3.11 Serial Extension Mode Register (SEMR) ............................................................. 867 15.4 Operation in Asynchronous Mode ..................................................................................... 869 15.4.1 Data Transfer Format............................................................................................ 869 Rev. 1.00 Sep. 19, 2008 Page xxii of xxviii 15.5 15.6 15.7 15.8 15.9 15.10 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ............................................................................................. 871 15.4.3 Clock..................................................................................................................... 872 15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 873 15.4.5 Data Transmission (Asynchronous Mode) ........................................................... 874 15.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 876 Multiprocessor Communication Function.......................................................................... 880 15.5.1 Multiprocessor Serial Data Transmission ............................................................. 881 15.5.2 Multiprocessor Serial Data Reception .................................................................. 883 Operation in Clocked Synchronous Mode ......................................................................... 887 15.6.1 Clock..................................................................................................................... 887 15.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 888 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 888 15.6.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 891 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) .............................................................................. 893 Operation in Smart Card Interface Mode........................................................................... 895 15.7.1 Pin Connection Example ...................................................................................... 895 15.7.2 Data Format (Except for Block Transfer Mode)................................................... 896 15.7.3 Block Transfer Mode ............................................................................................ 897 15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 898 15.7.5 Initialization.......................................................................................................... 900 15.7.6 Data Transmission (Except for Block Transfer Mode)......................................... 900 15.7.7 Serial Data Reception (Except for Block Transfer Mode).................................... 904 15.7.8 Clock Output Control............................................................................................ 906 IrDA Operation .................................................................................................................. 908 Interrupt Sources................................................................................................................ 911 15.9.1 Interrupts in Normal Serial Communication Interface Mode ............................... 911 15.9.2 Interrupts in Smart Card Interface Mode .............................................................. 913 Usage Notes ....................................................................................................................... 915 15.10.1 Module Stop Mode Setting ................................................................................... 915 15.10.2 Break Detection and Processing ........................................................................... 915 15.10.3 Mark State and Break Sending ............................................................................. 915 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 915 15.10.5 Relation between Writes to TDR and the TDRE Flag .......................................... 916 15.10.6 Restrictions on Use of DMAC or DTC................................................................. 916 15.10.7 Operation in Case of Mode Transition.................................................................. 917 Rev. 1.00 Sep. 19, 2008 Page xxiii of xxviii Section 16 I2C Bus Interface 2 (IIC2)................................................................ 921 16.1 Features.............................................................................................................................. 921 16.2 Input/Output Pins............................................................................................................... 923 16.3 Register Descriptions ......................................................................................................... 924 16.3.1 I2C Bus Control Register A (ICCRA) ................................................................... 926 16.3.2 I2C Bus Control Register B (ICCRB) ................................................................... 928 16.3.3 I2C Bus Mode Register (ICMR)............................................................................ 929 16.3.4 I2C Bus Interrupt Enable Register (ICIER)........................................................... 931 16.3.5 I2C Bus Status Register (ICSR)............................................................................. 933 16.3.6 Slave Address Register (SAR).............................................................................. 935 16.3.7 I2C Bus Transmit Data Register (ICDRT) ............................................................ 936 16.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 936 16.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 936 16.4 Operation ........................................................................................................................... 937 16.4.1 I2C Bus Format...................................................................................................... 937 16.4.2 Master Transmit Operation................................................................................... 938 16.4.3 Master Receive Operation .................................................................................... 940 16.4.4 Slave Transmit Operation ..................................................................................... 942 16.4.5 Slave Receive Operation....................................................................................... 945 16.4.6 Noise Canceler...................................................................................................... 947 16.4.7 Example of Use..................................................................................................... 947 16.5 Interrupt Request................................................................................................................ 952 16.6 Bit Synchronous Circuit..................................................................................................... 953 16.7 Usage Notes ....................................................................................................................... 954 Section 17 A/D Converter ................................................................................. 955 17.1 Features.............................................................................................................................. 955 17.2 Input/Output Pins............................................................................................................... 958 17.3 Register Descriptions ......................................................................................................... 960 17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 961 17.3.2 A/D Control/Status Register for Unit 0 (ADCSR_0)............................................ 963 17.3.3 A/D Control/Status Register for Unit 1 (ADCSR_1)............................................ 965 17.3.4 A/D Control Register (ADCR_0) Unit 0 .............................................................. 968 17.3.5 A/D Control Register (ADCR_1) Unit 1 .............................................................. 970 17.4 Operation ........................................................................................................................... 972 17.4.1 Single Mode.......................................................................................................... 972 17.4.2 Scan Mode ............................................................................................................ 974 17.4.3 Input Sampling and A/D Conversion Time .......................................................... 978 17.4.4 External Trigger Input Timing.............................................................................. 980 Rev. 1.00 Sep. 19, 2008 Page xxiv of xxviii 17.5 Interrupt Source ................................................................................................................. 981 17.6 A/D Conversion Accuracy Definitions .............................................................................. 982 17.7 Usage Notes ....................................................................................................................... 984 17.7.1 Module Stop Function Setting .............................................................................. 984 17.7.2 A/D Input Hold Function in Software Standby Mode .......................................... 984 17.7.3 Restarting the A/D Converter ............................................................................... 984 17.7.4 Permissible Signal Source Impedance .................................................................. 985 17.7.5 Influences on Absolute Accuracy ......................................................................... 986 17.7.6 Setting Range of Analog Power Supply and Other Pins....................................... 986 17.7.7 Notes on Board Design ......................................................................................... 987 17.7.8 Notes on Noise Countermeasures ......................................................................... 987 Section 18 D/A Converter..................................................................................989 18.1 Features.............................................................................................................................. 989 18.2 Input/Output Pins............................................................................................................... 991 18.3 Register Descriptions ......................................................................................................... 992 18.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)............................................. 992 18.3.2 D/A Control Register 23 (DACR23) .................................................................... 992 18.4 Operation ........................................................................................................................... 995 18.5 Usage Notes ....................................................................................................................... 997 18.5.1 Setting for Module Stop Mode ............................................................................. 997 18.5.2 D/A Output Hold Function in Software Standby Mode........................................ 997 Section 19 Synchronous Serial Communication Unit (SSU) ............................999 19.1 Features.............................................................................................................................. 999 19.2 Input/Output Pins............................................................................................................. 1001 19.3 Register Descriptions ....................................................................................................... 1001 19.3.1 SS Control Register H (SSCRH) ........................................................................ 1002 19.3.2 SS Control Register L (SSCRL) ......................................................................... 1004 19.3.3 SS Mode Register (SSMR) ................................................................................. 1005 19.3.4 SS Enable Register (SSER) ................................................................................ 1006 19.3.5 SS Status Register (SSSR).................................................................................. 1007 19.3.6 SS Control Register 2 (SSCR2) .......................................................................... 1010 19.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................. 1012 19.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................. 1013 19.3.9 SS Shift Register (SSTRSR)............................................................................... 1013 19.4 Operation ......................................................................................................................... 1014 19.4.1 Transfer Clock .................................................................................................... 1014 19.4.2 Relationship of Clock Phase, Polarity, and Data ................................................ 1014 19.4.3 Relationship between Data Input/Output Pins and Shift Register ...................... 1015 Rev. 1.00 Sep. 19, 2008 Page xxv of xxviii 19.4.4 Communication Modes and Pin Functions ......................................................... 1016 19.4.5 SSU Mode........................................................................................................... 1018 19.4.6 SCS Pin Control and Conflict Error.................................................................... 1029 19.4.7 Clock Synchronous Communication Mode ........................................................ 1030 19.5 Interrupt Requests ............................................................................................................ 1037 19.6 Usage Note....................................................................................................................... 1037 19.6.1 Setting of Module Stop Mode............................................................................. 1037 Section 20 RAM ..............................................................................................1039 Section 21 Flash Memory................................................................................1041 21.1 Memory Map ................................................................................................................... 1043 21.1.1 Boot Mode .......................................................................................................... 1043 21.2 Register Descriptions ....................................................................................................... 1044 21.2.1 Flash Memory Control Register 1 (FLMCR1).................................................... 1045 21.2.2 Flash Memory Data Block Protect Register (DFPR) .......................................... 1046 21.2.3 Flash Memory Status Register (FLMSTR)......................................................... 1047 21.3 On-Board Programming Mode ........................................................................................ 1048 21.3.1 SCI Boot Mode ................................................................................................... 1049 21.3.2 User Programming Mode.................................................................................... 1050 21.3.3 EW0 Mode.......................................................................................................... 1051 21.4 Notes on User Programming Mode ................................................................................. 1052 21.4.1 Prohibited Interrupts (EW0 Mode) ..................................................................... 1052 21.4.2 Access Method.................................................................................................... 1052 21.4.3 Programming (EW0 Mode) ................................................................................ 1052 21.4.4 Writing Commands or Data ................................................................................ 1052 21.4.5 Software Standby Mode...................................................................................... 1052 21.5 Software Commands........................................................................................................ 1053 21.5.1 Read Array.......................................................................................................... 1054 21.5.2 Read Status Register ........................................................................................... 1054 21.5.3 Clear Status Register........................................................................................... 1054 21.5.4 Program .............................................................................................................. 1054 21.5.5 Block Erase......................................................................................................... 1056 21.5.6 Block Blank Check ............................................................................................. 1058 21.6 Status Register ................................................................................................................. 1059 21.6.1 Sequencer Status (FMRDY Bit) ......................................................................... 1060 21.6.2 Erase Status (FMERSF Bit) ................................................................................ 1060 21.6.3 Programming Status (FMPRSF Bit) ................................................................... 1060 21.7 Full Status Check ............................................................................................................. 1061 21.8 Programmer Mode ........................................................................................................... 1063 Rev. 1.00 Sep. 19, 2008 Page xxvi of xxviii 21.9 Serial Communication Interface Specification for Boot Mode........................................ 1064 Section 22 Boundary Scan (JTAG) .................................................................1089 Section 23 Clock Pulse Generator ...................................................................1091 23.1 Register Descriptions ....................................................................................................... 1092 23.1.1 System Clock Control Register (SCKCR) .......................................................... 1092 23.1.2 PLL Control Register (PLLCR).......................................................................... 1094 23.2 Oscillator.......................................................................................................................... 1095 23.2.1 Connecting a Crystal Resonator.......................................................................... 1095 23.2.2 External Clock Input........................................................................................... 1096 23.3 System-Clock PLL Circuit and Divider........................................................................... 1098 23.4 Usage Notes ..................................................................................................................... 1099 23.4.1 Notes on Clock Pulse Generator ......................................................................... 1099 23.4.2 Notes on Resonator............................................................................................. 1099 23.4.3 Notes on Board Design ....................................................................................... 1100 Section 24 Power-Down Modes ......................................................................1101 24.1 Register Descriptions ....................................................................................................... 1105 24.1.1 Standby Control Register (SBYCR) ................................................................... 1105 24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................. 1107 24.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) ........................................................................ 1108 24.1.4 RAM Module Stop Control Registers H and L (RMMSTPCRH, RMMSTPCRL)....................................................................... 1109 24.2 Operation ......................................................................................................................... 1110 24.2.1 Clock Division Mode.......................................................................................... 1110 24.2.2 Sleep Mode ......................................................................................................... 1111 24.2.3 Software Standby Mode...................................................................................... 1112 24.2.4 Hardware Standby Mode .................................................................................... 1115 24.2.5 Module Stop Function ........................................................................................ 1116 24.2.6 All Module Clocks Stop Mode ........................................................................... 1117 24.3 Clock Output Control.................................................................................................... 1118 24.4 SDRAM Clock Output Control ..................................................................................... 1119 24.5 Usage Notes ..................................................................................................................... 1120 24.5.1 I/O Port Status..................................................................................................... 1120 24.5.2 Current Dissipation during Oscillation Stabilization Standby Period................. 1120 24.5.3 EXDMAC, DMAC, and DTC Module Stop....................................................... 1120 24.5.4 On-Chip Peripheral Module Interrupts ............................................................... 1120 24.5.5 Writing to MSTPCR, EXMSTPCR, and RMMSTPCR...................................... 1120 Rev. 1.00 Sep. 19, 2008 Page xxvii of xxviii 24.5.6 Notes on Clock Division Mode........................................................................... 1121 Section 25 List of Registers............................................................................. 1123 25.1 Register Addresses (Address Order)................................................................................ 1124 25.2 Register Bits..................................................................................................................... 1140 25.3 Register States in Each Operating Mode ......................................................................... 1160 Section 26 Electrical Characteristics ...............................................................1175 26.1 Electrical Characteristics for H8S/2426 Group and H8S/2426R Group .......................... 1175 26.1.1 Absolute Maximum Ratings ............................................................................... 1175 26.1.2 DC Characteristics .............................................................................................. 1176 26.1.3 AC Characteristics .............................................................................................. 1180 26.1.4 A/D Conversion Characteristics ......................................................................... 1189 26.1.5 D/A Conversion Characteristics ......................................................................... 1190 26.1.6 Flash Memory Characteristics ............................................................................ 1191 26.2 Electrical Characteristics for H8S/2424 Group................................................................ 1193 26.2.1 Absolute Maximum Ratings ............................................................................... 1193 26.2.2 DC Characteristics .............................................................................................. 1194 26.2.3 AC Characteristics .............................................................................................. 1198 26.2.4 A/D Conversion Characteristics ......................................................................... 1206 26.2.5 D/A Conversion Characteristics ......................................................................... 1207 26.2.6 Flash Memory Characteristics ............................................................................ 1208 26.3 Timing Charts .................................................................................................................. 1210 26.3.1 Clock Timing ...................................................................................................... 1210 26.3.2 Control Signal Timing ........................................................................................ 1212 26.3.3 Bus Timing ......................................................................................................... 1213 26.3.4 DMAC and EXDMAC Timing........................................................................... 1231 26.3.5 Timing of On-Chip Peripheral Modules ............................................................. 1236 Appendix A. B. C. .......................................................................................................1243 Port States in Each Processing State ................................................................................ 1243 Product Code Lineup ....................................................................................................... 1261 Package Dimensions ........................................................................................................ 1262 Index .......................................................................................................1265 Rev. 1.00 Sep. 19, 2008 Page xxviii of xxviii Section 1 Overview Section 1 Overview 1.1 Features The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group are CISC (Complex Instruction Set Computer) microprocessors that integrate an H8S/2600 CPU core, which has an internal 16-bit architecture and is upward-compatible with Renesas Technology original H8/300, H8/300H, and H8S CPUs. The on-chip peripheral functions provided for enabling system configuration at a low cost are the DMA controller, EXDMA controller*, data transfer controller, serial communication interface, I2C bus interface 2, synchronous serial communication unit, A/D converter, D/A converter, and various timers. On-chip ROM is flash memory whose size is 256 Kbytes and 128 Kbytes. Note: * Not supported by the H8S/2424 Group. 1.1.1 Applications Application field examples: PC peripheral equipment, office automation equipment, consumer equipment, etc. 1.1.2 Overview of Specifications The specifications of this LSI are summarized in table 1.1. Rev. 1.00 Sep. 19, 2008 Page 1 of 1270 REJ09B0466-0100 Section 1 Overview Table 1.1 Type Memory Overview of Specifications Module/ Function ROM Description Expanded ROM: Flash memory version, 256 Kbytes and 128 Kbytes ROM-less version RAM RAM size: 64 Kbytes (in planning) and 48 Kbytes * 16-bit high-speed H8S/2600 CPU (CISC type) Upward-compatible with H8/300, H8/300H, and H8S CPUs on an object level * * * * General register mode (Sixteen 16-bit general registers) Eight addressing modes Address space: 4 Gbytes (program: 4 Gbytes, data: 4 Gbytes) Number of basic instructions 69 types (arithmetic and logic, multiply and divide, bitmanipulation, and multiply-and-accumulate instructions) * Minimum instruction execution time (ns) 30.3 ns when system clock = 33 MHz and Vcc = 3.0 to 3.6 V (ADD instruction) * * Operating mode Multiplier is included (16 x 16 32 bits) Multiply-and-accumulate instructions are supported (16 x 16 + 32 32 bits) CPU CPU Advanced mode Rev. 1.00 Sep. 19, 2008 Page 2 of 1270 REJ09B0466-0100 Section 1 Overview Type CPU Module/ Function MCU operating mode Description * Mode 1: Expanded mode with on-chip ROM disabled, 16-bit bus (MD2 and MD1 pins are low and MD0 pin is high) Expanded mode with on-chip ROM disabled, 8-bit bus (MD2 pin is low, MD1 pin is high, and MD0 pin is low) Boot mode (MD2 pin is low and MD1 and MD0 pins are high) Expanded mode with on-chip ROM enabled, 8-bit bus (MD2 pin is high and MD1 and MD0 pins are low) Single-chip mode (MD2, MD1, and MD0 pins are high) * Mode 2: * * Mode 3: Mode 4: * * Interrupts (sources) Interrupt controller * Mode 7: Power-down modes (a power-down mode is entered when the SLEEP instruction is executed) External interrupt pins H8S/2426 Group, H8S/2426R Group: 33 pins (NMI, IRQ15-A to IRQ0-A, IRQ15-B to IRQ0-B) H8S/2424 Group: 17 pins (NMI, IRQ7-A to IRQ0-A, IRQ7-B to IRQ0-B) * Internal interrupt sources H8S/2426 Group, H8S/2426R Group: 102 sources H8S/2424 Group: 100 sources * * * DMA DMA controller (DMAC) * * * * * Two interrupt control modes (specified by the interrupt control register) Eight priority levels can be set (specified by the interrupt priority registers) Independent vector addresses DMA transfer is possible on four channels Three activation sources (auto-request, on-chip module interrupt, and external request) Byte or word can be set as the transfer unit Short address mode or full address mode can be selected 16-Mbyte address space can be specified directly Rev. 1.00 Sep. 19, 2008 Page 3 of 1270 REJ09B0466-0100 Section 1 Overview Type DMA Module/ Function EXDMA controller (EXDMAC) Description * * * * * DMA transfer is possible on two channels Two activation sources (auto-request and external request) Two transfer modes (normal mode and block transfer mode) Dual address mode or single address mode can be selected 16-Mbyte address space can be specified directly * Repeat area can be set Note: * EXDMAC is supported only by the H8S/2426 Group and H8S/2426R Group. Data transfer controller (DTC) * * * * * External bus extension Bus controller (BSC) * * Transfer is possible on any number of channels An interrupt source can trigger data transfer (chain transfer is possible) Three transfer modes (normal mode, repeat mode, and block transfer mode) Byte or word can be set as the transfer unit Activation by software is possible External address space: 16 Mbytes Manages the external address space divided into eight areas Chip select signals (CS0 to CS7) can be output 8-bit access or 16-bit access can be selected 2-state access or 3-state access can be selected Program wait states can be inserted * * Clock Clock pulse generator (CPG) * * External memory interfaces (burst ROM, DRAM, synchronous DRAM*1, address/data multiplexed I/O) Bus arbitration function (bus arbitration of the bus masters CPU, DTC, DMAC, and EXDMAC) This LSI has a single on-chip clock pulse generator circuit Consists of an oscillator, a system-clock PLL circuit, a divider, and the system clock frequency can be changed System clock () cycle: 8 to 33 MHz * Six power-down modes Divided clock mode, sleep mode, module stop function, all module clock stop mode, software standby mode, and hardware standby mode Rev. 1.00 Sep. 19, 2008 Page 4 of 1270 REJ09B0466-0100 Section 1 Overview Type A/D converter Module/ Function A/D converter (ADC) Description * * * Two units 10-bit resolution Number of input channels H8S/2426 Group and H8S/2426R Group: 16 channels Unit 0: 8 channels Unit 1: 8 channels H8S/2424 Group: 10 channels Unit 0: 8 channels Unit 1: 2 channels * * * * Sample and hold functionality Conversion time: 4.0 s per channel (when A/D conversion clock is set to 10 MHz) Two kinds of operating modes (single mode and scan mode) Three types of A/D conversion start (software, trigger by timer (TPU or TMR), or external trigger) Resolution (8 bits) x Number of output channels (2 channels) Conversion time: Maximum 10 s (with 20-pF load) Output voltage: 0 V to Vref 16-bit timer x 12 channels (general pulse timer unit) Eight counter input clocks can be selected for each channel Maximum 16-pulse input/output (when external expanded mode is set) Maximum 32-pulse input/output (when single-chip mode is set) Counter clear operation, simultaneous write to multiple timer counters (TCNT), simultaneous clearing by compare match and input capture, register simultaneous input/output possible by counter synchronous operation, and maximum of 15-phase PWM output by combination with synchronous operation Buffer operation, phase counting mode (two-phase encoder input), and cascaded operation settable for channels Input capture function Output compare function (waveform output at compare match) D/A converter D/A converter (DAC) * * * * * * * * Timer 16-bit timer pulse unit (TPU) * * * Rev. 1.00 Sep. 19, 2008 Page 5 of 1270 REJ09B0466-0100 Section 1 Overview Type Timer Module/ Function 8-bit timer (TMR) Description * * * 8-bit timer x 2 channels (operation as a 16-bit timer is also possible) Selection of seven clock sources: Six internal clock signals or an external clock input Pulse output with an arbitrary duty cycle or PWM output 16-bit pulse output Pulse outputs are divided into four groups Non-overlap mode is available Inverted output can be specified * Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) 8-bit timer x 1 channel (eight counter input clocks can be selected) Switchable between watchdog timer mode and interval timer mode Five channels (asynchronous or clocked synchronous serial communication mode) Full-duplex communication capability Choice of any bit rate and choice of LSB-first or MSB-first Programmable pulse generator (PPG) * * Watchdog timer Watchdog timer (WDT) * * Serial interface Serial communication interface (SCI) * * * Smart Card/SIM Highfunction communications SCI supports Smart Card (SIM) interface I2C bus interface 2 * (IIC2) * * * * * Synchronous serial * communication * unit (SSU) * * * Four channels Continuous transmission/reception Start and stop conditions generated automatically in master mode Selection of acknowledge output levels when receiving Automatic loading of acknowledge bit when transmitting Bit synchronization/wait function One channel Master mode or slave mode can be selected Standard mode or bidirectional mode can be selected Full-duplex communication capability Consecutive serial communication capability Rev. 1.00 Sep. 19, 2008 Page 6 of 1270 REJ09B0466-0100 Section 1 Overview Type I/O ports Module/ Function Description * * * * Input-only pins: 18 (144-pin version), 17 (145-pinersion)*2, 11 (120-pin version) Input/output pins: 96 (144-pin version or 145-pin version)*2, 83 (120-pin version) Pull-up resistor pins: 40 Open-drain pins: 91 144-pin QFP package (PLQP0144KA-A) (code: FP-144LV, body size: 20 x 20 mm, pin pitch: 0.50 mm) * * * 145-pin TLP package (PTLG0145JB-A) (body size: 9 x 9 mm, pin pitch: 0.65 mm) 120-pin QFP package (PLQP0120LA-A) (code: FP-120BV, body size: 14 x 14 mm, pin pitch: 0.40 mm) Pb-free package Operating frequency: 8 to 33 MHz Power supply voltage: VCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V Current consumption: 55 mA typ. (VCC = 3.3 V, AVCC = 3.3 V, = 33 MHz) Package * Operating frequency/ power supply voltage * * * Operating environment temperature (C) Note: -20C to +75C (regular specifications) 1. Supported only by the H8S/2426R Group. 2. Note that the function of 145-pin version partly differs from that of 144-pin version. Rev. 1.00 Sep. 19, 2008 Page 7 of 1270 REJ09B0466-0100 Section 1 Overview 1.2 List of Products Table 1.2 lists the products and figure 1.1 shows how to read the product type name. Table 1.2 Products ROM Size 256 Kbytes 128 Kbytes 256 Kbytes 128 Kbytes Note: * In planning RAM Size 64 Kbytes 48 Kbytes 64 Kbytes 48 Kbytes Package PLQP0144KA-A PTLG0145JB-A* PLQP0120LA-A Flash memory version Remarks Flash memory version Product Type Name R4F2426 R4F2426R R4F2424 Product type name R 4 F 2426 8 Indicates memory size classification: On-chip memory size Indicates "product original type number": H8S/2426 Indicates the ROM device type: F: On-chip ROM S: ROM-less Indicates the product classification: Microprocessor Indicates "Renesas semiconductor" Figure 1.1 Meaning of Product Type Name Rev. 1.00 Sep. 19, 2008 Page 8 of 1270 REJ09B0466-0100 Section 1 Overview 1.3 Block Diagrams PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 PE7/D7/AD7 PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 Vcc Vcc Vcc Vcc PLLVcc PLLVss Vss Vss Vss Vss Vss Vss Vss Vss VCL Port D MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF/TDO*3 NMI BSCANE*3 Port E JTAG*3 (boundary scan) PA7/A23/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 System clock PLL Clock pulse generator Internal data bus H8S/2600 CPU Internal address bus Port A P65/IRQ13-A/DACK1/TMO1-A P64/IRQ12-A/DACK0/TMO0-A P63/IRQ11-A/TEND1/TMCI1-A P62/IRQ10-A/TEND0/TMCI0-A P61/IRQ9-A/DREQ1/TMRI1-A P60/IRQ8-A/DREQ0/TMRI0-A P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/EDACK3 P84/IRQ4-B/EDACK2 P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ETEND3 P82/IRQ2-B/ETEND2 P81/IRQ1-B/PO1-B/TIOCB3-B/TMRI1-B/TxD3/EDREQ3 P80/IRQ0-B/EDREQ2 IIC2 x 4 channels Port 6 TPU x 12 channels 8-bit D/A converter (6 channels) 10-bit A/D converter P53/IRQ3-A/ADTRG0-A/TRST*3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 PPG SSU Port 8 TMR x 2 channels Port 1 Port 2 Port 4 Port 5 Port 3 PG6/BREQ-A/TDI*3 PG5/BACK-A/TMS*3 PG4/BREQO-A/TCK*3 PG3/CS3/RAS3/CAS*1 PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 EXDMAC Port G RAM WDT SCI x 5 channels Port C PF7/ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/LCAS/DQML*1/IRQ15-A/SSI0-C PF1/UCAS/DQMU*1/IRQ14-A/SSCK0-C PF0/WAIT-A/ADTRG0-B/SCS0-C Interrupt controller Port F DMAC ROM (flash memory) Peripheral data bus DTC Peripheral address bus PB7/A15/TIOCB8/TCLKH PB6/A14/TIOCA8 PB5/A13/TIOCB7/TCLKG PB4/A12/TIOCA7 PB3/A11/TIOCD6/TCLKF PB2/A10/TIOCC6/TCLKE PB1/A9/TIOCB6 PB0/A8/TIOCA6 PC7/A7/TIOCB11 PC6/A6/TIOCA11 PC5/A5/TIOCB10 PC4/A4/TIOCA10 PC3/A3/TIOCD9 PC2/A2/TIOCC9 PC1/A1/TIOCB9 PC0/A0/TIOCA9 P35/OE-B/CKE-B*1/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD Bus controller Port B Port 9 Port H Port J P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/TCLKA P13/PO11/TIOCD0/TCLKB P14/PO12/TIOCA1/SSO0-A P15/PO13/TIOCB1/TCLKC/SSI0-A P16/PO14/TIOCA2/EDRAK2/SSCK0-A P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A PH3/CS7/OE-A/CKE-A*1/IRQ7-B PH2/CS6/IRQ6-B PH1/CS5/RAS5/SDRAM*1 PH0/CS4/RAS4/WE*1 P47/AN7_0 P46/AN6_0 P45/AN5_0 P44/AN4_0 P43/AN3_0 P42/AN2_0 P41/AN1_0 P40/AN0_0 P20/IRQ8-B/PO0-A/TIOCA3-A P21/IRQ9-B/PO1-A/TIOCB3-A P22/IRQ10-B/PO2-A/TIOCC3-A P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1 P27/IRQ15-B/PO7/TIOCB5/SCL2 Notes: 1. Not available in the H8S/2426 Group. 2. Can be used only in FP-144LV. 3. Pins BSCANE, TD1, TMS, TCK, TRST, and TDO can be used only in TLP-145V. (under development) Figure 1.2 Block Diagram of H8S/2426 Group and H8S/2426R Group Rev. 1.00 Sep. 19, 2008 Page 9 of 1270 REJ09B0466-0100 P97/AN15_1 P96/AN14_1 P95/AN13_1/DA3 P94/AN12_1/DA2 P93/AN11_1 P92/AN10_1 P91/AN9_1 P90/AN8_1 PJ2*2 PJ1 PJ0 Vref AVcc AVss Section 1 Overview PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 Port D Internal data bus H8S/2600 CPU Clock pulse generator Internal address bus MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF NMI PE7/D7/AD7 PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 Port E VCC VCC VCC VCC PLLVCC PLLVSS VSS VSS VSS VSS VSS VSS VCL System clock PLL PA7/A23/CS7/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 Port A IIC2 x 4 channels Port 8 P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 TPU x 12 channels 8-bit D/A converter 10-bit A/D converter Port 3 PG6/BREQ-A PG5/BACK-A PG4/BREQO-A/CS4 PG3/CS3/RAS3 PG2/CS2/RAS2 PG1/CS1 PG0/CS0 Port G WDT RAM SCI x 5 channels Port C PF7/ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS/SSI0-C PF1/CS5/UCAS/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C Interrupt controller Port F DTC DMAC ROM (flash memory) Periheral address bus Peripheral data bus PB7/A15/TIOCB8/TCLKH PB6/A14/TIOCA8 PB5/A13/TIOCB7/TCLKG PB4/A12/TIOCA7 PB3/A11/TIOCD6/TCLKF PB2/A10/TIOCC6/TCLKE PB1/A9/TIOCB6 PB0/A8/TIOCA6 PC7/A7/TIOCB11 PC6/A6/TIOCA11 PC5/A5/TIOCB10 PC4/A4/TIOCA10 PC3/A3/TIOCD9 PC2/A2/TIOCC9 PC1/A1/TIOCB9 PC0/A0/TIOCA9 P35/OE-B/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD Bus controller Port B PPG SSU P53/IRQ3-A/ADTRG0-A P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 TMR x 2 channels Port 1 Port 2 Port 4 Port 5 Port 9 P10/DREQ0/PO8/TIOCA0 P11/DREQ1/PO9/TIOCB0 P12/TEND0/PO10/TIOCC0/TCLKA P13/TEND1/PO11/TIOCD0/TCLKB P14/DACK0/PO12/TIOCA1/SSO0-A P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A P16/PO14/TIOCA2/SSCK0-A P17/PO15/TIOCB2/TCLKD/SCS0-A P20/PO0-A/TIOCA3-A/TMRI0-A P21/PO1-A/TIOCB3-A/TMRI1-A P22/PO2-A/TIOCC3-A/TMCI0-A P23/PO3-A/TIOCD3-A/TMCI1-A/TXD4-A P24/PO4-A/TIOCA4-A/TMO0-A/RXD4-A P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A P26/PO6/TIOCA5/SDA2/ADTRG1 P27/PO7/TIOCB5/SCL2 Figure 1.3 Block Diagram of H8S/2424 Group Rev. 1.00 Sep. 19, 2008 Page 10 of 1270 REJ09B0466-0100 P47/IRQ7-B/AN7_0 P46/IRQ6-B/AN6_0 P45/IRQ5-B/AN5_0 P44/IRQ4-B/AN4_0 P43/IRQ3-B/AN3_0 P42/IRQ2-B/AN2_0 P41/IRQ1-B/AN1_0 P40/IRQ0-B/AN0_0 P95/AN13_1/DA3 P94/AN12_1/DA2 Vref AVCC AVSS Section 1 Overview 1.4 1.4.1 Pin Description Pin Assignments PG1/CS1 PG0/CS0 P65/IRQ13-A/DACK1/TMO1-A P64/IRQ12-A/DACK0/TMO0-A P63/IRQ11-A/TEND1/TMCI1-A STBY Vss PJ1 PJ0 Vcc Vcc EXTAL XTAL Vss PF7/ PLLVss RES PLLVcc PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/LCAS/DQML*1/IRQ15-A/SSI0-C PF1/UCAS/DQMU*1/IRQ14-A/SSCK-C PF0/WAIT-A/ADTRG0-B/SCS0-C P62/IRQ10-A/TEND0/TMCI0-A P61/IRQ9-A/DREQ1/TMRI1-A P60/IRQ8-A/DREQ0/TMRI0-A PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 MD2 Vss P80/IRQ0-B/EDREQ2 Vcc PC0/A0/TIOCA9 PC1/A1/TIOCB9 PC2/A2/TIOCC9 PC3/A3/TIOCD9 PC4/A4/TIOCA10 Vss PC5/A5/TIOCB10 PC6/A6/TIOCA11 PC7/A7/TIOCB11 PB0/A8/TIOCA6 PB1/A9/TIOCB6 PB2/A10/TIOCC6/TCLKE PB3/A11/TIOCD6/TCLKF Vss PB4/A12/TIOCA7 PB5/A13/TIOCB7/TCLKG PB6/A14/TIOCA8 PB7/A15/TIOCB8/TCLKH PA0/A16 PA1/A17/TxD4-B Vss PA2/A18/RxD4-B PA3/A19/SCK4-B PA4/A20/IRQ4-A/SCS0-B PA5/A21/IRQ5-A/SSCK0-B PA6/A22/IRQ6-A/SSI0-B PA7/A23/IRQ7-A/SSO0-B EMLE*2 P81/IRQ1-B/PO1-B/TIOCB3-B/TMRI1-B/TxD3/EDREQ3 P82/IRQ2-B/ETEND2 PH0/CS4/RAS4/WE*1 PH1/CS5/RAS5/SDRAM*1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PG2/CS2/RAS2/RAS PG3/CS3/RAS3/CAS*1 AVcc Vref P40/AN0_0 P41/AN1_0 P42/AN2_0 P43/AN3_0 P44/AN4_0 P45/AN5_0 P46/AN6_0 P47/AN7_0 P90/AN8_1 P91/AN9_1 P92/AN10_1 P93/AN11_1 P94/AN12_1/DA2 P95/AN13_1/DA3 P96/AN14_1 P97/AN15_1 AVss PG4/BREQO-A PG5/BACK-A PG6/BREQ-A P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P53/IRQ3-A/ADTRG0-A P35/OE-B/CKE-B*1/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 H8S/2426 Group, H8S/2426R Group PLQP0144KA-A FP-144LV (Top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Vcc PE7/D7/AD7 Vss PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 PJ2 P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/EDACK3 P84/IRQ4-B/EDACK2 P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ETEND3 P27/IRQ15-B/PO7/TIOCB5/SCL2 P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A P23/IRQ11-B/PO3-A/TIOCD3/TxD4-A P22/IRQ10-B/PO2-A/TIOCC3-A P21/IRQ9-B/PO1-A/TIOCB3-A P20/IRQ8-B/PO0-A/TIOCA3-A Vss P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A P16/PO14/TIOCA2/EDRAK2/SSCK0-A P15/PO13/TIOCB1/TCLKC/SSI0-A P14/PO12/TIOCA1/SSO0-A P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 VCL*3 NMI WDTOVF PH3/CS7/OE-A/CKE-A*1/IRQ7-B PH2/CS6/IRQ6-B 41 0.1 F (recommended value) Notes: 1. Not available in the H8S/2426 Group. 2. Emulator enable pin. In normal operating mode, this pin should be fixed low. Driving this pin high in the flash-memory version enables the on-chip emulation function. When the on-chip emulation function is in use, pins P53, PG4, PG5, PG6, and WDTOVF are used exclusively as the on-chip emulator pins. 3. The VCL pin should be connected to an external capacitor. Figure 1.4 Pin Assignments for H8S/2426 Group and H8S/2426R Group (1) Rev. 1.00 Sep. 19, 2008 Page 11 of 1270 REJ09B0466-0100 Section 1 Overview 1 A Vss 2 MD1 3 MD0 4 P32 5 P35 6 P50 7 AVss 8 P94 9 P90 10 P44 11 P40 12 PG2 13 PG3 B MD2 Vcc P31 P34 P51 PG4 P93 P47 P45 P42 AVcc Vref PG1 C PC0 P80 PC1 P30 P33 P52 PG5 P92 P46 P43 P41 PG0 P65 STBY Vcc D PC4 PC2 PC3 P53 PG6 P97 P96 P95 P91 P63 PJ0 P64 E PC7 Vss PC5 PB0 NC Vss Vcc PJ1 F PB3 PC6 PB1 Vss H8S/2426 Group, H8S/2426R Group PTLG0145JB-A (Perspective top view) PF7 Vss RES PF4 XTAL EXTAL G PB6 PB2 PA0 PB4 PF6 PF5 PLLVss H Vss PB7 PA3 PB5 PF2 PF1 PLLVcc J PA5 PA2 PA7 PA1 P62 PF0 P60 PF3 K EMLE PA6 P82 PA4 P15 P16 P27 P83 PE0 PE4 PD7 PD6 P61 L PH0 P81 VCL P12 P17 P20 P21 P26 BSCANE * PE3 PD4 PD2 PD5 M PH1 NMI PH3 WDTOVF P11 P13 P22 P24 P85 PE2 PE6 Vss PD3 PD0 N PH2 P10 P14 Vss P23 P25 P84 PE1 PE5 PE7 Vcc PD1 Note: Connect NC to VSS or leave it open. The VCL pin must be connected to an external capacitor (recommended value: 0.1 F). * Boundary scan enable pin. When the boundary scan function is used, this pin should be fixed high. At this time, pins P53, PG4 to PG6, and WDTOVF are used exclusively for boundary scan. Therefore, the corresponding pin functions of those pins are not available. When the boundary scan function is not used, this pin should be fixed low. Figure 1.5 Pin Assignments for H8S/2426 Group and H8S/2426R Group (2) (LGA is in Planning) Rev. 1.00 Sep. 19, 2008 Page 12 of 1270 REJ09B0466-0100 Section 1 Overview 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PG1/CS1 PG0/CS0 STBY VSS P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 VCC VCC EXTAL XTAL VSS PF7/ PLLVSS RES PLLVCC PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS/SSI0-C PF1/CS5/UCAS/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 PG2/CS2/RAS2 PG3/CS3/RAS3 AVCC Vref P40/IRQ0-B/AN0_0 P41/IRQ1-B/AN1_0 P42/IRQ2-B/AN2_0 P43/IRQ3-B/AN3_0 P44/IRQ4-B/AN4_0 P45/IRQ5-B/AN5_0 P46/IRQ6-B/AN6_0 P47/IRQ7-B/AN7_0 P94/AN12_1/DA2 P95/AN13_1/DA3 AVSS PG4/BREQO-A/CS4 PG5/BACK-A PG6/BREQ-A P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P53/IRQ3-A/ADTRG0-A P35/OE-B/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 H8S/2424 Group PLQ0120LA-A FP-120BV (Top view) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VCC PE7/D7/AD7 VSS PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P27/PO7/TIOCB5/SCL2 P26/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A P22/PO2-A/TIOCC3-A/TMCI0-A P21/PO1-A/TIOCB3-A/TMRI1-A P20/PO0-A/TIOCA3-A/TMRI0-A P17/PO15/TIOCB2/TCLKD/SCS0-A P16/PO14/TIOCA2/SSCK0-A P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A P14/DACK0/PO12/TIOCA1/SSO0-A P13/TEND1/PO11/TIOCD0/TCLKB P12/TEND0/PO10/TIOCC0/TCLKA P11/DREQ1/PO9/TIOCB0 P10/DREQ0/PO8/TIOCA0 VCL*2 NMI WDTOVF MD2 VCC PC0/A0/TIOCA9 PC1/A1/TIOCB9 PC2/A2/TIOCC9 PC3/A3/TIOCD9 PC4/A4/TIOCA10 VSS PC5/A5/TIOCB10 PC6/A6/TIOCA11 PC7/A7/TIOCB11 PB0/A8/TIOCA6 PB1/A9/TIOCB6 PB2/A10/TIOCC6/TCLKE PB3/A11/TIOCD6/TCLKF PB4/A12/TIOCA7 VSS PB5/A13/TIOCB7/TCLKG PB6/A14/TIOCA8 PB7/A15/TIOCB8/TCLKH PA0/A16 VSS PA1/A17/TxD4-B PA2/A18/RxD4-B PA3/A19/SCK4-B PA4/A20/IRQ4-A/SCS0-B PA5/A21/IRQ5-A/SSCK0-B PA6/A22/IRQ6-A/SSI0-B PA7/A23/CS7/IRQ7-A/SSO0-B EMLE*1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 0.1 F (recommended value) Notes: 1. Emulator enable pin. In normal operating mode, this pin should be fixed low. Driving this pin high in the flash-memory version enables the on-chip emulation function. When the on-chip emulation function is in use, pins P53, PG4, PG5, PG6, and WDTOVF are used exclusively as the on-chip emulator pins. 2. The VCL pin should be connected to an external capacitor. Figure 1.6 Pin Assignments for H8S/2424 Group Rev. 1.00 Sep. 19, 2008 Page 13 of 1270 REJ09B0466-0100 Section 1 Overview 1.4.2 Table 1.3 Pin Assignments in Each Operating Mode Pin Assignments in Each Operating Mode of H8S/2426 Group and H8S/2426R Group Pin Name 5 Pin No. 145-Pin* (LGA-145 in Mode 7 Mode 1 MD2 Vss Mode 2 MD2 Vss Mode 4 MD2 Vss P80/IRQ0-B/ EDREQ2 Vcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 Vss PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 EXPE = 1 MD2 Vss P80/IRQ0-B/ EDREQ2 Vcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 Vss PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 EXPE = 0 MD2 Vss P80/IRQ0-B/ EDREQ2 Vcc PC0/TIOCA9 PC1/TIOCB9 PC2/TIOCC9 PC3/TIOCD9 PC4/TIOCA10 Vss PC5/TIOCB10 PC6/TIOCA11 PC7/TIOCB11 PB0/TIOCA6 PB1/TIOCB6 PB2/TIOCC6/ TCLKE PB3/TIOCD6/ TCLKF Vss PB4/TIOCA7 PB5/TIOCB7/ TCLKG PB6/TIOCA8 PB7/TIOCB8/ TCLKH PA0 144-Pin* 1 2 3 4 planning) Flash Memory Programmer Mode Vss Vss NC B1 A1 C2 P80/IRQ0-B/ P80/IRQ0-B/ EDREQ2 EDREQ2 Vcc A0 A1 A2 A3 A4 Vss A5 A6 A7 A8 A9 A10 Vcc A0 A1 A2 A3 A4 Vss A5 A6 A7 A8 A9 A10 4 5 6 7 8 9 10 11 12 13 14 15 16 B2 C1 C3 D2 D3 D1 E2 E3 F2 E1 E4 F3 G2 Vcc A0 A1 A2 A3 A4 Vss A5 A6 A7 A8 A9 A10 17 F1 A11 A11 PB3/A11 PB3/A11 A11 18 19 20 F4 G4 H4 Vss A12 A13 Vss A12 A13 Vss PB4/A12 PB5/A13 Vss PB4/A12 PB5/A13 Vss A12 A13 21 22 G1 H2 A14 A15 A14 A15 PB6/A14 PB7/A15 PB6/A14 PB7/A15 A14 A15 23 24 G3 J4 A16 A17 A16 A17 PA0/A16 PA0/A16 A16 A17 PA1/A17/TxD4-B PA1/A17/TxD4-B PA1/TxD4-B Rev. 1.00 Sep. 19, 2008 Page 14 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. 145-Pin* (LGA-145 in 5 Pin Name Mode 7 Mode 1 Vss A18 A19 A20/IRQ4-A Mode 2 Vss A18 A19 A20/IRQ4-A Mode 4 Vss EXPE = 1 Vss EXPE = 0 Vss Flash Memory Programmer Mode Vss A18 NC NC 144-Pin* 25 26 27 28 4 planning) H1 J2 H3 K4 PA2/A18/RxD4-B PA2/A18/RxD4-B PA2/RxD4-B PA3/A19/SCK4-B PA3/A19/RxD4-B PA3/SCK4-B PA4/A20/IRQ4-A/ PA4/A20/IRQ4-A/ PA4/IRQ4-A/ SCS0-B SCS0-B SCS0-B 29 J1 PA5/A21/ IRQ5A/SSCK0-B PA5/A21/ PA5/A21/ PA5/A21/ PA5/ NC IRQ5-A/SSCK0-B IRQ5-A/SSCK0-B IRQ5-A/SSCK0-B IRQ5-A/SSCK0-B 30 K2 PA6/A22/ PA6/A22/ IRQ6-A/SSI0- IRQ6-A/SSI0-B B PA7/A23/ IRQ7A/SSO0-B EMLE P81/IRQ1-B/ PO1-B/ TIOCB3-B/ TMRI1B/TxD3/ EDREQ3 PA7/A23/ IRQ7-A/SSO0-B PA6/A22/ IRQ6-A/SSI0-B PA6/A22/ IRQ6-A/SSI0-B PA6/ IRQ6-A/SSI0-B NC 31 J3 PA7/A23/ IRQ7-A/SSO0-B PA7/A23/ IRQ7-A/SSO0-B PA7/ IRQ7-A/SSO0-B NC 32 33 K1 L2 EMLE P81/IRQ1-B/ PO1-B/ TIOCB3-B/ TMRI1-B/TxD3/ EDREQ3 EMLE P81/IRQ1-B/ PO1-B/ TIOCB3-B/ TMRI1-B/TxD3/ EDREQ3 EMLE P81/IRQ1-B/ PO1-B/ TIOCB3-B/ TMRI1-B/TxD3/ EDREQ3 EMLE Vss P81/IRQ1-B/ NC PO1-B/ TIOCB3-B/ TMRI1B/TxD3/EDREQ3 34 K3 P82/IRQ2-B/ P82/IRQ2-B/ ETEND2 ETEND2 PH0/CS4/ RAS4/WE*1 PH0/CS4/ RAS4/WE*1 P82/IRQ2-B/ ETEND2 PH0/CS4/ RAS4/WE*1 P82/IRQ2-B/ ETEND2*3 PH0/CS4/ RAS4/WE*1 P82/IRQ2-B NC 35 L1 PH0 NC 36 M1 PH1/CS5/ PH1/CS5/ PH1/CS5/ PH1/CS5/ PH1/ RAS5/SDRA RAS5/SDRAM *1 RAS5/SDRAM *1 RAS5/SDRAM *1 SDRAM *1 M *1 PH2/CS6/IRQ PH2/CS6/IRQ6-B PH2/CS6/IRQ6-B PH2/CS6/IRQ6-B PH2/IRQ6-B 6-B PH3/CS7/ OE-A/CKEA*1/ IRQ7-B PH3/CS7/ OE-A/CKE-A*1/ IRQ7-B PH3/CS7/ OE-A/CKE-A*1/ IRQ7-B PH3/CS7/ OE-A/CKE-A*1/ IRQ7-B PH3/IRQ7-B NC 37 N2 NC 38 M2 NC 39 M3 WDTOVF/TD WDTOVF/TDO*3 WDTOVF/TDO*3 WDTOVF/TDO*3 WDTOVF/TDO*3 NC O*3 NMI VCL NMI VCL NMI VCL NMI VCL NMI VCL Vcc VCL 40 41 N1 L3 Rev. 1.00 Sep. 19, 2008 Page 15 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. 145-Pin* (LGA-145 in 5 Pin Name Mode 7 Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode 144-Pin* 42 4 planning) N3 P10/PO8/TIO P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 NC CA0 P11/PO9/TIO P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 NC CB0 P12/PO10/ P12/PO10/ TIOCC0/TCL TIOCC0/TCLKA KA P13/PO11/ P13/PO11/ TIOCD0/TCL TIOCD0/TCLKB KB P12/PO10/ TIOCC0/TCLKA P12/PO10/ TIOCC0/TCLKA P12/PO10/ TIOCC0/TCLKA OE 43 M4 44 L4 45 M5 P13/PO11/ TIOCD0/TCLKB P13/PO11/ TIOCD0/TCLKB P13/PO11/ TIOCD0/TCLKB CE 46 N4 P14/PO12/ P14/PO12/ P14/PO12/ P14/PO12/ WE P14/PO12/ TIOCA1/SSO TIOCA1/SSO0-A TIOCA1/SSO0-A TIOCA1/SSO0-A TIOCA1/SSO0-A 0-A P15/PO13/ P15/PO13/ P15/PO13/ P15/PO13/ NC P15/PO13/ TIOCB1/TCL TIOCB1/TCLKC/ TIOCB1/TCLKC/ TIOCB1/TCLKC/ TIOCB1/TCLKC/ SSI0-A SSI0-A SSI0-A SSI0-A KC/ SSI0-A P16/PO14/ TIOCA2/ EDRAK2/ SSCK0-A P16/PO14/ TIOCA2/ EDRAK2/ SSCK0-A P16/PO14/ TIOCA2/ EDRAK2/ SSCK0-A P16/PO14/ TIOCA2/ EDRAK2/ SSCK0-A P16/PO14/ TIOCA2/ SSCK0-A NC 47 K5 48 K6 49 L5 P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ NC P17/PO15/ TIOCB2/TCL TIOCB2/TCLKD/ TIOCB2/TCLKD/ TIOCB2/TCLKD/ TIOCB2/TCLKD/ EDRAK3/SCS0-A EDRAK3/SCS0-A EDRAK3/SCS0-A SCS0-A KD/ EDRAK3/SC S0-A Vss Vss Vss Vss Vss Vss 50 51 N5 L6 P20/IRQ8-B/ P20/IRQ8-B/ P20/IRQ8-B/ NC P20/IRQ8-B/ P20/IRQ8-B/ PO0-A/TIOCA3-A PO0-A/TIOCA3-A PO0-A/TIOCA3-A PO0-A/TIOCA3-A PO0A/TIOCA3-A P21/IRQ9-B/ P21/IRQ9-B/ P21/IRQ9-B/ P21/IRQ9-B/ P21/IRQ9-B/ Vcc PO1PO1-A/TIOCB3-A PO1-A/TIOCB3-A PO1-A/TIOCB3-A PO1-A/TIOCB3-A A/TIOCB3-A P22/IRQ10-B/ P22/IRQ10-B/ P22/IRQ10-B/ P22/IRQ10-B/ P22/IRQ10-B/ NC PO2PO2-A/TIOCC3-A PO2-A/TIOCC3-A PO2-A/TIOCC3-A PO2-A/TIOCC3-A A/TIOCC3-A P23/IRQ11-B/ P23/IRQ11-B/ PO3-A/ PO3-A/ TIOCD3-A/ TIOCD3-A/ TxD4-A TxD4-A P23/IRQ11-B/ PO3-A/ TIOCD3-A/ TxD4-A P23/IRQ11-B/ PO3-A/ TIOCD3-A/ TxD4-A P23/IRQ11-B/ PO3-A/ TIOCD3-A/ TxD4-A NC 52 L7 53 M6 54 N6 Rev. 1.00 Sep. 19, 2008 Page 16 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. 145-Pin* (LGA-145 in 5 Pin Name Mode 7 Mode 1 Mode 2 Mode 4 P24/IRQ12-B/ PO4-A/ TIOCA4-A/ RxD4-A EXPE = 1 P24/IRQ12-B/ PO4-A/ TIOCA4-A/ RxD4-A EXPE = 0 P24/IRQ12-B/ PO4-A/ TIOCA4-A/ RxD4-A P25/IRQ13-B/ PO5-A/ TIOCB4-A Flash Memory Programmer Mode Vss 144-Pin* 55 4 planning) M7 P24/IRQ12-B/ P24/IRQ12-B/ PO4-A/ PO4-A/ TIOCA4-A/ TIOCA4-A/ RxD4-A RxD4-A 56 N7 P25/WAIT-B/ P25/WAIT-B/ P25/WAIT-B/ P25/WAIT-B/ IRQ13IRQ13-B/PO5-A/ IRQ13-B/PO5-A/ IRQ13-B/PO5B/PO5-A/ TIOCB4-A TIOCB4-A A/TIOCB4-A TIOCB4-A P26/IRQ14-B/ P26/IRQ14-B/ PO6/TIOCA5/ PO6/TIOCA5/ SDA2/ADTR SDA2/ADTRG1 G1 P27/IRQ15-B/ P27/IRQ15-B/ PO7/TIOCB5/ PO7/TIOCB5/ SCL2 SCL2 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1B/RxD3/ ETEND3 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1-B/RxD3/ ETEND3 P26/IRQ14-B/ PO6/TIOCA5/ SDA2/ADTRG1 P26/IRQ14-B/ PO6/TIOCA5/ SDA2/ADTRG1 NC 57 L8 P26/IRQ14-B/ PO6/TIOCA5/ SDA2/ADTRG1 NC 58 K7 P27/IRQ15-B/ PO7/TIOCB5/ SCL2 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1-B/RxD3/ ETEND3 P27/IRQ15-B/ PO7/TIOCB5/ SCL2 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1-B/RxD3/ ETEND3 P27/IRQ15-B/ PO7/TIOCB5/ SCL2 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 NC 59 K8 NC 60 N8 P84/IRQ4-B/ P84/IRQ4-B/ EDACK2 EDACK2 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1B/SCK3/ EDACK3 PJ2*2 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 Vss PE7/D7 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1-B/SCK3/ EDACK3 PJ2*2 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 Vss PE7/D7 P84/IRQ4-B/ EDACK2 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1-B/SCK3/ EDACK3 PJ2*2 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 Vss PE7/D7 P84/IRQ4-B/ EDACK2 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1-B/SCK3/ EDACK3 PJ2*2 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 Vss PE7/D7 P84/IRQ4-B/ NC 61 M8 P85/IRQ5-B/ PO5-B/ TIOCB4-B/ TMO1-B/SCK3 NC 62 63 64 65 66 67 68 69 70 71 L9 K9 N9 M9 L10 K10 N10 M10 M11 N11 PJ2* PE0 PE1 PE2 PE3 PE4 PE5 PE6 Vss PE7 NC NC NC NC NC NC NC NC Vss NC Rev. 1.00 Sep. 19, 2008 Page 17 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. 145-Pin* (LGA-145 in 5 Pin Name Mode 7 Mode 1 Vcc D8 D9 D10 D11 D12 D13 D14 D15 Mode 2 Vcc D8 D9 D10 D11 D12 D13 D14 D15 Mode 4 Vcc D8 D9 D10 D11 D12 D13 D14 D15 EXPE = 1 Vcc D8 D9 D10 D11 D12 D13 D14 D15 EXPE = 0 Vcc PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Flash Memory Programmer Mode Vcc I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 144-Pin* 72 73 74 75 76 77 78 79 80 81 4 planning) N12 M13 N13 L12 M12 L11 L13 K12 K11 J12 P60/IRQ8-A/ P60/IRQ8-A/ P60/IRQ8-A/ P60/IRQ8-A/ P60/IRQ8-A/ NC DREQ0/TMRI DREQ0/TMRI0-A DREQ0/TMRI0-A DREQ0/TMRI0-A DREQ0/TMRI0-A 0-A P61/IRQ9-A/ P61/IRQ9-A/ P61/IRQ9-A/ P61/IRQ9-A/ P61/IRQ9-A/ NC DREQ1/TMRI DREQ1/TMRI1-A DREQ1/TMRI1-A DREQ1/TMRI1-A DREQ1/TMRI1-A 1-A P62/IRQ10-A/ P62/IRQ10-A/ P62/IRQ10-A/ NC P62/IRQ10-A/ P62/IRQ10-A/ TEND0/TMCI TEND0/TMCI0-A TEND0/TMCI0-A TEND0/TMCI0-A TEND0/TMCI0-A 0-A PF0/WAIT-A/ PF0/WAIT-A/ ADTRG0-B/ ADTRG0-B/ SCS0-C SCS0-C PF1/UCAS/ DQMU*1 /IRQ14-A/ SSCK0-C PF2/LCAS/ DQML*1/ IRQ15A/SSI0-C PF3/LWR/ SSO0-C HWR RD PF6/AS/AH PLLVcc RES PLLVss PF1/UCAS/ DQMU*1/ IRQ14-A/ SSCK0-C PF2/LCAS/ DQML*1/ IRQ15-A/SSI0-C PF0/WAIT-A/ ADTRG0-B/ SCS0-C PF1/UCAS/ DQMU*1/ IRQ14-A/ SSCK0-C PF2/LCAS/ DQML*1/ IRQ15-A/SSI0-C PF0/WAIT-A/ ADTRG0-B/ SCS0-C PF1/UCAS/ DQMU*1/ IRQ14-A/ SSCK0-C PF2/LCAS/ DQML*1/ IRQ15-A/SSI0-C PF0/ ADTRG0-B/ SCS0-C PF1/IRQ14-A/ SSCK0-C NC 82 K13 83 J10 84 J11 85 H12 NC 86 H10 PF2/IRQ15-A/ SSI0-C NC 87 J13 PF3/LWR/ SSO0-C HWR RD PF6/AS/AH PLLVcc RES PLLVss PF3/LWR/ SSO0-C HWR RD PF6/AS/AH PLLVcc RES PLLVss PF3/LWR/ SSO0-C HWR RD PF6/AS/AH PLLVcc RES PLLVss PF3/ SSO0-C PF4 PF5 PF6 PLLVcc RES PLLVss NC 88 89 90 91 92 93 H11 G12 G10 H13 G11 G13 NC NC NC Vcc RES Vss Rev. 1.00 Sep. 19, 2008 Page 18 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. 145-Pin* (LGA-145 in 5 Pin Name Mode 7 Mode 1 PF7/ Vss XTAL EXTAL Vcc Vcc PJ0 PJ1 Vss STBY Mode 2 PF7/ Vss XTAL EXTAL Vcc Vcc PJ0 PJ1 Vss STBY Mode 4 PF7/ Vss XTAL EXTAL Vcc Vcc PJ0 PJ1 Vss STBY EXPE = 1 PF7/ Vss XTAL EXTAL Vcc Vcc PJ0 PJ1 Vss STBY EXPE = 0 PF7/ Vss XTAL EXTAL Vcc Vcc PJ0 PJ1 Vss STBY Flash Memory Programmer Mode NC Vss XTAL EXTAL Vcc Vcc NC NC Vss Vcc 144-Pin* 94 95 96 97 98 99 100 101 102 103 104 4 planning) F10 F11 F12 F13 E11 E13 D11 E12 E10 D13 D10 P63/IRQ11-A/ P63/IRQ11-A/ P63/IRQ11-A/ NC P63/IRQ11-A/ P63/IRQ11-A/ TEND1/TMCI TEND1/TMCI1-A TEND1/TMCI1-A TEND1/TMCI1-A TEND1/TMCI1-A 1-A P64/IRQ12-A/ P64/IRQ12-A/ DACK0/TMO DACK0/TMO0-A 0-A P65/IRQ13-A/ P65/IRQ13-A/ DACK1/TMO DACK1/TMO1-A 1-A PG0/CS0 PG1/CS1 PG2/CS2/ RAS2/RAS PG0/CS0 PG1/CS1 PG2/CS2/ RAS2/RAS P64/IRQ12-A/ DACK0/TMO0-A P64/IRQ12-A/ DACK0/TMO0-A P64/IRQ12-A/ DACK0/TMO0-A NC 105 D12 106 C13 P65/IRQ13-A/ DACK1/TMO1-A P65/IRQ13-A/ DACK1/TMO1-A P65/IRQ13-A/ DACK1/TMO1-A NC 107 108 109 C12 B13 A12 PG0/CS0 PG1/CS1 PG2/CS2/ RAS2/RAS PG3/CS3/ RAS3/CAS*1 AVcc Vref P40/AN0_0 P41/AN1_0 P42/AN2_0 P43/AN3_0 P44/AN4_0 P45/AN5_0 P46/AN6_0 P47/AN7_0 PG0/CS0 PG1/CS1 PG2/CS2/ RAS2/RAS PG3/CS3/ RAS3/CAS*1 AVcc Vref P40/AN0_0 P41/AN1_0 P42/AN2_0 P43/AN3_0 P44/AN4_0 P45/AN5_0 P46/AN6_0 P47/AN7_0 PG0 PG1 PG2 NC NC NC 110 A13 PG3/CS3/ PG3/CS3/ RAS3/CAS*1 RAS3/CAS*1 AVcc Vref P40/AN0_0 P41/AN1_0 P42/AN2_0 P43/AN3_0 P44/AN4_0 P45/AN5_0 P46/AN6_0 P47/AN7_0 AVcc Vref P40/AN0_0 P41/AN1_0 P42/AN2_0 P43/AN3_0 P44/AN4_0 P45/AN5_0 P46/AN6_0 P47/AN7_0 PG3 NC 111 112 113 114 115 116 117 118 119 120 B11 B12 A11 C11 B10 C10 A10 B9 C9 B8 AVcc Vref P40/AN0_0 P41/AN1_0 P42/AN2_0 P43/AN3_0 P44/AN4_0 P45/AN5_0 P46/AN6_0 P47/AN7_0 Vcc Vcc NC NC NC Vss Vcc Vss NC NC Rev. 1.00 Sep. 19, 2008 Page 19 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. 145-Pin* (LGA-145 in 5 Pin Name Mode 7 Mode 1 P90/AN8_1 P91/AN9_1 Mode 2 P90/AN8_1 P91/AN9_1 Mode 4 P90/AN8_1 P91/AN9_1 P92/AN10_1 P93/AN11_1 EXPE = 1 P90/AN8_1 P91/AN9_1 P92/AN10_1 P93/AN11_1 EXPE = 0 P90/AN8_1 P91/AN9_1 P92/AN10_1 P93/AN11_1 Flash Memory Programmer Mode NC NC NC NC 144-Pin* 121 122 123 124 125 4 planning) A9 D9 C8 B7 A8 P92/AN10_1 P92/AN10_1 P93/AN11_1 P93/AN11_1 P94/AN12_1/ P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 NC DA2 P95/AN13_1/ P95/AN13_1/DA3 P95/AN13_1/DA3 P95/AN13_1/DA3 P95/AN13_1/DA3 NC DA3 P96/AN14_1 P97/AN15_1 AVss P96/AN14_1 P97/AN15_1 AVss P96/AN14_1 P97/AN15_1 AVss PG4/BREQO-A/ TCK*3 P96/AN14_1 P97/AN15_1 AVss PG4/BREQO-A/ TCK*3 P96/AN14_1 P97/AN15_1 AVss PG4/TCK* 3 126 D8 127 128 129 130 D7 D6 A7 B6 NC NC Vss NC PG4/BREQO- PG4/BREQO-A/ TCK*3 A/ 3 TCK* PG5/ BACKA/TMS*3 PG6/ BREQA/TDI*3 P50/BREQOB/ IRQ0-A/PO0B/ TIOCA3-B/ TMRI0B/TxD2/ SDA3 P51/BREQ-B/ IRQ1-A/PO2B/ TIOCC3-B/ TMCI0B/RxD2/ SCL3 PG5/BACK/ TMS*3 131 C7 PG5/BACK/ TMS*3 PG5/BACK/ TMS*3 PG5/TMS*3 NC 132 D5 PG6/ BREQ-A/TDI*3 PG6/ BREQ-A/TDI*3 PG6/ BREQ-A/TDI*3 PG6/TDI*3 NC 133 A6 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/TxD2/ SDA3 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/TxD2/ SDA3 P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/TxD2/ SDA3 P50/IRQ0-A/ PO0-B/ TIOCA3-B/ TMRI0-B/TxD2/ SDA3 Vss 134 B5 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/RxD2/ SCL3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/RxD2/ SCL3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/RxD2/ SCL3 P51/IRQ1-A/ PO2-B/ TIOCC3-B/ TMCI0-B/RxD2/ SCL3 Vss Rev. 1.00 Sep. 19, 2008 Page 20 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. 145-Pin* (LGA-145 in 5 Pin Name Mode 7 Mode 1 P52/BACK-B/ IRQ2-A/PO4B/ TIOCA4-B/ TMO0B/SCK2 Mode 2 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 Mode 4 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 EXPE = 1 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 EXPE = 0 P52/IRQ2-A/ PO4-B/ TIOCA4-B/ TMO0-B/SCK2 Flash Memory Programmer Mode Vcc 144-Pin* 135 4 planning) C6 136 D4 P53/IRQ3-A/ P53/IRQ3-A/ ADTRG0-A/ ADTRG0-A/ TRST*3 TRST*3 P35/OE-B/ CKE-B*1/ SCK1/SCL0 P34/SCK0/ SCK4A/SDA0 P35/OE-B/ CKE-B*1/ SCK1/SCL0 P34/SCK0/ SCK4-A/SDA0 P53/IRQ3-A/ ADTRG0-A/ TRST*3 P35/OE-B/ CKE-B*1/ SCK1/SCL0 P34/SCK0/ SCK4-A/SDA0 P53/IRQ3-A/ ADTRG0-A/ TRST*3 P35/OE-B/ CKE-B*1/ SCK1/SCL0 P34/SCK0/ SCK4-A/SDA0 P53/IRQ3-A/ ADTRG0-A/ TRST*3 P35/SCK1/ SCL0 NC 137 A5 NC 138 B4 P34/SCK0/ SCK4-A/SDA0 NC 139 C5 P33/RxD1/SC P33/RxD1/SCL1 L1 P32/RxD0/ IrRxD/SDA1 P31/TxD1 P32/RxD0/ IrRxD/SDA1 P31/TxD1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 NC 140 A4 P32/RxD0/ IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD P32/RxD0/ IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD P32/RxD0/ IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD Vcc 141 142 B3 C4 NC NC P30/TxD0/IrT P30/TxD0/IrTxD xD MD0 MD1 NC MD0 MD1 NC 143 144 A3 A2 E5 MD0 MD1 NC MD0 MD1 NC MD0 MD1 NC Vss Vss NC Notes: 1. 2. 3. 4. 5. Not available in the H8S/2426 Group. Can be used only in FP-144LV version. Can be used only in TLP-145V version. The 144-pin code is FP-144LV. The 145-pin code is TLP-145V. Rev. 1.00 Sep. 19, 2008 Page 21 of 1270 REJ09B0466-0100 Section 1 Overview Table 1.4 Pin No. Pin Assignments in Each Operating Mode of H8S/2424 Group Pin Name Mode 7 Flash Memory Programmer Mode Vss Vcc A0 A1 A2 A3 A4 Vss A5 A6 A7 A8 A9 A10 120-PIn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mode 1 MD2 Vcc A0 A1 A2 A3 A4 Vss A5 A6 A7 A8 A9 A10 Mode 2 MD2 Vcc A0 A1 A2 A3 A4 Vss A5 A6 A7 A8 A9 A10 Mode 4 MD2 Vcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 Vss PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 EXPE = 1 MD2 Vcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 Vss PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 EXPE = 0 MD2 Vcc PC0/TIOCA9 PC1/TIOCB9 PC2/TIOCC9 PC3/TIOCD9 PC4/TIOCA10 Vss PC5/TIOCB10 PC6/TIOCA11 PC7/TIOCB11 PB0/TIOCA6 PB1/TIOCB6 PB2/TIOCC6/ TCLKE PB3/TIOCD6/ TCLKF PB4/TIOCA7 Vss PB5/TIOCB7/ TCLKG PB6/TIOCA8 PB7/TIOCB8/ TCLKH PA0 Vss PA1/TxD4-B PA2/RxD4-B PA3/SCK4-B PA4/IRQ4-A/ SCS0-B PA5/IRQ5-A/ SSCK0-B 15 A11 A11 PB3/A11 PB3/A11 A11 16 17 18 A12 Vss A13 A12 Vss A13 PB4/A12 Vss PB5/A13 PB4/A12 Vss PB5/A13 A12 Vss A13 19 20 A14 A15 A14 A15 PB6/A14 PB7/A15 PB6/A14 PB7/A15 A14 A15 21 22 23 24 25 26 A16 Vss A17 A18 A19 A20/IRQ4-A A16 Vss A17 A18 A19 A20/IRQ4-A PA0/A16 Vss PA1/A17/TxD4-B PA2/A18/RxD4-B PA3/A19/SCK4-B PA4/A20/IRQ4-A/ SCS0-B PA5/A21/IRQ5-A/ SSCK0-B PA0/A16 Vss PA1/A17/TxD4-B PA2/A18/RxD4-B PA3/A19/SCK4-B PA4/A20/IRQ4-A/ SCS0-B PA5/A21/IRQ5-A/ SSCK0-B A16 Vss A17 A18 NC NC 27 PA5/A21/IRQ5-A/ PA5/A21/IRQ5-A/ SSCK0-B SSCK0-B NC Rev. 1.00 Sep. 19, 2008 Page 22 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Mode 7 Flash Memory Programmer Mode NC 120-PIn 28 Mode 1 PA6/A22/ IRQ6-A/SSI0-B PA7/A23/CS7/ IRQ7-A/SSO0-B EMLE WDTOVF NMI VCL P10/DREQ0/ PO8/TIOCA0 P11/DREQ1/ PO9/TIOCB0 P12/TEND0/ PO10/TIOCC0/ TCLKA P13/TEND1/ PO11/TIOCD0/ TCLKB P14/DACK0/ PO12/TIOCA1/ SSO0-A P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P16/PO14/ TIOCA2/ SSCK0-A P17/PO15/ TIOCB2/ TCLKD/SCS0-A P20/PO0-A/ TIOCA3-A/ TMRI0-A P21/PO1-A/ TIOCB3-A/ TMRI1-A P22/PO2-A/ TIOCC3-A/ TMCI0-A Mode 2 PA6/A22/ IRQ6-A/SSI0-B PA7/A23/CS7/ IRQ7-A/SSO0-B EMLE WDTOVF NMI VCL P10/DREQ0/ PO8/TIOCA0 P11/DREQ1/ PO9/TIOCB0 P12/TEND0/ PO10/TIOCC0/ TCLKA P13/TEND1/ PO11/TIOCD0/ TCLKB P14/DACK0/ PO12/TIOCA1/ SSO0-A P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P16/PO14/ TIOCA2/ SSCK0-A P17/PO15/ TIOCB2/ TCLKD/SCS0-A P20/PO0-A/ TIOCA3-A/ TMRI0-A P21/PO1-A/ TIOCB3-A/ TMRI1-A P22/PO2-A/ TIOCC3-A/ TMCI0-A Mode 4 PA6/A22/ IRQ6-A/SSI0-B PA7/A23/CS7/ IRQ7-A/SSO0-B EMLE WDTOVF NMI VCL P10/DREQ0/ PO8/TIOCA0 P11/DREQ1/ PO9/TIOCB0 P12/TEND0/ PO10/TIOCC0/ TCLKA P13/TEND1/ PO11/TIOCD0/ TCLKB P14/DACK0/ PO12/TIOCA1/ SSO0-A P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P16/PO14/ TIOCA2/ SSCK0-A P17/PO15/ TIOCB2/ TCLKD/SCS0-A P20/PO0-A/ TIOCA3-A/ TMRI0-A P21/PO1-A/ TIOCB3-A/ TMRI1-A P22/PO2-A/ TIOCC3-A/ TMCI0-A EXPE = 1 PA6/A22/ IRQ6-A/SSI0-B PA7/A23/CS7/ IRQ7-A/SSO0-B EMLE WDTOVF NMI VCL P10/DREQ0/ PO8/TIOCA0 P11/DREQ1/ PO9/TIOCB0 P12/TEND0/ PO10/TIOCC0/ TCLKA P13/TEND1/ PO11/TIOCD0/ TCLKB P14/DACK0/ PO12/TIOCA1/ SSO0-A P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P16/PO14/ TIOCA2/ SSCK0-A P17/PO15/ TIOCB2/ TCLKD/SCS0-A P20/PO0-A/ TIOCA3-A/ TMRI0-A P21/PO1-A/ TIOCB3-A/ TMRI1-A P22/PO2-A/ TIOCC3-A/ TMCI0-A EXPE = 0 PA6/IRQ6-A/ SSI0-B PA7/IRQ7-A/ SSO0-B EMLE WDTOVF NMI VCL P10/DREQ0/ PO8/TIOCA0 P11/DREQ1/ PO9/TIOCB0 P12/TEND0/ PO10/TIOCC0/ TCLKA P13/TEND1/ PO11/TIOCD0/ TCLKB P14/DACK0/ PO12/TIOCA1/ SSO0-A P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P16/PO14/ TIOCA2/ SSCK0-A P17/PO15/ TIOCB2/ TCLKD/SCS0-A P20/PO0-A/ TIOCA3-A/ TMRI0-A P21/PO1-A/ TIOCB3-A/ TMRI1-A P22/PO2-A/ TIOCC3-A/ TMCI0-A 29 NC 30 31 32 33 34 Vss NC Vcc VCL NC 35 NC OE 36 37 CE 38 WE 39 NC 40 NC 41 NC 42 NC 43 Vcc 44 NC Rev. 1.00 Sep. 19, 2008 Page 23 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Mode 7 Flash Memory Programmer Mode NC 120-PIn 45 Mode 1 Mode 2 Mode 4 P23/PO3-A/ TIOCD3-A/ TMCI1-A/TxD4-A P24/PO4-A/ TIOCA4-A/ TMO0-A/RxD4-A P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A P26/PO6/ TIOCA5/SDA2/ ADTRG1 P27/PO7/ TIOCB5/SCL2 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 Vss PE7/D7 Vcc D8 D9 D10 D11 D12 D13 D14 D15 EXPE = 1 P23/PO3-A/ TIOCD3-A/ TMCI1-A/TxD4-A P24/PO4-A/ TIOCA4-A/ TMO0-A/RxD4-A P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A P26/PO6/ TIOCA5/SDA2/ ADTRG1 P27/PO7/ TIOCB5/SCL2 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 Vss PE7/D7 Vcc D8 D9 D10 D11 D12 D13 D14 D15 EXPE = 0 P23/PO3-A/ TIOCD3-A/ TMCI1-A/TxD4-A P24/PO4-A/ TIOCA4-A/ TMO0-A/RxD4-A P23/PO3-A/ P23/PO3-A/ TIOCD3-A/ TIOCD3-A/ TMCI1-A/TxD4-A TMCI1-A/TxD4-A P24/PO4-A/ P24/PO4-A/ TIOCA4-A/ TIOCA4-A/ TMO0-A/RxD4-A TMO0-A/RxD4-A P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A P26/PO6/ TIOCA5/SDA2/ ADTRG1 P27/PO7/ TIOCB5/SCL2 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 Vss PE7/D7 Vcc D8 D9 D10 D11 D12 D13 D14 D15 P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A P26/PO6/ TIOCA5/SDA2/ ADTRG1 P27/PO7/ TIOCB5/SCL2 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 Vss PE7/D7 Vcc D8 D9 D10 D11 D12 D13 D14 D15 46 Vss 47 P25/PO5-A/ NC TIOCB4-A/TMO1-A 48 P26/PO6/ TIOCA5/SDA2/ ADTRG1 P27/PO7/ TIOCB5/SCL2 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 PE0 PE1 PE2 PE3 PE4 PE5 PE6 Vss PE7 Vcc PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 NC 49 NC 50 NC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 NC NC NC NC NC NC NC Vss NC Vcc I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Rev. 1.00 Sep. 19, 2008 Page 24 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Mode 7 Flash Memory Programmer Mode NC 120-PIn 69 Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 PF0/WAIT-A/ PF0/WAIT-A/ PF0/WAIT-A/ PF0/WAIT-A/ PF0/ OE-A/ADTRG0-B/ OE-A/ADTRG0-B/ OE-A/ADTRG0-B/ OE-A/ADTRG0-B/ ADTRG0-B/ SCS0-C SCS0-C SCS0-C SCS0-C SCS0-C PF1/CS5/UCAS/ PF1/CS5/UCAS/ SSCK0-C SSCK0-C PF2/CS6/ LCAS/SSI0-C PF3/LWR/ SSO0-C HWR RD PF6/AS/AH PLLVcc RES PLLVss PF7/ Vss XTAL EXTAL Vcc Vcc P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 Vss STBY PG0/CS0 PG1/CS1 PF2/CS6/ LCAS/SSI0-C PF3/LWR/ SSO0-C HWR RD PF6/AS/AH PLLVcc RES PLLVss PF7/ Vss XTAL EXTAL Vcc Vcc P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 Vss STBY PG0/CS0 PG1/CS1 PF1/CS5/UCAS/ SSCK0-C PF2/CS6/ LCAS/SSI0-C PF3/LWR/ SSO0-C HWR RD PF6/AS/AH PLLVcc RES PLLVss PF7/ Vss XTAL EXTAL Vcc Vcc P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 Vss STBY PG0/CS0 PG1/CS1 PG2/CS2/RAS2*3 PG3/CS3/RAS3*3 AVcc Vref PF1/CS5/UCAS/ SSCK0-C PF2/CS6/ LCAS/SSI0-C PF3/LWR/ SSO0-C HWR RD PF6/AS/AH PLLVcc RES PLLVss PF7/ Vss XTAL EXTAL Vcc Vcc P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 Vss STBY PG0/CS0 PG1/CS1 PG2/CS2/RAS2*3 PG3/CS3/RAS3*3 AVcc Vref PF1/SSCK0-C 70 NC 71 PF2/ SSI0-C PF3/ SSO0-C PF4 PF5 PF6 PLLVcc RES PLLVss PF7/ Vss XTAL EXTAL Vcc Vcc P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 Vss STBY PG0 PG1 PG2 PG3 AVcc Vref NC 72 NC 73 74 75 76 77 78 79 80 81 82 83 84 85 NC NC NC Vcc RES Vss NC Vss XTAL EXTAL Vcc Vcc NC 86 NC 87 88 89 90 91 92 93 94 Vss Vcc NC NC NC NC Vcc Vcc PG2/CS2/RAS2*3 PG2/CS2/RAS2*3 PG3/CS3/RAS3*3 PG3/CS3/RAS3*3 AVcc Vref AVcc Vref Rev. 1.00 Sep. 19, 2008 Page 25 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Mode 7 Flash Memory Programmer Mode NC 120-PIn 95 Mode 1 P40/IRQ0-B/ AN0_0 P41/IRQ1-B/ AN1_0 P42/IRQ2-B/ AN2_0 P43/IRQ3-B/ AN3_0 P44/IRQ4-B/ AN4_0 P45/IRQ5-B/ AN5_0 P46/IRQ6-B/ AN6_0 P47/IRQ7-B/ AN7_0 Mode 2 P40/IRQ0-B/ AN0_0 P41/IRQ1-B/ AN1_0 P42/IRQ2-B/ AN2_0 P43/IRQ3-B/ AN3_0 P44/IRQ4-B/ AN4_0 P45/IRQ5-B/ AN5_0 P46/IRQ6-B/ AN6_0 P47/IRQ7-B/ AN7_0 Mode 4 P40/IRQ0-B/ AN0_0 P41/IRQ1-B/ AN1_0 P42/IRQ2-B/ AN2_0 P43/IRQ3-B/ AN3_0 P44/IRQ4-B/ AN4_0 P45/IRQ5-B/ AN5_0 P46/IRQ6-B/ AN6_0 P47/IRQ7-B/ AN7_0 P94/AN12_1/DA2 P95/AN13_1/DA3 AVss PG4/BREQO-A/ CS4 PG5/BACK-A PG6/BREQ-A P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P53/IRQ3-A/ ADTRG0-A EXPE = 1 P40/IRQ0-B/ AN0_0 P41/IRQ1-B/ AN1_0 P42/IRQ2-B/ AN2_0 P43/IRQ3-B/ AN3_0 P44/IRQ4-B/ AN4_0 P45/IRQ5-B/ AN5_0 P46/IRQ6-B/ AN6_0 P47/IRQ7-B/ AN7_0 P94/AN12_1/DA2 P95/AN13_1/DA3 AVss PG4/BREQO-A/ CS4 PG5/BACK-A PG6/BREQ-A P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P53/IRQ3-A/ ADTRG0-A EXPE = 0 P40/IRQ0-B/ AN0_0 P41/IRQ1-B/ AN1_0 P42/IRQ2-B/ AN2_0 P43/IRQ3-B/ AN3_0 P44/IRQ4-B/ AN4_0 P45/IRQ5-B/ AN5_0 P46/IRQ6-B/ AN6_0 P47/IRQ7-B/ AN7_0 P94/AN12_1/DA2 P95/AN13_1/DA3 AVss PG4 96 NC 97 NC 98 Vss 99 Vcc 100 Vss 101 NC 102 NC 103 104 105 106 P94/AN12_1/DA2 P94/AN12_1/DA2 P95/AN13_1/DA3 P95/AN13_1/DA3 AVss PG4/BREQO-A/ CS4 PG5/BACK-A PG6/BREQ-A P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P53/IRQ3-A/ ADTRG0-A AVss PG4/BREQO-A/ CS4 PG5/BACK-A PG6/BREQ-A P50/BREQO-B/ IRQ0-A/PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 P51/BREQ-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P53/IRQ3-A/ ADTRG0-A NC NC Vss NC 107 108 109 PG5 PG6 P50/IRQ0-A/ PO0-B/ TIOCA3-B/ TMRI0-B/ TxD2/SDA3 P51/IRQ1-A/ PO2-B/ TIOCC3-B/ TMCI0-B/ RxD2/SCL3 P52/IRQ2-A/ PO4-B/ TIOCA4-B/ TMO0-B/SCK2 P53/IRQ3-A/ ADTRG0-A NC NC Vss 110 Vss 111 Vcc 112 NC Rev. 1.00 Sep. 19, 2008 Page 26 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. Pin Name Mode 7 Flash Memory Programmer Mode NC 120-PIn 113 Mode 1 P35/OE-B/ SCK1/SCL0 P34/SCK0/ SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/ IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 Mode 2 P35/OE-B/ SCK1/SCL0 P34/SCK0/ SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/ IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 Mode 4 P35/OE-B/ SCK1/SCL0 P34/SCK0/ SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/ IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 EXPE = 1 P35/OE-B/ SCK1/SCL0 P34/SCK0/ SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/ IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 EXPE = 0 P35/SCK1/ SCL0 P34/SCK0/ SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/ IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 114 NC 115 116 NC Vcc 117 118 119 120 NC NC Vss Vss Rev. 1.00 Sep. 19, 2008 Page 27 of 1270 REJ09B0466-0100 Section 1 Overview 1.4.3 Table 1.5 Pin Functions Pin Functions Pin No. H8S/2426, H8S/2426R H8S/2424 FP-120BV 2, 60, 83, 84 I/O Input Function For connection to the power supply. VCC pins should be connected to the system power supply. For connection to ground. VSS pins should be connected to the system power supply (0 V). Power supply pin for the onchip PLL oscillator. Ground pin for the on-chip PLL oscillator. Type Power supply Symbol VCC FP-144LV 4, 72, 98, 99 TLP-145V B2, N12, E11, E13 VSS A1, E2, F4, H1, 2, 10, 18, 25, 50, 70, N5, M11, E10, F11 95, 102 91 93 41 H13 G13 L3 8, 17, 22, 58, 80, 87 Input PLLVCC PLLVSS VCL 76 78 33 Input Input Output This pin must not be connected to the power supply and should be connected to the VSS pin via a 0.1-F (recommended value) capacitor (place it close to pin). Input For connection to a crystal oscillator. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator and external clock input. For connection to a crystal oscillator. The EXTAL pin can also input an external clock. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator and external clock input. Clock XTAL 96 F12 81 EXTAL 97 F13 82 Input 94 F10 79 Output Supplies the system clock to external devices. Rev. 1.00 Sep. 19, 2008 Page 28 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Clock Symbol SDRAM* 1 H8S/2424 FP-120BV I/O Function FP-144LV 36 TLP-145V M1 Output When a synchronous DRAM is connected, this pin is connected to the CLK pin of the synchronous DRAM. For details, refer to section 6, Bus Controller (BSC). Input These pins set the operating mode. These pins should not be changed during operation. Reset pin. When this pin is driven low, the chip is reset. When this pin is driven low, a transition is made to hardware standby mode. On-chip emulator enable pin. When the on-chip emulator is used, this pin should be fixed high. At this time, pins P53, PG4 to PG6, and WDTOVF are used exclusively by the on-chip emulator. Therefore, the corresponding pin functions of those pins are not available. When the on-chip emulator is not used, this pin should be fixed low. Boundary scan enable pin. When the boundary scan function is used, this pin should be fixed high. At this time, pins P53, PG4 to PG6, and WDTOVF are used exclusively for boundary scan. Therefore, the corresponding pin functions of those pins are not available. When the boundary scan function is not used, this pin should be fixed low. Operating mode control System control MD2 MD1 MD0 RES STBY 1 144 143 92 103 B1 A2 A3 G12 D13 1 120 119 77 88 Input Input EMLE 32 K1 30 Input BSCANE* 2 L9 Input Rev. 1.00 Sep. 19, 2008 Page 29 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Address bus Symbol A23 to A0 FP-144LV 31 to 26, 24 to 19, 17 to 11, 9 to 5 TLP-145V J3, K2, J1, K4, H3, J2, J4, G3, H2, G1, H4, G4, F1, G2, F3, E4, E1, F2, E3, D1, D3, D2, C3, C1 H8S/2424 FP-120BV 29 to 23, 21 to 18, 16 to 9, 7 to 3 I/O Function Output These pins output an address. Data bus D15 to D0 80 to 73, 71, 69 to 63 68 to 61, K11, K12, L13, 59, L11, M12, L12, 57 to 51 N13, M13, N11, M11, N10, L9, M10, N9, K10, L8 29, 71, 70, 106, 92 to 89 75 Input/ output These pins constitute a bidirectional data bus. When an address/data multiplexed I/O space is accessed, an address is also output. Bus control CS7 to CS0 AS 38 to 35, M2, N2, M1, 110 to 107 L1, A13, A12, B13, C12 90 G10 Output Signals that select division areas 7 to 0 in the external address space Output When this pin is low, it indicates that address output on the address bus is valid. Output Signal for holding the address when an address/data multiplexed I/O space is being accessed. Output When this pin is low, it indicates that the external address space is being read. AH 90 G10 75 RD 89 G12 74 Rev. 1.00 Sep. 19, 2008 Page 30 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Bus control Symbol HWR FP-144LV 88 TLP-145V H11 H8S/2424 FP-120BV 73 I/O Function Output Strobe signal indicating that an external address space is to be written to, and the upper half (D15 to D8) of the data bus is enabled. Also functions as the write enable signal for accessing the DRAM space. Output Strobe signal indicating that an external address space is to be written to, and the lower half (D7 to D0) of the data bus is enabled. Input The external bus master requests the bus to this LSI. LWR 87 J13 72 BREQ-A BREQ-B BREQO-A BREQO-B 132 134 130 133 D5 B5 B6 A6 108 110 106 109 Output External bus request signal when the internal bus master accesses an external space in the external bus release state. Output Indicates the bus is released to the external bus master. Output Upper column address strobe signal for accessing the 16-bit DRAM space. Also functions as the column address strobe signal for accessing the 8-bit DRAM space. Output Lower column address strobe signal for accessing the 16-bit DRAM space. Output Upper data mask enable signal for accessing the 16-bit continuous synchronous DRAM space. Also functions as the data mask enable signal for accessing the 8-bit continuous synchronous DRAM space. Output Lower-data mask enable signal for accessing the 16-bit continuous synchronous DRAM interface space. BACK-A BACK-B UCAS 131 135 85 C7 C6 H12 107 111 70 LCAS 86 H10 71 DQMU* 1 85 H12 DQML* 1 86 H10 Rev. 1.00 Sep. 19, 2008 Page 31 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Bus control Symbol RAS3 RAS4* RAS5* RAS* 1 3 3 H8S/2424 FP-120BV 91 92 I/O Function FP-144LV TLP-145V A12 A13 L1 M1 A12 RAS/RAS2 109 110 35 36 109 Output Row address strobe signal for the DRAM when the DRAM interface is set. RAS signal is a row address strobe signal when areas 2 to 5 are set as the continuous DRAM space. Output Row address strobe signal for the synchronous DRAM when the synchronous DRAM interface is set. Output Column address strobe signal for the synchronous DRAM when the synchronous DRAM interface is set. Output Write enable signal for the synchronous DRAM when the synchronous DRAM interface is set. Input Requests insertion of a wait state in the bus cycles when accessing an external 3-state address space. CAS* 1 110 A13 WE* 1 35 L1 WAIT-A WAIT-B 84 56 J11 N7 69 47 OE-A OE-B 38 137 M2 A5 69 113 Output Output enable signal when accessing the DRAM space. The output pins of OE and (OE) are selected by the port function control register 2 (PFCR2) of port 3. Output Clock enable signal when the synchronous DRAM interface is set. The output pins of CKE and (CKE) are selected by the port function control register 2 (PFCR2) of port 3. CKE-A* CKE-B* 1 38 137 M2 A5 1 Rev. 1.00 Sep. 19, 2008 Page 32 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Interrupt signals Symbol NMI FP-144LV 40 TLP-145V N1 H8S/2424 FP-120BV 32 I/O Input Function Nonmaskable interrupt request pin. This pin should be fixed high when not used. These pins request a maskable interrupt. The input pins of IRQn-A and IRQn-B are selected by the IRQ pin select register (ITSR) of the interrupt controller. (n = 0 to 15 for the H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for the H8S/2424 Group) Input These signals request DMAC activation. H10, H12, C13, IRQ15-A to 86, 85, 3 IRQ8-A* 106 to 104, D12, D10, J10, K13, J12 83 to 81 IRQ7-A to IRQ0-A 31 to 28, J3, K2, J1, K4, 136 to 133 D4, C6, B5, A6 K7, L8, N7, M7, N6, M6, L7, L6, M2, N2, M8, N8, K8, K3, L2, C2 K13 J12 D10 J10 C13 D12 L2 C2 K8 K3 M8 N8 L5 K6 Input 29 to 26, 112 to 109 IRQ15-B to 58 to 51 3 IRQ8-B* IRQ7-B to IRQ0-B DMA controller (DMAC) DREQ1 DREQ0 TEND1 TEND0 DACK1 DACK0 EXDMA EDREQ3 controller EDREQ2 (EXDMAC) 3 ETEND3 * ETEND2 EDACK3 EDACK2 EDRAK3 EDRAK2 38, 37, 61 to 59, 34, 33, 3 82 81 104 83 106 105 33 3 59 34 61 60 49 48 102 to 95 35 34 37 36 39 38 Output These signals indicate the end of DMAC data transfer. Output DMAC single address transfer acknowledge signals. Input These signals request EXDMAC activation. Output These signals indicate the end of EXDMAC data transfer. Output EXDMAC single address transfer acknowledge signals. Output These signals notify an external device of acceptance and start of execution of a DMA transfer request. Rev. 1.00 Sep. 19, 2008 Page 33 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol FP-144LV 22 20 17 16 49 47 45 44 42 43 44 45 46 47 48 49 51 52 TLP-145V H2 H4 F1 G2 L5 K5 M5 L4 N3 M4 L4 M5 N4 K5 K6 L5 L6 M7 N6 K6 A6 L2 B5 K8 K7 N7 C6 M8 L8 K7 H8S/2424 FP-120BV 20 18 15 14 41 39 37 36 34 35 36 37 38 39 40 41 42 43 44 45 109 86 110 85 46 47 111 50 48 49 Input/ output TGRA_5 and TGRB_5 input capture input/output compare output/PWM output pins. Input/ output TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins. Input/ output Input/ output Input/ output TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. Input/ output TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. I/O Input Function External clock input pins of the timer. 16-bit timer TCLKH pulse TCLKG unit (TPU) TCLKF TCLKE TCLKD TCLKC TCLKB TCLKA TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3-A TIOCB3-A TIOCC3-A 53 TIOCD3-A 54 TIOCA3-B TIOCB3-B 133 33 TIOCC3-B 134 TIOCD3-B 59 TIOCA4-A TIOCB4-A TIOCA4-B TIOCB4-B TIOCA5 TIOCB5 55 56 135 61 57 58 Rev. 1.00 Sep. 19, 2008 Page 34 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol FP-144LV 14 15 16 17 19 20 21 22 5 6 7 8 9 11 TLP-145V E4 F3 G2 F1 G4 H4 G1 H2 C1 C3 D2 D3 D1 E3 H8S/2424 FP-120BV 12 13 14 15 16 18 19 20 3 4 5 6 7 9 Input/ output TGRA_10 and TGRB_10 input capture input/output compare output/PWM output pins. TGRA_11 and TGRB_11 input capture input/output compare output/PWM output pins. Input/ output Input/ output Input/ output TGRA_7 and TGRB_7 input capture input/output compare output/PWM output pins. TGRA_8 and TGRB_8 input capture input/output compare output/PWM output pins. TGRA_9 to TGRD_9 input capture input/output compare output/PWM output pins. I/O Input/ output Function TGRA_6 to TGRD_6 input capture input/output compare output/PWM output pins. 16-bit timer TIOCA6 pulse TIOCB6 unit (TPU) TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 12 13 F2 E1 10 11 Input/ output Programmable pulse generator (PPG) PO15 to PO8 PO7 PO6 PO5-A to PO0-A PO5-B PO4-B PO3-B PO2-B PO1-B PO0-B 49 to 42 58 to 51 L5, K6, K5, N4, M5, L4, M4, N3 K7, L8, N7, M7, N6, M6, L7, L6 41 to 34 49 to 42 Output Pulse output pins. 61 135 59 134 33 133 M8 C6 K8 B5 L2 A6 50 111 85 110 86 109 Rev. 1.00 Sep. 19, 2008 Page 35 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type 8-bit timer (TMR) Symbol TMO0-A TMO1-A TMO0-B TMO1-B TMCI0-A TMCI1-A TMCI0-B TMCI1-B TMRI0-A TMRI1-A TMRI0-B TMRI1-B Watchdog timer (WDT) Serial communication interface (SCI)/ Smart Card interface (SCI_0 with IrDA function) WDTOVF FP-144LV 105 106 135 61 83 104 134 59 81 82 133 33 39 TLP-145V D12 C13 C6 M8 J10 D10 B5 K8 J12 K13 A6 L2 M3 H8S/2424 FP-120BV 46 47 111 50 44 45 110 85 42 43 109 86 31 Output Counter overflow signal output pin in watchdog timer mode. Output Data output pins. Input Counter reset input pins. Input External event input pins. I/O Function Output Waveform output pins with output compare function. TxD4-A TxD4-B TxD3 TxD2 TxD1 TxD0/ IrTxD RxD4-A RxD4-B RxD3 RxD2 RxD1 RxD0/ IrRxD SCK4-A SCK4-B SCK3 SCK2 SCK1 SCK0 54 24 33 133 141 142 55 26 59 134 139 140 138 27 61 135 137 138 K6 J4 L2 A6 B3 C4 K7 J2 K8 C5 A4 45 23 86 109 117 118 46 24 85 110 115 116 Input Data input pins. B4 H3 M8 C6 A5 B4 114 25 50 111 113 114 Input/ output Clock input/output pins. Rev. 1.00 Sep. 19, 2008 Page 36 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type 2 H8S/2424 FP-120BV 110 49 115 113 109 48 116 114 38 29 39 28 40 27 41 26 Input/ output Input/ output Input/ output Input/ output Input Input Data input/output pins. Input/ output I C data input/output pins. 2 Symbol FP-144LV 134 58 139 137 133 57 140 138 46 31 47 30 48 29 49 28 TLP-145V B5 K7 C5 A5 A6 L8 A4 B4 N4 J3 K5 K2 K6 J1 L5 K4 D4 C7 M3 D5 B6 I/O Input/ output Function I C clock input/output pins. 2 I C bus SCL3 interface 2 SCL2 (IIC2) SCL1 SCL0 SDA3 SDA2 SDA1 SDA0 Synchronous serial communication unit (SSU) SSO0-A SSO0-B SSI0-A SSI0-B SSCK0-A SSCK0-B SCS0-A SCS0-B Boundary 2 scan* (JTAG) TRST TMS TDO TDI TCK Data input/output pins. Clock input/output pins. Chip select input/output pins. TAP controller reset pin. Control signal input pin for boundary scan. Output Data output pin for boundary scan. Input Input Data input pin for boundary scan. Clock input pin for boundary scan. Rev. 1.00 Sep. 19, 2008 Page 37 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type A/D converter Symbol AN15_1* AN14_1* AN13_1 AN12_1 3 H8S/2424 FP-120BV I/O Input Function Analog input pins. FP-144LV 128 127 126 125 TLP-145V D6 D7 D8 A8 3 104 103 102 to 95 Input Analog input pins. AN11_1 to 124 to 121 B7, C8, D9, A9 3 AN8_1* AN7_0 to AN0_0 120 to 113 B8, C9, B9, A10, C10, B10, C11, A11 D4 J11 L8 D8 A8 B11 Input Input Analog input pins. Analog input pins. ADTRG0-A 136 ADTRG0-B 84 ADTRG1 D/A converter A/D converter, D/A converter DA3 DA2 AVCC 57 126 125 111 112 69 48 104 103 93 Input Pin for input of an external trigger to start A/D conversion. Output Analog output pins. Input Analog power-supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). Ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). Reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). AVSS 129 A7 105 Input Vref 112 B12 94 Input Rev. 1.00 Sep. 19, 2008 Page 38 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type I/O ports Symbol P17 to P10 P27 to P20 P35 to P30 P47 to P40 P53 to P50 P65 to P60 P85 P84* P83 P82* P81 P80* 3 3 3 3 H8S/2424 FP-120BV 41 to 34 I/O Input/ output Input/ output Input/ output Input Function 8-bit input/output pins. FP-144LV 49 to 42 TLP-145V L5, K6, K5, N4, M5, L4, M4, N3 K7, L8, N7, M7, N6, M6, L7, L6 58 to 51 49 to 42 8-bit input/output pins. 137 to 142 A5, B4, C5, A4, B3, C4 120 to 113 B8, C9, B9, A10, C10, B10, C11, A11 136 to 133 D4, C6, B5, A6 106 to 104, C13, D12, D10, 83 to 81 J10, K13, J12 61 60 59 34 33 3 M8 N8 K8 K3 L2 C2 113 to 118 102 to 95 6-bit input/output pins. 8-bit input pins. 112 to 109 50 85 86 104, 103 Input/ output Input/ output Input/ output 4-bit input/output pins. 6-bit input/output pins. 6-bit input/output pins in the H8S/2426 Group and H8S/2426R Group. 3-bit input/output pins in the H8S/2424 Group. P97* , 3 P96* , P95, P94, P93 to 3 P90* PA7 to PA0 PB7 to PB0 PC7 to PC0 128 to 121 D6, D7, D8, A8, B7, C8, D9, A9 Input 8-bit input/output pins in the H8S/2426 Group and H8S/2426R Group. 2-bit input/output pins in the H8S/2424 Group. 31 to 26, 24, 23 22 to 19, 17 to 14 13 to 11, 9 to 5 J3, K2, J1, K4, H3, J2, J4, G3 H2, G1, H4, G4, F1, G2, F3, E4 E1, F2, E3, D1, D3, D2, C3, C1 29 to 23, 21 20 to 18, 16 to 12 11 to 9, 7 to 3 Input/ output Input/ output Input/ output 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. Rev. 1.00 Sep. 19, 2008 Page 39 of 1270 REJ09B0466-0100 Section 1 Overview Pin No. H8S/2426, H8S/2426R Type I/O ports Symbol PD7 to PD0 PE7 to PE0 PF7 to PF0 PG6 to PG0 PH3 to 3 PH0* PJ2* * PJ1* 3 3 34 H8S/2424 FP-120BV 68 to 61 I/O Input/ output Input/ output Input/ output Input/ output Input/ output Input Function 8-bit input/output pins. FP-144LV 80 to 73 TLP-145V K11, K12, L13, L11, M12, L12, N13, M13 N11, M10, N10, K10, L10, M9, N9, K9 F10, G10, G12, H11, J13, H10, H12, J11 71, 69 to 63 94, 90 to 84 59, 57 to 51 79, 75 to 69 108 to 106, 92 to 89 8-bit input/output pins. 8-bit input/output pins. 132 to 130, D5, C7, B6, 110 to 107 A13, A12, B13, C12 38 to 35 62 101 100 M2, N2, M1, L1 E12 D11 7-bit input/output pins. 4-bit input/output pins. 3-bit input pins. PJ0* Notes: 1. 2. 3. 4. Not supported by the H8S/2426 Group or H8S/2424R Group. Can be used only in the 145-pin version. Not supported by the H8S/2424 Group. Can be used only in the 144-pin version. Rev. 1.00 Sep. 19, 2008 Page 40 of 1270 REJ09B0466-0100 Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.1 Features * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPUs object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 2 states Rev. 1.00 Sep. 19, 2008 Page 41 of 1270 REJ09B0466-0100 Section 2 CPU 16 / 8-bit register-register divide: 12 states 16 x 16-bit register-register multiply: 4 states 32 / 16-bit register-register divide: 20 states * Two CPU operating modes Normal mode* Advanced mode Note: * Normal mode is not available in this LSI. * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * The number of execution states of the MULXU and MULXS instructions Rev. 1.00 Sep. 19, 2008 Page 42 of 1270 REJ09B0466-0100 Section 2 CPU Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd CLRMAC LDMAC CLRMAC LDMAC ERs, MACH LDMAC ERs, MACL STMAC Note: STMAC MACH, ERd STMAC MACL, ERd * H8S/2600 2* 2* 3* 3* 1* 1* 1* 1* 1* H8S/2000 12 20 13 21 Not supported The number of execution states is incremented following a MAC instruction. In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-Kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. Rev. 1.00 Sep. 19, 2008 Page 43 of 1270 REJ09B0466-0100 Section 2 CPU * Higher speed Basic instructions execute twice as fast. Note: Normal mode is not available in this LSI. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. * Additional control register One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev. 1.00 Sep. 19, 2008 Page 44 of 1270 REJ09B0466-0100 Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 45 of 1270 REJ09B0466-0100 Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) SP (SP*2 ) EXR*1 Reserved*1 *3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not used, it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning. (b) Exception Handling Figure 2.2 Stack Structure in Normal Mode Rev. 1.00 Sep. 19, 2008 Page 46 of 1270 REJ09B0466-0100 Section 2 CPU 2.2.2 Advanced Mode * Address Space Linear access is provided to a 16-Mbyte maximum address space. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.3 Exception Vector Table (Advanced Mode) Rev. 1.00 Sep. 19, 2008 Page 47 of 1270 REJ09B0466-0100 Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also used for the exception vector table. * Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) (SP*2 ) EXR*1 Reserved*1 *3 CCR PC (24 bits) (a) Subroutine Branch Notes: 1. When EXR is not used, it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. (b) Exception Handling Figure 2.4 Stack Structure in Advanced Mode Rev. 1.00 Sep. 19, 2008 Page 48 of 1270 REJ09B0466-0100 Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. H'0000 64 Kbytes H'FFFF H'00000000 16 Mbytes Program area H'00FFFFFF Cannnot be used in this LSI Data area H'FFFFFFFF (a) Normal Mode* Note: * Normal mode cannot be used in this LSI. (b) Advanced Mode Figure 2.5 Memory Map Note: Normal mode is not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 49 of 1270 REJ09B0466-0100 Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiplyaccumulate register (MAC). General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers (CR) 23 PC 0 EXR T 76543210 - - - - I2 I1 I0 76543210 CCR I UI H U N Z V C 63 MAC 31 Sign extension MACL 0 41 MACH 32 [Legend] SP: PC: EXR: T: I2 to I0: CCR: I: UI: Stack pointer Program counter Extended register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Note: * UI cannot be used as an interrupt mask bit in this LSI. Figure 2.6 CPU Registers Rev. 1.00 Sep. 19, 2008 Page 50 of 1270 REJ09B0466-0100 Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.7 Usage of General Registers Rev. 1.00 Sep. 19, 2008 Page 51 of 1270 REJ09B0466-0100 Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.3 Extended Register (EXR) EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions except for the STC instruction is executed, all interrupts including NMI will be masked for three states after execution is completed. Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is started each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 -- I2 I1 I0 All 1 1 1 1 -- R/W R/W R/W Reserved These bits are always read as 1. These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Rev. 1.00 Sep. 19, 2008 Page 52 of 1270 REJ09B0466-0100 Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. Rev. 1.00 Sep. 19, 2008 Page 53 of 1270 REJ09B0466-0100 Section 2 CPU Bit 2 Bit Name Z Initial Value Undefined R/W R/W Description Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.6 Initial Values of CPU Internal Registers When the reset exception handling loads the start address from the vector address, PC is initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1. However, the general registers and the other CCR bits are not initialized. The initial value of SP (ER7) is undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a reset. Rev. 1.00 Sep. 19, 2008 Page 54 of 1270 REJ09B0466-0100 Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers. Data Type 1-bit data Register Number RnH Data Format 7 0 Don't care 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 1.00 Sep. 19, 2008 Page 55 of 1270 REJ09B0466-0100 Section 2 CPU Data Type Word data Register Number Rn Data Format 15 0 MSB LSB Word data 15 En 0 MSB LSB Longword data 31 ERn 16 15 0 MSB En Rn LSB Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 1.00 Sep. 19, 2008 Page 56 of 1270 REJ09B0466-0100 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Format 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M+1 MSB LSB Longword data Address 2N Address 2N+1 Address 2N+2 Address 2N+3 MSB LSB Figure 2.10 Memory Data Formats Rev. 1.00 Sep. 19, 2008 Page 57 of 1270 REJ09B0466-0100 Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM, STM MOVFPE*3, MOVTPE*3 1 1 Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B -- B/W/L B/W/L B -- -- -- Total: Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS* 4 23 MAC, LDMAC, STMAC, CLRMAC Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc*2, JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 4 8 14 5 9 1 69 Block data transfer EEPMOV Legend: B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. Rev. 1.00 Sep. 19, 2008 Page 58 of 1270 REJ09B0466-0100 Section 2 CPU 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Rev. 1.00 Sep. 19, 2008 Page 59 of 1270 REJ09B0466-0100 Section 2 CPU Symbol :8/:16/:24/:32 Note: * Description Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.3 Instruction MOV Data Transfer Instructions Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM Note: * L L Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Sep. 19, 2008 Page 60 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU B B/W/L L B B/W MULXS B/W DIVXU B/W Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Sep. 19, 2008 Page 61 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.4 Instruction DIVXS Arithmetic Operations Instructions (2) Size*1 B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS*2 MAC B -- CLRMAC LDMAC STMAC -- L Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 1.00 Sep. 19, 2008 Page 62 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.5 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement (logical complement) of general register contents. OR B/W/L XOR B/W/L NOT B/W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. B/W/L B/W/L B/W/L Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Sep. 19, 2008 Page 63 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions (1) Size* B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Note: * Size refers to the operand size. B: Byte Rev. 1.00 Sep. 19, 2008 Page 64 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.7 Instruction BXOR Bit Manipulation Instructions (2) Size* B Function C ( BIXOR B BLD B BILD B BST B BIST B Note: * Size refers to the operand size. B: Byte Rev. 1.00 Sep. 19, 2008 Page 65 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine. Rev. 1.00 Sep. 19, 2008 Page 66 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the contents of a general register or memory, or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. STC B/W ANDC ORC XORC NOP Note: * B B B -- Size refers to the operand size. B: Byte W: Word Rev. 1.00 Sep. 19, 2008 Page 67 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W -- 2.6.2 Basic Instruction Formats The H8S/2600 Series instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branching condition of Bcc instructions. Rev. 1.00 Sep. 19, 2008 Page 68 of 1270 REJ09B0466-0100 Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm, etc. (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Rev. 1.00 Sep. 19, 2008 Page 69 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 2.7.1 Register Direct--Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction code, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 1.00 Sep. 19, 2008 Page 70 of 1270 REJ09B0466-0100 Section 2 CPU 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn Register indirect with post-increment--@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. Register indirect with pre-decrement--@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. 2.7.5 Absolute Address--@aa:8 /@aa:16 / @aa:24 /@aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address Note: * 24 bits (@aa:24) Normal Mode* H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 71 of 1270 REJ09B0466-0100 Section 2 CPU 2.7.6 Immediate--#xx:8 / #xx:16/ #xx:32 The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: Normal mode is not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 72 of 1270 REJ09B0466-0100 Section 2 CPU Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* Note: * Normal mode is not available in this LSI. (a) Advanced Mode Figure 2.12 Branch Address Specification in Memory Indirect Mode Rev. 1.00 Sep. 19, 2008 Page 73 of 1270 REJ09B0466-0100 Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct (Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 General register contents Register indirect (@ERn) 0 31 24 23 0 Don't care op 3 r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 31 General register contents 0 31 24 23 0 op r disp 31 Sign extension Don't care 0 disp 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don't care op r 31 1, 2, or 4 * Register indirect with pre-decrement @-ERn 0 General register contents 31 24 23 0 Don't care op r Operand Size Byte Word Longword 1, 2, or 4 Offset 1 2 4 Rev. 1.00 Sep. 19, 2008 Page 74 of 1270 REJ09B0466-0100 Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 24 23 16 15 0 Don't care Sign extension @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode* 31 op abs H'000000 15 87 abs 0 0 Memory contents 31 24 23 16 15 H'00 0 Don't care * Advanced mode 31 op abs 31 Memory contents 87 H'000000 abs 0 31 24 23 Don't care 0 0 Note: * Normal mode is not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 75 of 1270 REJ09B0466-0100 Section 2 CPU 2.8 Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. * Reset State The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program Execution State In this state the CPU executes program instructions in sequence. * Bus-Released State In a product which has a bus master other than the CPU, such as a direct memory access controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further details, refer to section 24, Power-Down Modes. Rev. 1.00 Sep. 19, 2008 Page 76 of 1270 REJ09B0466-0100 Section 2 CPU End of bus request Bus request Program execution state of bu s re Bu qu sr es eq t ue st =0 BY SS EEP tion SL truc ins io = 1 ruct BY nst SS EP i E SL Bus-released state En d of Re ex qu ce es pt tf ion or ha ex nd ce lin pt g ion ha nd lin g En d Sleep mode n est equ pt r erru Int Exception handling state External interrupt request Software standby mode RES = High STBY = High, RES = Low Reset state*1 Reset state Hardware standby mode*2 Power down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever the RES pin goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. In every state, when the STBY pin becomes low, the hardware standby mode is entered. 3. For details, refer to section 24, Power-Down Modes. Figure 2.13 State Transitions Rev. 1.00 Sep. 19, 2008 Page 77 of 1270 REJ09B0466-0100 Section 2 CPU 2.9 2.9.1 Usage Note Usage Notes on Bit-wise Operation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore, special care is necessary to use these instructions for the registers and the ports that include writeonly bit. The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time, if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the flag beforehand. Rev. 1.00 Sep. 19, 2008 Page 78 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group have five operating modes (modes 1 to 4 and 7). The operating mode is selected by the setting of mode pins (MD2 to MD0). Modes 1, 2, and 4 are externally expanded modes in which the CPU can access an external memory and peripheral devices. In an externally expanded mode, the external address space can be designated as an 8-bit or 16-bit address space for each area by the bus controller at the beginning of program execution. If a 16-bit address space is designated for any one area, the 16bit bus mode is selected. If an 8-bit address space is designated for all areas, the 8-bit bus mode is selected. Mode 7 is a single-chip activation expanded mode in which the CPU can switch to access an external memory and peripheral devices at the beginning of program execution. Mode 3 is a boot mode in which the flash memory can be programmed or erased. For details on the boot mode, refer to section 21, Flash Memory. The settings for pins MD2 to MD0 should not be changed during LSI operation. Table 3.1 MCU Operating Mode 1* 2* 3 4 7 MCU Operating Modes CPU Operating Mode Advanced Advanced Advanced Advanced Advanced External Data Bus Description Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM disabled Boot mode Expanded mode with on-chip ROM enabled Single-chip mode On-Chip ROM Disabled Disabled Enabled Enabled Enabled Initial Value 16 bits 8 bits 8 bits Max. Value 16 bits 16 bits 16 bits 16 bits 16 bits MD2 0 0 0 1 1 MD1 0 1 1 0 1 MD0 1 0 1 0 1 Note: * Only modes 1 and 2 may be used in ROM-less versions. Rev. 1.00 Sep. 19, 2008 Page 79 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to operating mode setting. * * Mode control register (MDCR) System control register (SYSCR) Mode Control Register (MDCR) 3.2.1 MDCR monitors the current operating mode of this LSI. Bit 7 to 3 Bit Name Initial Value All 0 R/W Descriptions Reserved These bits are always read as 0 and cannot be modified. 2 1 0 MDS2 MDS1 MDS0 * * * R R R Mode Select 2 to 0 These bits indicate the input levels at mode pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0, respectively. These bits are read-only bits and so they cannot be modified. The input levels of the MD2 to MD0 pins are latched into these bits when MDCR is read. These latches are canceled by a reset. Note: * Determined by the settings of pins MD2 to MD0. 3.2.2 System Control Register (SYSCR) SYSCR selects saturation operation for the MAC instruction, controls CPU access to the flash memory control registers, sets the external bus mode, and enables or disables on-chip RAM. Rev. 1.00 Sep. 19, 2008 Page 80 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes Bit 7, 6 5 Bit Name MACS Initial Value All 1 0 R/W R/W R/W Descriptions Reserved The initial value should not be modified. MAC Saturation Operation Control Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction performs non-saturation operation 1: MAC instruction performs saturation operation 4 3 FLSHE 0 0 R/W R/W Reserved The initial value should not be modified. Flash Memory Control Register Enable Controls CPU access to the flash memory control registers (FLMCR1, DFPR, and FLMSTR). If this bit is set to 1, the flash memory control registers can be read from and written to. If this bit is cleared to 0, the flash memory control registers are not selected. At this time, the contents of the flash memory control registers are retained. 0 should be written to this bit in LSIs other than the flash memory version. 0: Flash memory control registers are not selected for addresses H'FFFEB0 to H'FFFEB3 1: Flash memory control registers are selected for addresses H'FFFEB0 to H'FFFEB3 2 1 EXPE 0 R/W Reserved This bit is always read as 0 and cannot be modified. External Bus Mode Enable Sets the external bus mode. In modes 1, 2, and 4, this bit is fixed at 1 and cannot be modified. In modes 3 and 7, this bit can be read from and written to. Writing 0 to this bit when its value is 1 should only be carried out when an external bus cycle is not being executed. 0: External address space is disabled 1: External address space is enabled 0 RAME 1 R/W RAM Enable Enables or disables the on-chip RAM. This bit is initialized when the reset state is canceled. 0: On-chip RAM is disabled 1: On-chip RAM is enabled Rev. 1.00 Sep. 19, 2008 Page 81 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H function as bus control signals. The initial bus mode immediately after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access is designated for all areas by the bus controller, the bus mode switches to 8 bits. 3.3.2 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H function as bus control signals. The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access is designated for any one of the areas by the bus controller, the bus mode switches to 16 bits and port E functions as a data bus. 3.3.3 Mode 3 This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for the programming and erasure of the flash memory. Mode 3 is only available in the flash memory version. Rev. 1.00 Sep. 19, 2008 Page 82 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes 3.3.4 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in the on-chip ROM connected to the first half of area 0 is executed. Ports A to C function as input ports immediately after a reset, but can be set to function as an address bus depending on each port register setting. Port D functions as a data bus and parts of ports F to H function as bus control signals. For details on function switching of ports A to C, see section 10, I/O Ports. The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access is designated for any one of the areas by the bus controller, the bus mode switches to 16 bits and port E functions as a data bus. In the flash memory version, user program mode is entered by setting the SWE bit in FMCMDEN to 1. 3.3.5 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, and the LSI starts up in single-chip mode. External address spaces cannot be used in single-chip mode. The initial mode immediately after a reset is single-chip mode, with all I/O ports available for use as input/output ports. However, setting the EXPE bit in SYSCR to 1 switches the mode to an externally expanded mode in which the external address spaces are enabled. When an externally expanded mode is selected, all areas are initially designated as a 16-bit access space. The functions of pins in ports A to H are the same as those in an externally expanded mode with on-chip ROM enabled. In the flash memory version, user program mode is entered by setting the SWE bit in FMCMDEN to 1. Rev. 1.00 Sep. 19, 2008 Page 83 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes 3.3.6 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.2 Port Port A PA7 to PA5 PA4 to PA0 Port B Port C Port D Port E Port F PF7, PF6 PF5, PF4 PF3 PF2 to PF0 Port G PG6 to PG1 PG0 Port H Pin Functions in Each Operating Mode Mode 1 P*/A A A A D P/D* P/C* C P/C* P*/C P*/C P/C* P*/C Mode 2 P*/A A A A D P*/D P/C* C P/C* P*/C P*/C P/C* P*/C P*/C P*/C P*/C P*/C P*/A P*/A P*/D P*/D P*/C P*/A P*/A D P*/D P/C* C P/C* P*/C P*/C P*/C P*/A P*/A P*/D P*/D P*/C Mode 3 P*/A Mode 4 P*/A Mode 7 P*/A [Legend] P: I/O port A: Address bus output D: Data bus input/output C: Control signals, clock input/output *: Immediately after a reset Note: Port H is not supported in the H8S/2424 Group. 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.5 show memory maps in each operating mode. Rev. 1.00 Sep. 19, 2008 Page 84 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes RAM: 64 Kbytes*6/48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 H'000000 ROM: 256 Kbytes RAM: 64 Kbytes*6/48 Kbytes Mode 3 (Boot mode) On-chip ROM H'040000 Reserved area*4 H'080000 External address space External address space/ Reserved area*2*4 H'F00000 Data flash area 8 Kbytes*7 H'F02000 External address space/ Reserved area*2*4 H'FE8000 H'FEC000 H'FF0000 H'FFC000 H'FFC800 H'FFFA00 Internal I/O registers H'FFFF00 External address space H'FFFF20 H'FFFFFF Notes: 1. 2. 3. 4. 5. Internal I/O registers H'FFFF20 H'FFFFFF H'FFFF00 H'FE8000 Reserved area*4 On-chip RAM/External address space/ Reserved area*1*5 On-chip RAM/External address space*1 Reserved area*4 H'FEC000 H'FF0000 H'FFC000 H'FFC800 H'FFFA00 On-chip RAM/Reserved area*3*5 On-chip RAM*3 Reserved area*4 External address space/ Reserved area*2*4 Internal I/O registers External address space/ Reserved area*2*4 Internal I/O registers Reserved area*4 External address space This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0. A reserved area should not be accessed. Area from H'FEC000 to H'FEFFFF in the H8S/24268, H8S/24268R, and H8S/24248 Groups is reserved and should not be accessed. 6. 64-Kbyte version (H8S/24269, H8S/24269R, and H8S/24249) is under development. 7. Data flash is in planning. Figure 3.1 Memory Map in Each Operating Mode (ROM: 256-Kbyte Version): H8S/24269, H8S/24269R, H8S/24268, H8S/24268R, H8S/24249, and H8S/24248 Rev. 1.00 Sep. 19, 2008 Page 85 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes ROM: 256 Kbytes RAM: 64 Kbytes*6 / 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area*4 ROM: 256 Kbytes RAM: 64 Kbytes*6 / 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area*4 H'080000 H'080000 External address space External address space/ Reserved area*2*4 H'F00000 Reserved area*4 H'F02000 External address space H'FE8000 Reserved area*4 H'FEC000 H'FF0000 H'FFC000 H'FFC800 H'FFFA00 H'FFFF00 H'FFFF20 H'FFFFFF Internal I/O registers Internal I/O registers External address space On-chip RAM/External address space/ Reserved area*1*5 On-chip RAM/ External address space*1 H'F00000 Data flash area 8 Kbytes*7 H'F02000 External address space/ Reserved area*2*4 H'FE8000 Reserved area*4 H'FEC000 H'FF0000 H'FFC000 H'FFC800 H'FFFA00 H'FFFF00 H'FFFF20 H'FFFFFF On-chip RAM/External address space/ Reserved area*3*5 On-chip RAM/ External address space*3 Reserved area*4 External address space Reserved area*4 External address space/ Reserved area*2*4 Internal I/O registers External address space/ Reserved area*2*4 Internal I/O registers Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 3. While EXPE = 1, this area is specified as the external address space when RAME = 0 and the on-chip RAM area when RAME = 1. While EXPE = 0, this area is specified as the on-chip RAM area. 4. A reserved area should not be accessed. 5. Area from H'FEC000 to H'FEFFFF in the H8S/24268, H8S/24268R, and H8S/24248 Groups is reserved and should not be accessed. 6. 64-Kbyte version (H8S/24269, H8S/24269R, and H8S/24249) is under development. 7. Data flash is in planning. Figure 3.2 Memory Map in Each Operating Mode (ROM: 256-Kbyte Version): H8S/24269, H8S/24269R, H8S/24249, and H8S/24248 Rev. 1.00 Sep. 19, 2008 Page 86 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes RAM: 48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 H'000000 ROM: 128 Kbytes RAM: 48 Kbytes Mode 3 (Boot mode) On-chip ROM H'020000 Reserved area*4 H'080000 External address space External address space/ Reserved area*2*4 H'F00000 Data flash area 8 Kbytes*5 H'F02000 External address space/ Reserved area*2*4 H'FE8000 H'FF0000 On-chip RAM/ External address space*1 H'FE8000 Reserved area*4 H'FF0000 On-chip RAM*3 H'FFC000 H'FFC800 H'FFFA00 Internal I/O registers H'FFFF00 External address space Internal I/O registers H'FFFF20 H'FFFFFF Reserved area*4 External address space/ Reserved area*2*4 Internal I/O registers External address space/ Reserved area*2*4 Internal I/O registers Reserved area*4 H'FFC000 H'FFC800 H'FFFA00 H'FFFF00 H'FFFF20 H'FFFFFF Notes: 1. 2. 3. 4. 5. Reserved area*4 External address space This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0. A reserved area should not be accessed. Data flash is in planning. Figure 3.3 Memory Map in Each Operating Mode (ROM: 128-Kbyte Version): H8S/24265, H8S/24265R, and H8S/24245 Rev. 1.00 Sep. 19, 2008 Page 87 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes ROM: 128 Kbytes RAM: 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'000000 ROM: 128 Kbytes RAM: 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) On-chip ROM H'020000 H'020000 Reserved area*4 H'080000 H'080000 Reserved area*4 External address space External address space/ Reserved area*2*4 H'F00000 Reserved area*4 H'F02000 External address space H'FE8000 Reserved area*4 H'FF0000 H'F00000 Data flash area 8 Kbytes*5 H'F02000 External address space/ Reserved area*2*4 H'FE8000 Reserved area*4 H'FF0000 On-chip RAM/ External address space*1 H'FFC000 H'FFC800 H'FFFA00 H'FFFF00 H'FFFF20 H'FFFFFF Internal I/O registers Internal I/O registers H'FFFF00 External address space H'FFFF20 H'FFFFFF Reserved area*4 External address space H'FFFA00 H'FFC000 H'FFC800 On-chip RAM/ External address space*3 Reserved area*4 External address space/ Reserved area*2*4 Internal I/O registers External address space/ Reserved area*2*4 Internal I/O registers Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 3. While EXPE = 1, this area is specified as the external address space when RAME = 0 and the on-chip RAM area when RAME = 1. While EXPE = 0, this area is specified as the on-chip RAM area. 4. A reserved area should not be accessed. 5. Data flash is in planning. Figure 3.4 Memory Map in Each Operating Mode (ROM: 128-Kbyte Version): H8S/24265, H8S/24265R, and H8S/24245 Rev. 1.00 Sep. 19, 2008 Page 88 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes RAM: 64 Kbytes*4 /48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FE8000 H'FEC000 H'FF0000 H'FFC000 H'FFC800 H'FFFA00 Reserved area*2 On-chip RAM/External address space/ Reserved area*1*3 On-chip RAM/External address space*1*3 Reserved area*2 External address space Internal I/O registers H'FFFF00 External address space H'FFFF20 H'FFFFFF Internal I/O registers Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. A reserved area should not be accessed. 3. Area from H'FEC000 to H'FEFFFF in the H8S/24261, H8S/24261R, and H8S/24241 Groups is reserved and should not be accessed. 4. 64-Kbyte version (H8S/24262, H8S/24262R, and H8S/24242) is in planning. Figure 3.5 Memory Map in Each Operating Mode (ROM-Less Version): H8S/24262, H8S/24262R, H8S/24261, H8S/24261R, H8S/24242, and H8S/24241 Rev. 1.00 Sep. 19, 2008 Page 89 of 1270 REJ09B0466-0100 Section 3 MCU Operating Modes Rev. 1.00 Sep. 19, 2008 Page 90 of 1270 REJ09B0466-0100 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal instruction, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Starts when execution of an illegal instruction code is detected. Starts when execution of the currently executed instruction or exception handling ends, if the trace (T) bit in the EXR is set to 1. Starts when the direct transition occurs by execution of the SLEEP instruction. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. *3 Started by execution of a trap instruction (TRAPA) Illegal instruction Trace*1 Direct transition*2 Interrupt Low Trap instruction*4 Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Not available in this LSI. 3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 4. Trap instruction exception handling requests are accepted at all times in program execution state. Rev. 1.00 Sep. 19, 2008 Page 91 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes. Table 4.2 Exception Handling Vector Table Vector Address*1 Exception Source Power-on reset Manual reset*3 Reserved for system use Vector Number 0 1 2 3 Illegal instruction Trace Interrupt (direct transition)* Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved for system use 3 Normal Mode*2 H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0019 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B 4 5 6 7 8 9 10 11 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 16 17 18 19 20 21 22 Rev. 1.00 Sep. 19, 2008 Page 92 of 1270 REJ09B0466-0100 Section 4 Exception Handling Vector Address*1 Exception Source External interrupt IRQ7 IRQ8* IRQ9* 5 5 Vector Number 23 24 25 26 27 28 29 30 31 32 157 5 Normal Mode*2 H'002E to H'002F H'0030 to H'0031 H'0032 to H'0033 H'0034 to H'0035 H'0036 to H'0037 H'0038 to H'0039 H'003A to H'003B H'003C to H'003D H'003E to H'003F H'0040 to H'0041 H'013A to H'013B Advanced Mode H'005C to H'005F H'0060 to H'0063 H'0064 to H'0067 H'0068 to H'006B H'006C to H'006F H'0070 to H'0073 H'0074 to H'0077 H'0078 to H'007B H'007C to H'007F H'0080 to H'0083 H'0274 to H'0277 IRQ10*5 IRQ11* IRQ12* External interrupt IRQ13* IRQ14* IRQ15* Internal interrupt* 4 5 5 5 5 Notes: 1. 2. 3. 4. Lower 16 bits of the address. Not available in this LSI. Not available in this LSI. It is reserved for system use. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. 5. Reserved for system use in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 93 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset this LSI during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. This LSI can also be reset by overflow of the watchdog timer. For details see section 14, Watchdog Timer (WDT). The interrupt control mode is 0 immediately after reset. 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.1 and 4.2 show examples of the reset sequence. Rev. 1.00 Sep. 19, 2008 Page 94 of 1270 REJ09B0466-0100 Section 4 Exception Handling Vector fetch Prefetch of first Internal processing program instruction RES Internal address bus (1) (3) (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled) Rev. 1.00 Sep. 19, 2008 Page 95 of 1270 REJ09B0466-0100 Section 4 Exception Handling Vector fetch Internal processing Prefetch of first program instruction * * * RES Address bus (1) (3) (5) RD HWR, LWR High D15 to D0 (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted. Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled) 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Functions after Reset Release After reset release, MSTPCR is initialized to H'0FFF, EXMSTPCR is initialized to H'FFFF, and all modules except the DMAC, EXDMAC, and DTC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. Rev. 1.00 Sep. 19, 2008 Page 96 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.4 Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.3 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 1 [Legend] 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution I UI I2 to I0 EXR T Trace exception handling cannot be used. -- -- 0 4.5 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. The interrupt exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. Rev. 1.00 Sep. 19, 2008 Page 97 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.6 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI I2 to I0 EXR T 0 Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution Rev. 1.00 Sep. 19, 2008 Page 98 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.7 Illegal Instruction Exception Handling Illegal instruction exception handling starts when the CPU executing an illegal instruction code is detected. Illegal instruction exception handling can be executed at all times in the program execution state. The illegal instruction exception handling is as follows: 1. The values in the PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the exception is generated, the start address of the exception service routine is loaded from the vector table to the PC, and program execution starts from that address. Table 4.5 shows the status of CCR and EXR after execution of illegal instruction exception handling. Table 4.5 Status of CCR and EXR after Illegal Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI T 0 EXR I2 to I0 Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution Illegal instruction codes will not be searched for in the fields that do not affect instruction definitions, such as the EA extension or register fields. Instruction codes for an instruction formed with several words are detected independently, and combined instruction codes are not detected. Undefined instruction codes must not be executed. The general register contents after execution of an undefined instruction code or illegal instruction exception handling cannot be guaranteed. The stack pointer during illegal instruction exception handling and the PC value that will be saved are also not guaranteed. Rev. 1.00 Sep. 19, 2008 Page 99 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.8 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal Modes*2 SP EXR Reserved*1 SP CCR CCR*1 PC (16 bits) CCR CCR*1 PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) CCR PC (24 bits) Interrupt control mode 0 Notes: 1. Ignored on return. 2. Normal modes are not available in this LSI. Interrupt control mode 2 Figure 4.3 Stack Status after Exception Handling Rev. 1.00 Sep. 19, 2008 Page 100 of 1270 REJ09B0466-0100 Section 4 Exception Handling 4.9 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation when the SP value is odd. Address CCR SP PC SP R1L H'FFFEFA H'FFFEFB PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF TRAP instruction executed SP set to H'FFFEFF Legend: CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer MOV.B R1L, @-ER7 Contents of CCR lost Data saved above SP Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.4 Operation when SP Value Is Odd Rev. 1.00 Sep. 19, 2008 Page 101 of 1270 REJ09B0466-0100 Section 4 Exception Handling Rev. 1.00 Sep. 19, 2008 Page 102 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * External interrupt pins NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQn-A and IRQn-B. Note: n = 15 to 0 for H8S/2426 Group, n = 7 to 0 for H8S/2424 Group * DTC and DMAC control DTC and DMAC activations are performed by means of interrupts. Rev. 1.00 Sep. 19, 2008 Page 103 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 INTCR NMIEG NMI input IRQ input ITSR Internal interrupt sources SWDTEND to SSTXI IPR Interrupt controller Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR: IRQ status register IPR: Interrupt priority register INTCR: Interrupt control register ITSR: IRQ pin select register NMI input unit IRQ input unit ISR ISCR IER Priority determination I I2 to I0 Interrupt request Vector number CPU CCR EXR Figure 5.1 Block Diagram of Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 104 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Name NMI IRQ15-A to IRQ0-A* IRQ15-B to IRQ0-B* Note: * Pin Configuration I/O Input Input Function Nonmaskable external interrupt Rising or falling edge can be selected. Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected. IRQ7-A to IRQ0-A and IRQ7-B to IRQ0-B in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 105 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. * * * * * * * * * * * * * * * * * * * * * Interrupt control register (INTCR) IRQ sense control register H (ISCRH) IRQ sense control register L (ISCRL) IRQ enable register (IER) IRQ status register (ISR) IRQ pin select register (ITSR) Software standby release IRQ enable register (SSIER) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Interrupt priority register H (IPRH) Interrupt priority register I (IPRI) Interrupt priority register J (IPRJ) Interrupt priority register K (IPRK) Interrupt priority register L (IPRL) Interrupt priority register M (IPRM) Interrupt priority register N (IPRN) Rev. 1.00 Sep. 19, 2008 Page 106 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and the initial value should not be changed. 5 4 INTM1 INTM0 0 0 R/W R/W Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0, and IPR. 11: Setting prohibited. 3 NMIEG 0 R/W NMI Edge Select Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input 2 to 0 -- All 0 -- Reserved These bits are always read as 0 and the initial value should not be changed. Rev. 1.00 Sep. 19, 2008 Page 107 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.2 Interrupt Priority Registers A to N (IPRA to IPRN) IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding interrupt. IPR should be read in word size. Bit 15 Bit Name -- Initial Value 0 R/W -- Description Reserved This bit is always read as 0 and the initial value should not be changed. 14 13 12 IPR14 IPR13 IPR12 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 11 -- 0 -- Reserved This bit is always read as 0 and the initial value should not be changed. 10 9 8 IPR10 IPR9 IPR8 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Rev. 1.00 Sep. 19, 2008 Page 108 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit 7 Bit Name -- Initial Value 0 R/W -- Description Reserved This bit is always read as 0 and the initial value should not be changed. 6 5 4 IPR6 IPR5 IPR4 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Reserved This bit is always read as 0 and the initial value should not be changed. 3 -- 0 -- 2 1 0 IPR2 IPR1 IPR0 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Rev. 1.00 Sep. 19, 2008 Page 109 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit 15 Bit Name IRQ15E Initial Value 0 R/W R/W Description IRQ15 Enable* The IRQ15 interrupt request is enabled when this bit is 1. 14 IRQ14E 0 R/W IRQ14 Enable* The IRQ14 interrupt request is enabled when this bit is 1. 13 IRQ13E 0 R/W IRQ13 Enable* The IRQ13 interrupt request is enabled when this bit is 1. 12 IRQ12E 0 R/W IRQ12 Enable* The IRQ12 interrupt request is enabled when this bit is 1. 11 IRQ11E 0 R/W IRQ11 Enable* The IRQ11 interrupt request is enabled when this bit is 1. 10 IRQ10E 0 R/W IRQ10 Enable* The IRQ10 interrupt request is enabled when this bit is 1. 9 IRQ9E 0 R/W IRQ9 Enable* The IRQ9 interrupt request is enabled when this bit is 1. 8 IRQ8E 0 R/W IRQ8 Enable* The IRQ8 interrupt request is enabled when this bit is 1. 7 IRQ7E 0 R/W IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. 6 IRQ6E 0 R/W IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1. Rev. 1.00 Sep. 19, 2008 Page 110 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit 5 Bit Name IRQ5E Initial Value 0 R/W R/W Description IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. 1 IRQ1E 0 R/W IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. 0 IRQ0E 0 R/W IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. Note: * These bits are reserved in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 111 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0. * ISCRH (H8S/2426 Group only) Bit 15 14 Bit Name IRQ15SCB IRQ15SCA Initial Value 0 0 R/W R/W R/W Description IRQ15 Sense Control B IRQ15 Sense Control A 00: Interrupt request generated at IRQ15 input low level 01: Interrupt request generated at falling edge of IRQ15 input 10: Interrupt request generated at rising edge of IRQ15 input 11: Interrupt request generated at both falling and rising edges of IRQ15 input 13 12 IRQ14SCB IRQ14SCA 0 0 R/W R/W IRQ14 Sense Control B IRQ14 Sense Control A 00: Interrupt request generated at IRQ14 input low level 01: Interrupt request generated at falling edge of IRQ14 input 10: Interrupt request generated at rising edge of IRQ14 input 11: Interrupt request generated at both falling and rising edges of IRQ14 input 11 10 IRQ13SCB IRQ13SCA 0 0 R/W R/W IRQ13 Sense Control B IRQ13 Sense Control A 00: Interrupt request generated at IRQ13 input low level 01: Interrupt request generated at falling edge of IRQ13 input 10: Interrupt request generated at rising edge of IRQ13 input 11: Interrupt request generated at both falling and rising edges of IRQ13 input Rev. 1.00 Sep. 19, 2008 Page 112 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit 9 8 Bit Name IRQ12SCB IRQ12SCA Initial Value 0 0 R/W R/W R/W Description IRQ12 Sense Control B IRQ12 Sense Control A 00: Interrupt request generated at IRQ12 input low level 01: Interrupt request generated at falling edge of IRQ12 input 10: Interrupt request generated at rising edge of IRQ12 input 11: Interrupt request generated at both falling and rising edges of IRQ12 input 7 6 IRQ11SCB IRQ11SCA 0 0 R/W R/W IRQ11 Sense Control B IRQ11 Sense Control A 00: Interrupt request generated at IRQ11 input low level 01: Interrupt request generated at falling edge of IRQ11 input 10: Interrupt request generated at rising edge of IRQ11 input 11: Interrupt request generated at both falling and rising edges of IRQ11 input 5 4 IRQ10SCB IRQ10SCA 0 0 R/W R/W IRQ10 Sense Control B IRQ10 Sense Control A 00: Interrupt request generated at IRQ10 input low level 01: Interrupt request generated at falling edge of IRQ10 input 10: Interrupt request generated at rising edge of IRQ10 input 11: Interrupt request generated at both falling and rising edges of IRQ10 input Rev. 1.00 Sep. 19, 2008 Page 113 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit 3 2 Bit Name IRQ9SCB IRQ9SCA Initial Value 0 0 R/W R/W R/W Description IRQ9 Sense Control B IRQ9 Sense Control A 00: Interrupt request generated at IRQ9 input low level 01: Interrupt request generated at falling edge of IRQ9 input 10: Interrupt request generated at rising edge of IRQ9 input 11: Interrupt request generated at both falling and rising edges of IRQ9 input 1 0 IRQ8SCB IRQ8SCA 0 0 R/W R/W IRQ8 Sense Control B IRQ8 Sense Control A 00: Interrupt request generated at IRQ8 input low level 01: Interrupt request generated at falling edge of IRQ8 input 10: Interrupt request generated at rising edge of IRQ8 input 11: Interrupt request generated at both falling and rising edges of IRQ8 input Rev. 1.00 Sep. 19, 2008 Page 114 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller * ISCRL Bit 15 14 Bit Name IRQ7SCB IRQ7SCA Initial Value 0 0 R/W R/W R/W Description IRQ7 Sense Control B IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input low level 01: Interrupt request generated at falling edge of IRQ7 input 10: Interrupt request generated at rising edge of IRQ7 input 11: Interrupt request generated at both falling and rising edges of IRQ7 input 13 12 IRQ6SCB IRQ6SCA 0 0 R/W R/W IRQ6 Sense Control B IRQ6 Sense Control A 00: Interrupt request generated at IRQ6 input low level 01: Interrupt request generated at falling edge of IRQ6 input 10: Interrupt request generated at rising edge of IRQ6 input 11: Interrupt request generated at both falling and rising edges of IRQ6 input 11 10 IRQ5SCB IRQ5SCA 0 0 R/W R/W IRQ5 Sense Control B IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input low level 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input Rev. 1.00 Sep. 19, 2008 Page 115 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit 9 8 Bit Name IRQ4SCB IRQ4SCA Initial Value 0 0 R/W R/W R/W Description IRQ4 Sense Control B IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 6 IRQ3SCB IRQ3SCA 0 0 R/W R/W IRQ3 Sense Control B IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input low level 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input 5 4 IRQ2SCB IRQ2SCA 0 0 R/W R/W IRQ2 Sense Control B IRQ2 Sense Control A 00: Interrupt request generated at IRQ2 input low level 01: Interrupt request generated at falling edge of IRQ2 input 10: Interrupt request generated at rising edge of IRQ2 input 11: Interrupt request generated at both falling and rising edges of IRQ2 input Rev. 1.00 Sep. 19, 2008 Page 116 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit 3 2 Bit Name IRQ1SCB IRQ1SCA Initial Value 0 0 R/W R/W R/W Description IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 0 IRQ0SCB IRQ0SCA 0 0 R/W R/W IRQ0 Sense Control B IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input low level 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input Rev. 1.00 Sep. 19, 2008 Page 117 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name IRQ15F* IRQ14F* IRQ13F* IRQ12F* IRQ11F* IRQ10F* IRQ9F* IRQ8F* IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 2 2 2 2 2 2 2 2 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Description [Setting condition] When the interrupt source selected by ISCR occurs [Clearing conditions] * * Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 * * Notes: 1. Only 0 can be written, to clear the flag. 2. These bits are reserved in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 118 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ15 to IRQ0. * H8S/2426 Group Bit 15 Bit Name ITS15 Initial Value 0 R/W R/W Description Selects the IRQ15 input pin. 0: PF2/IRQ15-A selected 1: P27/IRQ15-B selected 14 ITS14 0 R/W Selects the IRQ14 input pin. 0: PF1/IRQ14-A selected 1: P26/IRQ14-B selected 13 ITS13 0 R/W Selects the IRQ13 input pin. 0: P65/IRQ13-A selected 1: P25/IRQ13-B selected 12 ITS12 0 R/W Selects the IRQ12 input pin. 0: P64/IRQ12-A selected 1: P24/IRQ12-B selected 11 ITS11 0 R/W Selects the IRQ11 input pin. 0: P63/IRQ11-A selected 1: P23/IRQ11-B selected 10 ITS10 0 R/W Selects the IRQ10 input pin. 0: P62/IRQ10-A selected 1: P22/IRQ10-B selected 9 ITS9 0 R/W Selects the IRQ9 input pin. 0: P61/IRQ9-A selected 1: P21/IRQ9-B selected 8 ITS8 0 R/W Selects the IRQ8 input pin. 0: P60/IRQ8-A selected 1: P20/IRQ8-B selected 7 ITS7 0 R/W Selects the IRQ7 input pin. 0: PA7/IRQ7-A selected 1: PH3/IRQ7-B selected Rev. 1.00 Sep. 19, 2008 Page 119 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Bit 6 Bit Name ITS6 Initial Value 0 R/W R/W Description Selects the IRQ6 input pin. 0: PA6/IRQ6-A selected 1: PH2/IRQ6-B selected 5 ITS5 0 R/W Selects the IRQ5 input pin. 0: PA5/IRQ5-A selected 1: P85/IRQ5-B selected 4 ITS4 0 R/W Selects the IRQ4 input pin. 0: PA4/IRQ4-A selected 1: P84/IRQ4-B selected 3 ITS3 0 R/W Selects the IRQ3 input pin. 0: P53/IRQ3-A selected 1: P83/IRQ3-B selected 2 ITS2 0 R/W Selects the IRQ2 input pin. 0: P52/IRQ2-A selected 1: P82/IRQ2-B selected 1 ITS1 0 R/W Selects the IRQ1 input pin. 0: P51/IRQ1-A selected 1: P81/IRQ1-B selected 0 ITS0 0 R/W Selects the IRQ0 input pin. 0: P50/IRQ0-A selected 1: P80/IRQ0-B selected Rev. 1.00 Sep. 19, 2008 Page 120 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller * H8S/2424 Group Bit Bit Name Initial Value R/W All 0 0 R/W R/W Description Reserved The initial value should not be changed. 7 ITS7 Selects the IRQ7 input pin. 0: PA7/IRQ7-A selected 1: P47/IRQ7-B selected 6 ITS6 0 R/W Selects the IRQ6 input pin. 0: PA6/IRQ6-A selected 1: P46/IRQ6-B selected 5 ITS5 0 R/W Selects the IRQ5 input pin. 0: PA5/IRQ5-A selected 1: P45/IRQ5-B selected 4 ITS4 0 R/W Selects the IRQ4 input pin. 0: PA4/IRQ4-A selected 1: P44/IRQ4-B selected 3 ITS3 0 R/W Selects the IRQ3 input pin. 0: P53/IRQ3-A selected 1: P43/IRQ3-B selected 2 ITS2 0 R/W Selects the IRQ2 input pin. 0: P52/IRQ2-A selected 1: P42/IRQ2-B selected 1 ITS1 0 R/W Selects the IRQ1 input pin. 0: P51/IRQ1-A selected 1: P41/IRQ1-B selected 0 ITS0 0 R/W Selects the IRQ0 input pin. 0: P50/IRQ0-A selected 1: P40/IRQ0-B selected 15 to 8 -- Rev. 1.00 Sep. 19, 2008 Page 121 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name SSI15* SSI14* SSI13* SSI12* SSI11* SSI10* SSI9* SSI8* SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Software Standby Release IRQ Setting These bits select the IRQn pins used to recover from the software standby state. 0: IRQn requests are not sampled in the software standby state (Initial value when n = 15 to 3) 1: When an IRQn request occurs in the software standby state, the chip recovers from the software standby state after the elapse of the oscillation settling time (Initial value when n = 2 to 0) These bits are reserved in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 122 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupts The H8S/2426 Group and H8S/2426R Group each have seventeen external interrupts: NMI and IRQ15 to IRQ0. The H8S/2424 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore the chip from software standby mode. NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQn Interrupts (n = 0 to 15 for H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for H8S/2424 Group): An IRQn interrupt is requested by an input signal at the IRQn pin. The IRQn interrupts have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at the IRQn pin. * Enabling or disabling of IRQn interrupt requests can be selected with IER. * The interrupt priority level can be set with IPR. * The status of IRQn interrupt requests is indicated in ISR. ISR flags can be cleared to 0 by software. When IRQn interrupt requests occur at low level of the IRQn pin, the corresponding IRQ pin should be held low until an interrupt handling starts. Then the corresponding IRQ pin should be set to high in the interrupt handling routine and clear the IRQnF bit in ISR to 0. Interrupts may not be executed when the corresponding IRQ pin is set to high before the interrupt handling starts. Detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. Rev. 1.00 Sep. 19, 2008 Page 123 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller A block diagram of IRQn interrupts is shown in figure 5.2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/ level detection circuit S R Clear signal Q IRQn interrupt request IRQn input Note: n = 0 to 15 for H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for H8S/2424 Group Figure 5.2 Block Diagram of IRQ Interrupts 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request. * When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt control mode or CPU interrupt mask bit. Rev. 1.00 Sep. 19, 2008 Page 124 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector 1 Address* Vector Number 7 16 17 18 19 20 21 22 23 2 Interrupt Source External pin Origin of Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8* IRQ9* Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C IPR IPRA14 to IPRA12 IPRA10 to IPRA8 IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB14 to IPRB12 IPRB10 to IPRB8 IPRB6 to IPRB4 IPRB2 to IPRB0 IPRC14 to IPRC12 IPRC10 to IPRC8 IPRC6 to IPRC4 IPRC2 to IPRC0 IPRD14 to IPRD12 IPRD10 to IPRD8 IPRD6 to IPRD4 IPRD2 to IPRD0 IPRE14 to IPRE12 IPRE10 to IPRE8 IPRE6 to IPRE4 IPRE2 to IPRE0 Priority High DTC Activation DMAC Activation 24 25 2 2 IRQ10* IRQ11* IRQ12* IRQ13* IRQ14* 26 27 28 29 30 31 32 33 2 2 2 2 IRQ15* DTC WDT Refresh controller 2 SWDTEND WOVI Low Reserved for 34 system use CMI 35 Rev. 1.00 Sep. 19, 2008 Page 125 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source Vector 1 Address* Vector Number Advanced Mode H'0090 H'0094 H'0098 H'009C H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC Low IPRG10 to IPRG8 IPRG14 to IPRG12 IPRF2 to IPRF0 IPRF6 to IPRF4 IPRF6 to IPRF4 IPRF10 to IPRF8 IPR IPRF14 to IPRF12 Priority High DTC Activation DMAC Activation Reserved for 36 system use 37 ADI0 38 A/D_0 Reserved for 39 system use TPU_0 TGI0A TGI0B TGI0C TGI0D TCI0V 40 41 42 43 44 Reserved for 45 system use 46 47 TPU_1 TGI1A TGI1B TCI1V TCI1U TPU_2 TGI2A TGI2B TCI2V TCI2U TPU_3 TGI3A TGI3B TGI3C TGI3D TCI3V 48 49 50 51 52 53 54 55 56 57 58 59 60 Reserved for 61 system use 62 63 Rev. 1.00 Sep. 19, 2008 Page 126 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Interrupt Source TPU_4 Origin of Interrupt Source TGI4A TGI4B TCI4V TCI4U Vector 1 Address* Vector Number 64 65 66 67 68 69 70 71 72 73 74 Advanced Mode H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C IPRH0 to IPRH0 IPRI14 to IPRI12 IPRI10 to IPRI8 IPRI6 to IPRI4 Low IPRH6 to IPRH4 IPRH14 to IPRH12 IPRH14 to IPRH12 IPRG2 to IPRG0 IPR IPRG6 to IPRG4 Priority High DTC Activation DMAC Activation TPU_5 TGI5A TGI5B TCI5V TCI5U TMR_0 CMIA0 CMIB0 OVI0 Reserved for 75 system use TMR_1 CMIA1 CMIB1 OVI1 76 77 78 IPRH10 to IPRH8 Reserved for 79 system use DMAC DMTEND0A 80 DMTEND0B 81 DMTEND1A 82 DMTEND1B 83 EXDMAC* Reserved for 84 system use 85 EXDMTEND 86 2 EXDMTEND 87 3 2 Rev. 1.00 Sep. 19, 2008 Page 127 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Interrupt Source SCI_0 Origin of Interrupt Source ERI0 RXI0 TXI0 TEI0 Vector 1 Address* Vector Number 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Advanced Mode H'0160 H'0164 H'0168 H'016C H'0170 H'0174 H'0178 H'017C H'0180 H'0184 H'0188 H'018C H'0190 H'0194 H'0198 H'019C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 H'01B8 H'01BC H'01C0 H'01C4 H'01C8 H'01CC Low IPRK10 to IPRK8 IPRK14 to IPRK12 IPRJ2 to IPRJ0 IPRJ6 to IPRJ4 IPRJ10 to IPRJ8 IPRJ14 to IPRJ12 IPR IPRI2 to IPRI0 Priority High DTC Activation DMAC Activation SCI_1 ERI1 RXI1 TXI1 TEI1 SCI_2 ERI2 RXI2 TXI2 TEI2 SCI_3 ERI3 RXI3 TXI3 TEI3 SCI_4 ERI4 RXI4 TXI4 TEI4 Reserved for 108 system use 109 110 111 A/D_1 ADI1 112 Reserved for 113 system use 114 115 Rev. 1.00 Sep. 19, 2008 Page 128 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Interrupt Source IIC2_0 Origin of Interrupt Source IICI0 Vector 1 Address* Vector Number 116 Advanced Mode H'01D0 H'01D4 H'01D8 H'01DC H'01E0 H'01E4 H'01E8 H'01EC H'01F0 H'01F4 H'01F8 H'01FC H'0200 H'0204 H'0208 H'020C H'0210 H'0214 H'0218 H'021C H'0220 H'0224 H'0228 H'022C H'0230 H'0234 Low IPRL2 to IPRL0 IPRL6 to IPRL4 IPRL10 to IPRL8 IPRL14 to IPRL12 IPRK2 to IPRK0 IPR IPRK6 to IPRK4 Priority High DTC Activation DMAC Activation Reserved for 117 system use IIC2_1 IICI1 118 Reserved for 119 system use TPU_6 TGI6A TGI6B TGI6C TGI6D TCI6V TPU_7 TGI7A TGI7B TCI7V TCI7U TPU_8 TGI8A TGI8B TCI8V TCI8U TPU_9 TGI9A TGI9B TGI9C TGI9D TCI9V TPU_10 TGI10A TGI10B TCI10V TCI10U 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Rev. 1.00 Sep. 19, 2008 Page 129 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Interrupt Source TPU_11 Origin of Interrupt Source TGI11A TGI11B TCI11V TCI11U Vector 1 Address* Vector Number 142 143 144 145 Advanced Mode H'0238 H'023C H'0240 H'0244 H'0248 H'024C H'0250 H'0254 H'0258 H'025C H'0260 H'0264 H'0268 H'026C H'0270 H'0274 H'0278 H'027C H'0280 H'0284 H'0288 H'028C H'0290 H'0294 H'0298 H'029C H'02A0 H'02A4 Low IPRN2 to IPRN0 IPRN6 to IPRN4 IPRN10 to IPRN8 IPRN14 to IPRN12 IPRM2 to IPRM0 IPRM6 to IPRM4 IPRM10 to IPRM8 IPR IPRM14 to IPRM12 Priority High DTC Activation DMAC Activation Reserved for 146 system use 147 148 149 150 151 152 IIC2_2 IIC2_3 SSU IICI2 IICI3 SSERI SSRXI SSTXI 153 154 155 156 157 Reserved for 158 system use 159 160 161 162 163 164 165 166 167 168 169 Rev. 1.00 Sep. 19, 2008 Page 130 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source Vector 1 Address* Vector Number Advanced Mode H'02A8 | H'03FC Low IPR Priority High DTC Activation | DMAC Activation | Reserved for 170 system use | 255 Notes: 1. Lower 16 bits of the start address. 2. Not supported in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 131 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Priority Setting Registers Default Interrupt Mask Bits I Interrupt Control Mode 0 Description The priorities of interrupt sources are fixed at the default settings. Interrupt sources except for NMI is masked by the I bit. 8 priority levels except for NMI can be set with IPR. 8-level interrupt mask control is performed by bits I2 to I0. 2 IPR I2 to I0 Rev. 1.00 Sep. 19, 2008 Page 132 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit of CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00 Sep. 19, 2008 Page 133 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes No NMI No I=0 Yes No Hold pending No IRQ0 Yes No IRQ1 Yes SSTXI Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 1.00 Sep. 19, 2008 Page 134 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00 Sep. 19, 2008 Page 135 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes No Level 1 interrupt? Mask level 5 or below? Yes Mask level 0? Yes No Yes No No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 1.00 Sep. 19, 2008 Page 136 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 1.00 Sep. 19, 2008 Page 137 of 1270 REJ09B0466-0100 REJ09B0466-0100 Interrupt acceptance Internal operation Stack Vector fetch Internal operation Interrupt handling routine instruction prefetch (1) (3) (5) (7) (9) (11) (13) (2) (4) (6) (8) (10) (12) (14) (6) (8) (9) (11) (10) (12) (13) (14) Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine Section 5 Interrupt Controller Interrupt level determination Instruction Wait for end of instruction prefetch Rev. 1.00 Sep. 19, 2008 Page 138 of 1270 Interrupt request signal Internal address bus Internal read signal Internal write signal Figure 5.5 Interrupt Exception Handling Internal data bus (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.4 Interrupt Response Times Normal Mode*5 Interrupt control mode 0 3 Interrupt control mode 2 3 1 to 19+2*SI 3*SK SI 2*SI 2 12 to 32 Advanced Mode Interrupt control mode 0 3 Interrupt control mode 2 3 No. 1 2 3 4 5 6 Execution Status Interrupt priority determination*1 Number of wait states until executing 1 to 19 2 +2*SI instruction ends* PC, CCR, EXR stack save Vector fetch Instruction fetch* 3 4 1 to 19+2*SI 1 to 19+2*SI 2*SK 2*SI 2*SI 2 12 to 32 3*SK 2*SI 2*SI 2 13 to 33 2*SK SI 2*SI 2 11 to 31 Internal processing* Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in this LSI. Rev. 1.00 Sep. 19, 2008 Page 139 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus 2-State Access 2 3-State Access 3+m Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK Internal Memory 1 2-State Access 4 3-State Access 6+2m Legend: m: Number of wait states in an external device access. 5.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: * * * * Interrupt request to CPU Activation request to DTC Activation request to DMAC Selection of a number of the above For details of interrupt requests that can be used to activate the DTC and DMAC, see table 5.2 and section 9, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC). Rev. 1.00 Sep. 19, 2008 Page 140 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.7 5.7.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU's TIER_0 register is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TIER_0 write cycle by CPU TCIV exception handling Internal address bus TIER_0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.6 Conflict between Interrupt Generation and Disabling Rev. 1.00 Sep. 19, 2008 Page 141 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.7.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNEL1 R4,R4 5.7.5 Change of IRQ Pin Select Register (ITSR) Setting When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15 for H8S/2426 Group, n = 0 to 7 for H8S/2424 Group) of ISR may be set to 1 at the unintended timing if the selected pin level before the change is different from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 15 for H8S/2426 Group, n = 0 to 7 for H8S/2424 Group) is enabled, the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be cleared to 0. Rev. 1.00 Sep. 19, 2008 Page 142 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller 5.7.6 IRQ Status Register (ISR) Depending on the pin status following a reset, IRQnF may be set to 1. Therefore, always read ISR and clear it to 0 after resets. Rev. 1.00 Sep. 19, 2008 Page 143 of 1270 REJ09B0466-0100 Section 5 Interrupt Controller Rev. 1.00 Sep. 19, 2008 Page 144 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus mastershipthe CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1. Note: * Not supported by the H8S/2424 Group. 6.1 Features * Manages external address space in area units Manages the external address space divided into eight areas of 2 Mbytes Bus specifications can be set independently for each area Burst ROM, DRAM, synchronous DRAM*1, and address/data multiplexed I/O interfaces can be set * Basic bus interface Chip select signals (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait cycles can be inserted for each area Extension cycles can be inserted while CS is asserted for each area Wait cycles can be inserted by the WAIT pin The negation timing of the read strobe signal (RD) can be modified * Burst ROM interface Burst ROM interface can be set independently for areas 0 and 1 * Address/data multiplexed I/O interface Address/data multiplexed I/O interface can be set for areas 6 and 7 * DRAM interface DRAM interface can be set for areas 2 to 5 * Synchronous DRAM interface*1 Continuous synchronous DRAM space can be set for areas 2 to 5 Rev. 1.00 Sep. 19, 2008 Page 145 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) * Idle cycle insertion Idle cycles can be inserted between external read cycles to different areas Idle cycles can be inserted before the write cycle after a read cycle Idle cycles can be inserted before the read cycle after a write cycle * Write buffer function External write cycles and internal accesses can be executed in parallel DMAC single address transfers and internal accesses can be executed in parallel * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, DTC, and EXDMAC*2 Notes: 1. Not supported by the H8S/2426 Group and H8S/2424 Group. 2. Not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 146 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) EXDMAC address bus Internal address bus Address selector Area decoder CS7 to CS0 External bus controller WAIT BREQ BACK BREQO Internal bus master bus request signal EXDMAC bus request signal Internal bus master bus acknowledge signal EXDMAC bus acknowledge signal External bus arbiter External bus control signals Internal bus control signals Internal bus controller CPU bus request signal DTC bus request signal DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal Internal bus arbiter Control registers Internal data bus ABWCR ASTCR DRAMCR DRACCRH DRACCRL REFCR RTCNT CSACRL RTCOR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR CSACRH BROMCRH BROMCRL BCR MPXCR Legend: ABWCR ASTCR WTCRAH, WTCRAL, WTCRBH, and WTCRBL RDNCR CSACRH and CSACRL BROMCRH BROMCRL BCR MPXCR DRAMCR DRACCRH and DRACCRL REFCR RTCNT RTCOR : Bus width control register : Access state control register : Wait control registers AH, AL, BH, and BL : Read strobe timing control register : CS assertion period control registers H and L : Area 0 burst ROM interface control register : Area 1 burst ROM interface control register : Bus control register : Address/data multiplexed I/O control register : DRAM control register : DRAM access control registers H and L : Refresh control register : Refresh timer counter : Refresh time constant register Figure 6.1 Block Diagram of Bus Controller Rev. 1.00 Sep. 19, 2008 Page 147 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Name Address strobe Pin Configuration Symbol AS I/O Output Function Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Signal indicating the timing for latching the address when the address/data multiplexed I/O space is set. Strobe signal indicating that normal space is being read. Strobe signal indicating that normal space is written to, and upper half (D15 to D8) of data bus is enabled or DRAM space write enable signal. Strobe signal indicating that normal space is written to, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that area 0 is selected. Strobe signal indicating that area 1 is selected Strobe signal indicating that area 2 is selected, DRAM row address strobe signal when area 2 is DRAM space or areas 2 to 5 are set as continuous DRAM space, or row address strobe signal of the synchronous DRAM when the synchronous DRAM interface is selected. Strobe signal indicating that area 3 is selected, DRAM row address strobe signal when area 3 is DRAM space, or column address strobe signal of the synchronous DRAM when the synchronous DRAM interface is selected. Address hold AH Output Read High write/write enable RD HWR/WE Output Output Low write LWR Output Chip select 0 Chip select 1 Chip select 2/ row address strobe 2/ row address strobe*1 CS0 CS1 CS2/ RAS2/ RAS*1 Output Output Output Chip select 3/ row address strobe 3/ column address strobe*1 CS3/ RAS3/ CAS*1 Output Rev. 1.00 Sep. 19, 2008 Page 148 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Name Chip select 4/ row address strobe 4/ 1 write enable* Symbol CS4/ RAS4/ WE*1 I/O Output Function Strobe signal indicating that area 4 is selected, DRAM row address strobe signal when area 4 is DRAM space, or write enable signal of the synchronous DRAM when the synchronous DRAM interface is selected. Strobe signal indicating that area 5 is selected, DRAM row address strobe signal when area 5 is DRAM space, or dedicated clock signal for the synchronous DRAM when the synchronous DRAM interface is selected. Strobe signal indicating that area 6 is selected. Strobe signal indicating that area 7 is selected. 16-bit DRAM space upper column address strobe signal, 8-bit DRAM space column address strobe signal, upper data mask signal of 16-bit synchronous DRAM space, or data mask signal of 8-bit synchronous DRAM space. 16-bit DRAM space lower column address strobe signal or lower data mask signal for the 16-bit synchronous DRAM space. Output enable signal for the DRAM space or clock enable signal for the synchronous DRAM space. Wait request signal when accessing external address space. Request signal for release of bus to external bus master. Acknowledge signal indicating that bus has been released to external bus master. External bus request signal used when internal bus master accesses external address space when external bus is released. Chip select 5/ row address strobe 5/ 1 SDRAM* CS5/ Output RAS5/ SDRAM*1 Chip select 6 Chip select 7 Upper column address strobe/ 1 upper data mask enable* CS6 CS7 UCAS/ DQMU*1 Output Output Output Lower column address strobe/ lower data mask enable*1 Output enable/clock enable LCAS/ DQML*1 OE/ CKE*1 WAIT BREQ BACK BREQO Output Output Wait Bus request Bus request acknowledge Bus request output Input Input Output Output Rev. 1.00 Sep. 19, 2008 Page 149 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Name Data transfer acknowledge 1 (DMAC) Data transfer acknowledge 0 (DMAC) Symbol DACK1 I/O Output Function Data transfer acknowledge signal for single address transfer by DMAC channel 1. Data transfer acknowledge signal for single address transfer by DMAC channel 0. Data transfer acknowledge signal for single address transfer by EXDMAC channel 3. Data transfer acknowledge signal for single address transfer by EXDMAC channel 2. DACK0 DACK0 Data transfer acknowledge 3*2 EDACK3*2 Output (EXDMAC) Data transfer acknowledge 2*2 (EXDMAC) EDACK2*2 Output Notes: 1. Not supported by the H8S/2426 Group and H8S/2424 Group 2. Not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 150 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3 Register Descriptions The bus controller has the following registers. * * * * * * * * * * * * * * * * * * Bus width control register (ABWCR) Access state control register (ASTCR) Wait control register AH (WTCRAH) Wait control register AL (WTCRAL) Wait control register BH (WTCRBH) Wait control register BL (WTCRBL) Read strobe timing control register (RDNCR) CS assertion period control register H (CSACRH) CS assertion period control register L (CSACRL) Area 0 burst ROM interface control register (BROMCRH) Area 1 burst ROM interface control register (BROMCRL) Bus control register (BCR) Address/data multiplexed I/O control register (MPXCR) DRAM control register (DRAMCR) DRAM access control register (DRACCR) Refresh control register (REFCR) Refresh timer counter (RTCNT) Refresh time constant register (RTCOR) Rev. 1.00 Sep. 19, 2008 Page 151 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit 7 6 5 4 3 2 1 0 Note: Bit Name ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 * Initial Value* 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Bus Width Control These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. 0: Area n is designated as 16-bit access space 1: Area n is designated as 8-bit access space (n = 7 to 0) In modes 2 and 4, ABWCR is initialized to 1. In modes 1 and 7, ABWCR is initialized to 0. 6.3.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space. Bit 7 6 5 4 3 2 1 0 Bit Name AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Access State Control These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait state insertion is enabled or disabled at the same time. 0: Area n is designated as 2-state access space Wait state insertion in area n access is disabled 1: Area n is designated as 3-state access space Wait state insertion in area n access is enabled (n = 7 to 0) Rev. 1.00 Sep. 19, 2008 Page 152 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM is connected. * WTCRAH Bit 15 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0 and cannot be modified. 14 13 12 W72 W71 W70 1 1 1 R/W R/W R/W Area 7 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 7 while AST7 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 11 -- 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 153 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 10 9 8 Bit Name W62 W61 W60 Initial Value 1 1 1 R/W R/W R/W R/W Description Area 6 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted Rev. 1.00 Sep. 19, 2008 Page 154 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) * WTCRAL Bit 7 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0 and cannot be modified. 6 5 4 W52 W51 W50 1 1 1 R/W R/W R/W Area 5 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 5 while AST5 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 3 -- 0 R Reserved This bit is always read as 0 and cannot be modified. 2 1 0 W42 W41 W40 1 1 1 R/W R/W R/W Area 4 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted Rev. 1.00 Sep. 19, 2008 Page 155 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) * WTCRBH Bit 15 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0 and cannot be modified. 14 13 12 W32 W31 W30 1 1 1 R/W R/W R/W Area 3 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 11 -- 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 156 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 10 9 8 Bit Name W22 W21 W20 Initial Value 1 1 1 R/W R/W R/W R/W Description Area 2 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM* is connected. The setting of area 2 is reflected to the setting of areas 2 to 5. A CAS latency can be set regardless of whether or not an ASTCR wait state insertion is enabled. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 000: Synchronous DRAM of CAS latency 1 is connected to areas 2 to 5. 001: Synchronous DRAM of CAS latency 2 is connected to areas 2 to 5. 010: Synchronous DRAM of CAS latency 3 is connected to areas 2 to 5. 011: Synchronous DRAM of CAS latency 4 is connected to areas 2 to 5. 1XX: Setting prohibited. Legend: Note: * X: Don't care. The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 157 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) * WTCRBL Bit 7 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0 and cannot be modified. 6 5 4 W12 W11 W10 1 1 1 R/W R/W R/W Area 1 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 3 -- 0 R Reserved This bit is always read as 0 and cannot be modified. 2 1 0 W02 W01 W00 1 1 1 R/W R/W R/W Area 0 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 0 while AST0 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted Rev. 1.00 Sep. 19, 2008 Page 158 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit 7 6 5 4 3 2 1 0 Bit Name RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Read Strobe Timing Control 7 to 0 These bits set the negation timing of the read strobe in a corresponding area read access. As shown in figure 6.2, the read strobe for an area for which the RDNn bit is set to 1 is negated one half-state earlier than that for an area for which the RDNn bit is cleared to 0. The read data setup and hold time specifications are also one half-state earlier. 0: In an area n read access, the RD is negated at the end of the read cycle 1: In an area n read access, the RD is negated one half-state before the end of the read cycle (n = 7 to 0) Rev. 1.00 Sep. 19, 2008 Page 159 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) Rev. 1.00 Sep. 19, 2008 Page 160 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL) CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices. * CSACRH Bit 7 6 5 4 3 2 1 0 Bit Name CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description CS and Address Signal Assertion Period Control 1 These bits specify whether or not the Th cycle is to be inserted (see figure 6.3). When an area for which the CSXHn bit is set to 1 is accessed, a one-state Th cycle, in which only the CSn and address signals are asserted, is inserted before the normal access cycle. 0: In area n basic bus interface access, the CSn and address assertion period (Th) is not extended 1: In area n basic bus interface access, the CSn and address assertion period (Th) is extended (n = 7 to 0) * CSACRL Bit 7 6 5 4 3 2 1 0 Bit Name CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description CS and Address Signal Assertion Period Control 2 These bits specify whether or not the Tt cycle shown in figure 6.3 is to be inserted. When an area for which the CSXTn bit is set to 1 is accessed, a one-state Tt cycle, in which only the CSn and address signals are asserted, is inserted after the normal access cycle. 0: In area n basic bus interface access, the CSn and address assertion period (Tt) is not extended 1: In area n basic bus interface access, the CSn and address assertion period (Tt) is extended (n = 7 to 0) Rev. 1.00 Sep. 19, 2008 Page 161 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle Th Address CS RD Read Data HWR, LWR Write Data T1 T2 T3 Tt Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Rev. 1.00 Sep. 19, 2008 Page 162 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. Bit 7 Bit Name BSRMn Initial Value 0 R/W R/W Description Burst ROM Interface Select Selects the basic bus interface or burst ROM interface. 0: Basic bus interface space 1: Burst ROM interface space 6 5 4 BSTSn2 BSTSn1 BSTSn0 0 0 0 R/W R/W R/W Burst Cycle Select These bits select the number of burst cycle states. 000: 1 state 001: 2 states 010: 3 states 011: 4 states 100: 5 states 101: 6 states 110: 7 states 111: 8 states 3 2 1 0 -- -- BSWDn1 BSWDn0 0 0 0 0 R/W R/W R/W R/W Reserved These bits are always read as 0. The initial value should not be changed. Burst Word Number Select These bits select the number of words that can be burst-accessed on the burst ROM interface. 00: Maximum 4 words 01: Maximum 8 words 10: Maximum 16 words 11: Maximum 32 words (n = 1 or 0) Rev. 1.00 Sep. 19, 2008 Page 163 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit 15 Bit Name BRLE Initial Value 0 R/W R/W Description External Bus Release Enable Enables or disables external bus release. 0: External bus release disabled BREQ, BACK, and BREQO pins can be used as I/O ports 1: External bus release enabled 14 BREQOE 0 R/W BREQO Pin Enable Controls outputting the bus request signal (BREQO) to the external bus master in the external bus released state, when an internal bus master performs an external address space access, or when a refresh request is generated. 0: BREQO output disabled BREQO pin can be used as I/O port 1: BREQO output enabled 13 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 12 IDLC 1 R/W Idle Cycle State Number Select Specifies the number of states in the idle cycle set by ICIS2, ICIS1, and ICIS0. 0: Idle cycle comprises 1 state 1: Idle cycle comprises 2 states 11 ICIS1 1 R/W Idle Cycle Insert 1 When consecutive external read cycles are executed in different areas, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted Rev. 1.00 Sep. 19, 2008 Page 164 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 10 Bit Name ICIS0 Initial Value 1 R/W R/W Description Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle or DMAC single address transfer cycle. 0: Write data buffer function not used 1: Write data buffer function used 8 WAITE 0 R/W WAIT Pin Enable Selects enabling or disabling of wait input by the WAIT pin. 0: Wait input by WAIT pin disabled WAIT pin can be used as I/O port 1: Wait input by WAIT pin enabled 7 to 3 -- All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 2 ICIS2 0 R/W Idle Cycle Insert 2 When an external write cycle and external read cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 1, 0 -- All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 165 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) MPXCR is used to make address/data multiplexed I/O interface settings. Bit 7 Bit Name MPXE Initial Value 0 R/W R/W Description Address/Data Multiplexed I/O Interface Enable These bits select the bus interface for areas 6 and 7. 0: Basic bus interface 1: Address/data multiplexed I/O interface 6 to 1 All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 0 ADDEX 0 R/W Address Output Cycle Extension Specifies whether a wait cycle is inserted for the address output cycle of the address/data multiplexed I/O interface. 0: No wait cycle inserted 1: One wait cycle inserted Rev. 1.00 Sep. 19, 2008 Page 166 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.9 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM interface settings. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Bit 15 Bit Name OEE Initial Value 0 R/W R/W Description OE Output Enable The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin. The OE signal is common to all areas designated as DRAM space. When the synchronous DRAM is connected, the CKE signal can be output from the (OE) pin. The CKE signal is common to the continuous synchronous DRAM space. 0: OE/CKE signal output disabled (OE)/(CKE) pin can be used as I/O port 1: OE/CKE signal output enabled 14 RAST 0 R/W RAS Assertion Timing Select Selects whether, in DRAM access, the RAS signal is asserted from the start of the Tr cycle (rising edge of ) or from the falling edge of . Figure 6.4 shows the relationship between the RAST bit setting and the RAS assertion timing. The setting of this bit applies to all areas designated as DRAM space. 0: RAS is asserted from falling edge in Tr cycle 1: RAS is asserted from start of Tr cycle 13 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 167 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 12 Bit Name CAST Initial Value 0 R/W R/W Description Column Address Output Cycle Number Select Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: Column address output cycle comprises 2 states 1: Column address output cycle comprises 3 states 11 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 168 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 10 9 8 Bit Name RMTS2 RMTS1 RMTS0 Initial Value 0 0 0 R/W R/W R/W R/W Description DRAM/Continuous Synchronous DRAM Space Select These bits designate DRAM/continuous synchronous DRAM space for areas 2 to 5. When continuous DRAM space is set, it is possible to connect large-capacity DRAM exceeding 2 Mbytes per area. In this case, the RAS signal is output from the CS2 pin. When continuous synchronous DRAM space is set, it is possible to connect large-capacity synchronous DRAM exceeding 2 Mbytes per area. In this case, the RAS, CAS, and WE signals are output from CS2, CS3, and CS4 pins, respectively. When synchronous DRAM mode is set, the mode registers of the synchronous DRAM can be set. 000: Normal space 001: Normal space in areas 3 to 5 DRAM space in area 2 010: Normal space in areas 4 and 5 DRAM space in areas 2 and 3 011: DRAM space in areas 2 to 5 100: Continuous synchronous DRAM space (setting possible only in H8S/2426R Group) 101: Synchronous DRAM mode setting (setting possible only in H8S/2426R Group) 110: Setting prohibited 111: Continuous DRAM space in areas 2 to 5 7 BE 0 R/W Burst Access Enable Selects enabling or disabling of burst access to areas designated as DRAM/continuous synchronous DRAM space. DRAM/continuous synchronous DRAM space burst access is performed in fast page mode. When using EDO page mode DRAM, the OE signal must be connected. 0: Full access 1: Access in fast page mode Rev. 1.00 Sep. 19, 2008 Page 169 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 6 Bit Name RCDM Initial Value 0 R/W R/W Description RAS Down Mode When access to DRAM space is interrupted by an access to normal space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode). The setting of this bit is valid only when the BE bit is set to 1. If this bit is cleared to 0 when set to 1 in the RAS down state, the RAS down state is cleared at that point, and RAS goes high. When continuous synchronous DRAM space is set, reading from and writing to this bit is enabled. However, the setting does not affect the operation. 0: RAS up mode selected for DRAM space access 1: RAS down mode selected for DRAM space access 5 DDS 0 R/W DMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when DMAC single address transfer is performed on the DRAM/synchronous DRAM. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, DMAC single address transfer is performed in full access mode regardless of the setting of this bit. This bit has no effect on other bus master external accesses or DMAC dual address transfers. 0: Full access is always executed 1: Burst access is enabled Rev. 1.00 Sep. 19, 2008 Page 170 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 4 Bit Name EDDS Initial Value 0 R/W R/W Description EXDMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when EXDMAC single address transfer is performed on the DRAM/synchronous DRAM. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, EXDMAC single address transfer is performed in full access mode regardless of the setting of this bit. This bit has no effect on other bus master external accesses or EXDMAC dual address transfers. 0: Full access is always executed 1: Burst access is enabled 3 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 171 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 2 1 0 Bit Name MXC2 MXC1 MXC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Address Multiplex Select These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison. When the MXC2 bit is set to 1 while continuous synchronous DRAM space is set, the address precharge setting command (Precharge-sel) is output to the upper column address. For details, refer to sections 6.7.2 and 6.8.2, Address Multiplexing. DRAM interface 000: 8-bit shift * When 8-bit access space is designated: Row address bits A23 to A8 used for comparison * When 16-bit access space is designated: Row address bits A23 to A9 used for comparison 001: 9-bit shift * When 8-bit access space is designated: Row address bits A23 to A9 used for comparison * When 16-bit access space is designated: Row address bits A23 to A10 used for comparison 010: 10-bit shift * When 8-bit access space is designated: Row address bits A23 to A10 used for comparison * When 16-bit access space is designated: Row address bits A23 to A11 used for comparison Rev. 1.00 Sep. 19, 2008 Page 172 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 2 1 0 Bit Name MXC2 MXC1 MXC0 Initial Value 0 0 0 R/W R/W R/W R/W Description 011: 11-bit shift * When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift * When 8-bit access space is designated: Row address bits A23 to A8 used for comparison * When 16-bit access space is designated: Row address bits A23 to A9 used for comparison The precharge-sel is A15 to A9 of the column address. 101: 9-bit shift * When 8-bit access space is designated: Row address bits A23 to A9 used for comparison * When 16-bit access space is designated: Row address bits A23 to A10 used for comparison The precharge-sel is A15 to A10 of the column address. 110: 10-bit shift * When 8-bit access space is designated: Row address bits A23 to A10 used for comparison * When 16-bit access space is designated: Row address bits A23 to A11 used for comparison The precharge-sel is A15 to A11 of the column address. Rev. 1.00 Sep. 19, 2008 Page 173 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 2 1 0 Bit Name MXC2 MXC1 MXC0 Initial Value 0 0 0 R/W R/W R/W R/W Description 111: 11-bit shift * When 8-bit access space is designated: Row address bits A23 to A11 used for comparison * When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address. Bus cycle Tp Address RAST = 0 RAS RAST = 1 RAS Row address Column address Tr Tc1 Tc2 UCAS, LCAS Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access) Rev. 1.00 Sep. 19, 2008 Page 174 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.10 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Bit 15 Bit Name DRMI Initial Value 0 R/W R/W Description Idle Cycle Insertion An idle cycle can be inserted after a DRAM/synchronous DRAM access cycle when a continuous normal space access cycle follows a DRAM/synchronous DRAM access cycle. Idle cycle insertion conditions, setting of number of states, etc., comply with settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR register 0: Idle cycle not inserted 1: Idle cycle inserted 14 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 13 12 TPC1 TPC0 0 0 R/W R/W Precharge State Control These bits select the number of states in the RAS precharge cycle in normal access and refreshing. 00: 1 state 01: 2 states 10: 3 states 11: 4 states 11 SDWCD 0* R/W CAS Latency Control Cycle Disabled during Continuous Synchronous DRAM Space Write Access Disables CAS latency control cycle (Tcl) inserted by WTCRB (H) settings during synchronous DRAM write access (see figure 6.5). 0: Enables CAS latency control cycle 1: Disables CAS latency control cycle Rev. 1.00 Sep. 19, 2008 Page 175 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 10 Bit Name Initial Value 0 R/W R/W Description Reserved This bit can be read from or written to. However, the write value should always be 0. 9 8 RCD1 RCD0 0 0 R/W R/W RAS-CAS Wait Control These bits select a wait cycle to be inserted between the RAS assert cycle and CAS assert cycle. A 1- to 4-state wait cycle can be inserted. 00: Wait cycle not inserted 01: 1-state wait cycle inserted 10: 2-state wait cycle inserted 11: 3-state wait cycle inserted 7 to 4 All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 3 CKSPE* 0 R/W Clock Suspend Enable Enables clock suspend mode for extend read data during DMAC and EXDMAC single address transfer with the synchronous DRAM interface. 0: Disables clock suspend mode 1: Enables clock suspend mode 2 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 1 0 RDXC1* RDXC0* 0 0 R/W R/W Read Data Extension Cycle Number Selection Selects the number of read data extension cycle (Tsp) insertion state in clock suspend mode. These bits are valid when the CKSPE bit is set to 1. 00: Inserts 1 state 01: Inserts 2 state 10: Inserts 3 state 11: Inserts 4 state Note: * Not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 176 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS SDWCD 0 CAS WE CKE High DQMU, DQML Data bus PALL Tp ACTV Tr NOP Tc1 WRIT Tc2 NOP Address bus Column address Row address Column address Precharge-sel Row address RAS SDWCD 1 CAS WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 177 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.11 Refresh Control Register (REFCR) REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Bit 15 Bit Name CMF Initial Value 0 R/W R/(W)* Description Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR. [Clearing conditions] * * When 0 is written to CMF after reading CMF = 1 while the RFSHE bit is cleared to 0 When CBR refreshing is executed while the RFSHE bit is set to 1 [Setting condition] When RTCOR = RTCNT 14 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag is set to 1. This bit is valid when refresh control is not performed. When the refresh control is performed, this bit is always cleared to 0 and cannot be modified. 0: Interrupt request by CMF flag disabled 1: Interrupt request by CMF flag enabled 13 12 RCW1 RCW0 0 0 R/W R/W CAS-RAS Wait Control These bits select the number of wait cycles to be inserted between the CAS assert cycle and RAS assert cycle in a DRAM/synchronous DRAM refresh cycle. 00: Wait state not inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted Note: * Only 0 can be written, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 178 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 11 Bit Name -- Initial Value 0 R/W R/W Description Reserved This bit can be read from or written to. However, the write value should always be 0. 10 9 8 RTCK2 RTCK1 RTCK0 0 0 0 R/W R/W R/W Refresh Counter Clock Select These bits select the clock to be used to increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up. 000: Count operation halted 001: Count on /2 010: Count on /8 011: Count on /32 100: Count on /128 101: Count on /512 110: Count on /2048 111: Count on /4096 7 RFSHE 0 R/W Refresh Control Refresh control can be performed. When refresh control is not performed, the refresh timer can be used as an interval timer. 0: Refresh control is not performed 1: Refresh control is performed 6 CBRM 0 R/W CBR Refresh Mode Selects CBR refreshing performed in parallel with other external accesses, or execution of CBR refreshing alone. When the continuous synchronous DRAM space is set, this bit can be read/written, but the setting contents do not affect operations. 0: External access during CAS-before-RAS refreshing is enabled 1: External access during CAS-before-RAS refreshing is disabled Rev. 1.00 Sep. 19, 2008 Page 179 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bit 5 4 Bit Name RLW1 RLW0 Initial Value 0 0 R/W R/W R/W Description Refresh Cycle Wait Control These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle/synchronous DRAM interface autorefresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space. 00: No wait state inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted 3 SLFRF 0 R/W Self-Refresh Enable If this bit is set to 1, DRAM/synchronous DRAM self-refresh mode is selected when a transition is made to the software standby state. This bit is valid when the RFSHE bit is set to 1, enabling refresh operations. It is cleared after recovery from software standby mode. 0: Self-refreshing is disabled 1: Self-refreshing is enabled 2 1 0 TPCS2 TPCS1 TPCS0 0 0 0 R/W R/W R/W Self-Refresh Precharge Cycle Control These bits select the number of states in the precharge cycle immediately after self-refreshing. The number of states in the precharge cycle immediately after self-refreshing are added to the number of states set by bits TPC1 and TPC0 in DRACCR. 000: [TPC set value] states 001: [TPC set value + 1] states 010: [TPC set value + 2] states 011: [TPC set value + 3] states 100: [TPC set value + 4] states 101: [TPC set value + 5] states 110: [TPC set value + 6] states 111: [TPC set value + 7] states Rev. 1.00 Sep. 19, 2008 Page 180 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.3.12 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. 6.3.13 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 1.00 Sep. 19, 2008 Page 181 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.4 6.4.1 Bus Control Area Division The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. In normal mode, a part of area 0, 64-Kbyte address space, is controlled. Figure 6.6 shows an outline of the memory map. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF Figure 6.6 Area Divisions Rev. 1.00 Sep. 19, 2008 Page 182 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.4.2 Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as 16-bit access space, 16-bit bus mode is set. (2) Number of Access States Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the DRAM or synchronous DRAM interface and burst ROM interface, the number of access states may be determined without regard to the setting of ASTCR. When 2-state access space is designated, wait insertion is disabled. When 3-state access space is designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and external waits by means of the WAIT pin. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. (3) Number of Program Wait States When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WTCRA and WTCRB. From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus width, and number of access states and program wait states) for each basic bus interface area. Rev. 1.00 Sep. 19, 2008 Page 183 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Table 6.2 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WTCRA, WTCRB Wn2 0 Wn1 0 Wn0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 1 Bus Specifications (Basic Bus Interface) Bus Width 16 Access States 2 3 Program Wait States 0 0 1 2 3 4 5 6 7 8 2 3 0 0 1 2 3 4 5 6 7 1 0 1 (n = 0 to 7) (4) Read Strobe Timing RDNCR can be used to select either of two negation timings (at the end of the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in the basic bus interface space. (5) Chip Select (CS) Assertion Period Extension States Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Rev. 1.00 Sep. 19, 2008 Page 184 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.4.3 Memory Interfaces The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; an address/data multiplexed I/O interface that allows direct connection of peripheral LSIs that require address/data multiplexing, a DRAM interface that allows direct connection of DRAM; a synchronous DRAM interface that allows direct connection of synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space. An area for which the address/data multiplexed I/O interface is designated functions as address/data multiplexed I/O space, an area for which the DRAM interface is designated functions as DRAM space, an area for which the synchronous DRAM interface is designated functions as continuous synchronous DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space. The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. (1) Area 0 Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the space excluding on-chip ROM is external address space, and in expanded mode with on-chip ROM disabled, all of area 0 is external address space. When area 0 external space is accessed, the CS0 signal can be output. Either the basic bus interface or burst ROM interface can be selected for the memory interface of area 0. (2) Area 1 In externally expanded mode, all of area 1 is external address space. When area 1 external address space is accessed, the CS1 signal can be output. Either the basic bus interface or burst ROM interface can be selected for the memory interface of area 1. Rev. 1.00 Sep. 19, 2008 Page 185 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (3) Areas 2 to 5 In externally expanded mode, areas 2 to 5 are all external address space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. The basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for the memory interface of areas 2 to 5. With the DRAM interface, signals CS2 and CS5 are used as RAS signals. If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM space. If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The OE pin is used as the CKE signal. (4) Area 6 In externally expanded mode, all of area 6 is external space. When area 6 external space is accessed, the CS6 signal can be output. Either the basic bus interface or address/data multiplexed I/O interface can be used for the memory interface of area 6. (5) Area 7 Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode, the space excluding the on-chip RAM and internal I/O registers is external address space. The on-chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in external address space. When area 7 external address space is accessed, the CS7 signal can be output. Either the basic bus interface or address/data multiplexed I/O interface can be used for the memory interface of area 7. Rev. 1.00 Sep. 19, 2008 Page 186 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.4.4 Chip Select Signals This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7 signals output timing. Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit for the port corresponding to the CS0 to CS7 pins. In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when outputting signals CS1 to CS7. In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when outputting signals CS0 to CS7. When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals. When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2426R Group, outputs CS2, CS3, CS4, and CS5 are used as RAS, CAS, WE, and CLK signals. Note: The A23E bit in PFCR1 should be cleared to 0 when CS7 signal is output in the H8S/2424 Group. Bus cycle T1 Address bus Area n external address T2 T3 CSn Figure 6.7 CSn Signal Output Timing (n = 0 to 7) Rev. 1.00 Sep. 19, 2008 Page 187 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.5 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external address space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. (1) 8-Bit Access Space Figure 6.8 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Upper data bus D15 Lower data bus D0 D8 D7 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) (2) 16-Bit Access Space Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. Rev. 1.00 Sep. 19, 2008 Page 188 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus D15 Lower data bus D0 D8 D7 Byte size Byte size Word size Longword size * Even address * Odd address 1st bus cycle 2nd bus cycle Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) 6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.3 Area 8-bit access space 16-bit access space Data Buses Used and Valid Strobes Access Size Byte Read/ Write Read Write Byte Read Address Even Odd Write Even Odd Word Read Write HWR LWR RD HWR, LWR Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Valid Upper Data Bus Lower Data (D15 to D8) Bus (D7 to D0) Valid Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid Note: Hi-Z: High-impedance state Invalid: Input state; input value is ignored. Rev. 1.00 Sep. 19, 2008 Page 189 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.5.3 (1) Basic Timing 8-Bit, 2-State Access Space Figure 6.10 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space Rev. 1.00 Sep. 19, 2008 Page 190 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) 8-Bit, 3-State Access Space Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space Rev. 1.00 Sep. 19, 2008 Page 191 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (3) 16-Bit, 2-State Access Space Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted. Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 192 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 193 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 1.00 Sep. 19, 2008 Page 194 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (4) 16-Bit, 3-State Access Space Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 195 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 196 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev. 1.00 Sep. 19, 2008 Page 197 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.5.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. (1) Program Wait Insertion From 0 to 7 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion Setting the WAITE bit to 1 in BCR enables wait input by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted in accordance with the settings in WTCRA and WTCRB. If the WAIT pin is low at the falling edge of in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting seven or more Tw states, or when changing the number of Tw states to be inserted for different external devices. The WAITE bit setting applies to all areas. Figure 6.18 shows an example of wait state insertion timing. The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input disabled. Rev. 1.00 Sep. 19, 2008 Page 198 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) By program wait T1 T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDNn = 0 Figure 6.18 Example of Wait State Insertion Timing 6.5.5 Read Strobe (RD) Timing The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. Figure 6.19 shows an example of the timing when the read strobe timing is changed in basic bus 3-state access space. When the DMAC or EXDMAC is used in single address mode, note that if the RD timing is changed by setting RDNn to 1, the RD timing will change relative to the rise of DACK or EDACK. Rev. 1.00 Sep. 19, 2008 Page 199 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus DACK, EDACK Figure 6.19 Example of Read Strobe Timing Rev. 1.00 Sep. 19, 2008 Page 200 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.5.6 Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Extension of the CS assertion period can be set for individual areas. With the CS assertion extension period in write access, the data setup and hold times are less stringent since the write data is output to the data bus. Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus 3-state access space. Bus cycle Th Address bus CSn AS Read (when RDNn = 0) RD Data bus Read data T1 T2 T3 Tt HWR, LWR Write Data bus Write data Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended Rev. 1.00 Sep. 19, 2008 Page 201 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0). 6.6 Address/Data Multiplexed I/O Interface If areas 6 and 7 of the external address space are specified as address/data multiplexed I/O space in this LSI, the address/data multiplexed I/O interfacing can be performed. In the address/data multiplexed I/O interface, peripheral LSIs that require address/data multiplexing can be connected directly to this LSI. 6.6.1 Setting Address/Data Multiplexed I/O Space In the address/data multiplexed I/O interface, areas 6 and 7 are designated as the address/data multiplexed I/O space by setting the MPXE bit in MPXCR to 1. 6.6.2 Address/Data Multiplexing With the address/data multiplexed I/O space, the data bus and address bus are multiplexed. Table 6.4 shows the relation between the bus width and corresponding address output. Table 6.4 Bus Width 8 bits Multiplexed Address/Data Data Pins Cycle Address Data PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 A7 D15 A15 D15 A6 D14 A14 D14 A5 D13 A13 D13 A4 D12 A12 D12 A3 D11 A11 D11 A2 D10 A10 D10 A1 D9 A9 D9 A0 D8 A8 D8 A7 D7 PE6 A6 D6 PE5 A5 D5 PE4 A4 D4 PE3 A3 D3 PE2 A2 D2 PE1 A1 D1 PE0 A0 D0 16 bits Address Data Rev. 1.00 Sep. 19, 2008 Page 202 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.6.3 Data Bus The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access space or 16-bit access space by the ABW7 and ABW6 bits in ABWCRA. For the 8-bit access space, D15 to D8 are valid for both address and data. For the 16-bit access space, D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is accessed, the corresponding address will be output to the address bus. For details on access size and data alignment, see section 6.5.1, Data Size and Data Alignment. 6.6.4 Address Hold Signal In the address/data multiplexed I/O space, a hold signal (AH) that indicates the timing for latching the address is output. The AH output pin is multiplexed with the AS output pin. When the external address space is specified as the address/data multiplexed I/O space, the multiplexed pin functions as the AH output pin. Note however that the multiplexed pin will function as the AS output pin until the address/data multiplexed I/O space is specified. 6.6.5 Basic Timing The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data cycle. The data cycle is based on the basic bus interface timing specified by ABWCR, ASTCR, WTCRAH, RDNCR, and CSACR. Rev. 1.00 Sep. 19, 2008 Page 203 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (1) 8-Bit, 2-State Data Access Space Figure 6.21 shows the bus timing for an 8-bit, 2-state data access space. When an 8-bit access space is accessed, the upper halves (D15 to D8) of both the address bus and data bus are used. Wait states cannot be inserted in the data cycle. Address cycle Tma1 Address bus CSn AH RD Read D15 to D8 HWR Write LWR Address Tma2 T1 Data cycle T2 Read data D15 to D8 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.21 Bus Timing for 8-Bit, 2-State Data Access Space Rev. 1.00 Sep. 19, 2008 Page 204 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) 8-Bit, 3-State Data Access Space Figure 6.22 shows the bus timing for an 8-bit, 3-state data access space. When an 8-bit access space is accessed, the upper halves (D15 to D8) of both the address bus and data bus are used. Wait states can be inserted in the data cycle. Address cycle Tma1 Tma2 T1 Data cycle T2 T3 Address bus CSn AH RD Read D15 to D8 HWR LWR Address Read data Write D15 to D8 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.22 Bus Timing for 8-Bit, 3-State Data Access Space Rev. 1.00 Sep. 19, 2008 Page 205 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (3) 16-Bit, 2-State Data Access Space Figures 6.23 to 6.25 show bus timings for a 16-bit, 2-state data access space. When a 16-bit access space is accessed, the entire address bus (D15 to D0) is used for all addresses, and the upper half (D15 to D8) of the data bus is used for even addresses and the lower half (D7 to D0) of the data bus is used for odd addresses. Wait states cannot be inserted in the data cycle. Address cycle Tma1 Tma2 T1 Data cycle T2 Address bus CSn AH RD Read data Read D15 to D8 Address D7 to D0 HWR LWR Write D15 to D8 Address Address Write data D7 to D0 Address Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.23 Bus Timing for 16-Bit, 2-State Data Access Space (Even Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 206 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 T1 Data cycle T2 Address bus CSn AH RD Read D15 to D8 Address D7 to D0 HWR LWR Write Address Read data D15 to D8 Address D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.24 Bus Timing for 16-Bit, 2-State Data Access Space (Odd Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 207 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 T1 Data cycle T2 Address bus CSn AH RD Read data Read data Read D15 to D8 Address D7 to D0 HWR LWR Write Address D15 to D8 Address Write data D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.25 Bus Timing for 16-Bit, 2-State Data Access Space (Word Access) Rev. 1.00 Sep. 19, 2008 Page 208 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (4) 16-Bit, 3-State Data Access Space Figures 6.26 to 6.28 show bus timings for a 16-bit, 3-state data access space. When a 16-bit access space is accessed, the entire address bus (D15 to D0) is used for all addresses, and the upper half (D15 to D8) of the data bus is used for even addresses and the lower half (D7 to D0) of the data bus is used for odd addresses. Wait states can be inserted in the data cycle. Address cycle Tma1 Tma2 T1 Data cycle T2 T3 Address bus CSn AH RD Read data Read D15 to D8 Address D7 to D0 HWR LWR Write D15 to D8 Address Address Write data D7 to D0 Address Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.26 Bus Timing for 16-Bit, 3-State Data Access Space (Even Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 209 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 T1 Data cycle T2 T3 Address bus CSn AH RD Read D15 to D8 Address D7 to D0 HWR LWR Write D15 to D8 Address Read data Address D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.27 Bus Timing for 16-Bit, 3-State Data Access Space (Odd Address Byte Access) Rev. 1.00 Sep. 19, 2008 Page 210 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 T1 Data cycle T2 T3 Address bus CSn AH RD Read data Read data Read D15 to D8 Address D7 to D0 HWR LWR Write D15 to D8 Address Address Write data D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.28 Bus Timing for 16-Bit, 3-State Data Access Space (Word Access) Rev. 1.00 Sep. 19, 2008 Page 211 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.6.6 (1) Wait Control Address Cycle A single address wait cycle Tmaw can be inserted between Tma1 and Tma2 cycles by setting the ADDEX bit in MPXCR to 1. Figure 6.29 shows the access timing when the address cycle is three cycles. Address cycle Tma1 Address bus CSn AH RD D15 to D8 Address Read data Tmaw Tma2 T1 Data cycle T2 Read D7 to D0 HWR LWR Write D15 to D8 Address Address Write data D7 to D0 Address Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.29 Example of Access Timing with Address Wait Rev. 1.00 Sep. 19, 2008 Page 212 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) Data Cycle In the data cycle, program wait insertion and pin wait insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details, refer to section 6.5.4, Wait Control. Wait control settings do not affect the address cycles. 6.6.7 Read Strobe (RD) Timing In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified in the same way as in the basic bus interface. For details, refer to section 6.5.5, Read Strobe (RD) Timing. Figure 6.30 shows an example when the read strobe timing is modified. Address cycle Tma1 Tma2 T1 Data cycle T2 Address bus CSn AH RD RDNn = 0 D15 to D8 RD RDNn = 1 D15 to D8 Address Read data Address Read data Note: n = 6, 7 Figure 6.30 Example of Read Strobe Timing Rev. 1.00 Sep. 19, 2008 Page 213 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.6.8 Extension of Chip Select (CS) Assertion Period in Data Cycle In the address/data multiplexed I/O interface, extension cycles can be inserted before and after the data cycle. For details, see section 6.5.6, Extension of Chip Select (CS) Assertion Period. Figure 6.31 shows an example of the timing when the chip select assertion period is extended in the data cycle. Address cycle Tma1 Tma2 Th T1 Data cycle T2 Tt Address bus CSn AH RD Read data Read data Read D15 to D8 Address D7 to D0 HWR LWR Write Address D15 to D8 Address Write data D7 to D0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.31 Example of Timing when Chip Select Assertion Period Is Extended in Data Cycle Rev. 1.00 Sep. 19, 2008 Page 214 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) When consecutively reading from the same area connected to a peripheral LSI whose output floating time is long, data outputs from the peripheral LSI may conflict with address outputs from this LSI. The data conflict can be avoided by inserting the CS assertion period extension cycle after the access cycle. Figure 6.32 shows an example of the operation. In the figure, both bus cycles A and B are read access cycles to the same area which is address/data multiplexed I/O space. (a) shows an example of conflict occurring between data outputs from the peripheral LSI whose output floating time is long and address outputs from this LSI because the CS assertion period extension cycle is not inserted. (b) shows an example of the data conflict being avoided by inserting the CS assertion period extension cycle. Bus cycle A Address bus CS WR RD Bus cycle B Address bus CS WR RD Data bus Data conflict Bus cycle A Bus cycle B Data bus Output floating time is long (a) Without CS assertion period extension cycle (CSXTn = 0) (b) With CS assertion period extension cycle (CSXTn = 1) Figure 6.32 Consecutive Read Accesses to Same Area (Address/Data Multiplexed I/O Space) Rev. 1.00 Sep. 19, 2008 Page 215 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7 DRAM Interface In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode. 6.7.1 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2 to 5), and continuous area (areas 2 to 5). Table 6.5 RMTS2 0 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space RMTS1 0 1 RMTS0 1 0 1 Area 5 Normal space Normal space DRAM space Area 4 Normal space Normal space DRAM space Area 3 Normal space DRAM space DRAM space Area 2 DRAM space DRAM space DRAM space 1 0 0 1 Continuous synchronous DRAM space* Mode register settings of synchronous DRAM* Reserved (setting prohibited) Continuous DRAM space Continuous DRAM space Continuous DRAM space Continuous DRAM space 1 0 1 Note: * Reserved (setting prohibited) in the H8S/2426 Group and H8S/2424 Group. With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait states, etc.) for continuous DRAM space conform to the settings for area 2. 6.7.2 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table 6.6 shows the relation between the settings of MXC2 to MXC0 and the shift size. The MXC2 bit should be cleared to 0 when the DRAM interface is used. Rev. 1.00 Sep. 19, 2008 Page 216 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Table 6.6 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR A23 Shift to A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A9 A0 A8 Address Pins MXC2 Row address 0 MXC1 0 MXC0 0 Size 8 bits A23 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 to A16 1 9 bits A23 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 to A16 A9 1 0 10 bits A23 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 to A16 1 11 bits A23 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 to A16 1 Column address 0 x x x x Reserved (setting prohibited) A23 A15 A14 A13 A12 A11 A10 to A16 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 x x Reserved (setting prohibited) Legend: x: Don't care. 6.7.3 Data Bus If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, x16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data Size and Data Alignment. Rev. 1.00 Sep. 19, 2008 Page 217 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.4 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Since the CS2 to CS5 pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2 to RAS5 signals are output. Table 6.7 Pin HWR CS2 DRAM Interface Pins With DRAM Setting WE RAS2/RAS Name Write enable Row address strobe 2/ row address strobe I/O Output Output Function Write enable for DRAM space access Row address strobe when area 2 is designated as DRAM space or row address strobe when areas 2 to 5 are designated as continuous DRAM space Row address strobe when area 3 is designated as DRAM space Row address strobe when area 4 is designated as DRAM space Row address strobe when area 5 is designated as DRAM space Upper column address strobe for 16-bit DRAM space access or column address strobe for 8-bit DRAM space access Lower column address strobe signal for 16-bit DRAM space access Output enable signal for DRAM space access Wait request signal Row address/column address multiplexed output Data input/output pins CS3 CS4 CS5 UCAS RAS3 RAS4 RAS5 UCAS Row address strobe 3 Row address strobe 4 Row address strobe 5 Upper column address strobe Output Output Output Output LCAS LCAS Lower column address strobe Output enable Wait Address pins Data pins Output RD, OE WAIT A15 to A0 D15 to D0 OE WAIT A15 to A0 D15 to D0 Output Input Output I/O Rev. 1.00 Sep. 19, 2008 Page 218 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.5 Basic Timing Figure 6.33 shows the basic access timing for DRAM space. The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. Tp Address bus Row address Column address Tr Tc1 Tc2 RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.33 DRAM Basic Access Timing (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 219 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When connecting DRAM provided with an EDO page mode, the OE signal should be connected to the (OE) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space, the signal is output only from the RD pin. Rev. 1.00 Sep. 19, 2008 Page 220 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.6 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width, etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.34 shows an example of the timing when a 3-state column address output cycle is selected. Tp Address bus Row address Column address Tr Tc1 Tc2 Tc3 RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.34 Example of Access Timing with 3-State Column Address Output Cycle (RAST = 0) Rev. 1.00 Sep. 19, 2008 Page 221 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal. Use the optimum setting according to the DRAM connected and the operating frequency of this LSI. Figure 6.35 shows an example of the timing when the RAS signal goes low from the beginning of the Tr state. Tp Address bus Row address Column address Tr Tc1 Tc2 RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.35 Example of Access Timing when RAS Signal Goes Low from Beginning of Tr State (CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 222 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which the column address is output. Use the setting that gives the optimum row address signal hold time relative to the falling edge of the RAS signal according to the DRAM connected and the operating frequency of this LSI. Figure 6.36 shows an example of the timing when one Trw state is set. Tp Address bus Row address Column address Tr Trw Tc1 Tc2 RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.36 Example of Timing with One Row Address Output Maintenance State (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 223 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.8 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is always inserted when DRAM space is accessed. From one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI. Figure 6.37 shows the timing when two Tp states are inserted. The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Address bus Row address Column address Tp2 Tr Tc1 Tc2 RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.37 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 224 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.9 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access. (1) Program Wait Insertion When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 7 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings in WTCR. (2) Pin Wait Insertion When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait input by means of the WAIT pin is enabled. When DRAM space is accessed in this state, a program wait (Tw) is first inserted. If the WAIT pin is low at the falling edge of in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figures 6.38 and 6.39 show examples of wait cycle insertion timing in the case of 2-state and 3state column address output cycles. Rev. 1.00 Sep. 19, 2008 Page 225 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw Tc2 WAIT Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus UCAS, LCAS WE (HWR) OE (RD) Data bus Row address Column address Read High Write High Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.38 Example of Wait State Insertion Timing (2-State Column Address Output) Rev. 1.00 Sep. 19, 2008 Page 226 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw Tc2 Tc3 WAIT Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus UCAS, LCAS WE (HWR) OE (RD) Data bus Row address Column address Read High Write High Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.39 Example of Wait State Insertion Timing (3-State Column Address Output) Rev. 1.00 Sep. 19, 2008 Page 227 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.10 Byte Access Control When DRAM with a x16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.40 shows the control timing for 2-CAS access, and figure 6.41 shows an example of 2-CAS DRAM connection. Tp Address bus Row address Column address Tr Tc1 Tc2 RASn (CSn) UCAS LCAS WE (HWR) OE (RD) Upper data bus High High Write data High-Z Lower data bus Note: n = 2 to 5 Figure 6.40 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 228 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) This LSI (Address shift size set to 10 bits) RASn (CSn) UCAS LCAS HWR (WE) RD (OE) A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 2-CAS type 16-Mbit DRAM 1-Mbyte x 16-bit configuration 10-bit column address RAS UCAS LCAS WE OE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Row address input: A9 to A0 Column address input: A9 to A0 Figure 6.41 Example of 2-CAS DRAM Connection 6.7.11 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR. (1) Burst Access (Fast Page Mode) Figures 6.42 and 6.43 show the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR. Rev. 1.00 Sep. 19, 2008 Page 229 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Address bus RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus WE (HWR) Write OE (RD) Data bus Tr Tc1 Tc2 Tc1 Tc2 Row address Column address 1 Column address 2 High High Note: n = 2 to 5 Figure 6.42 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 230 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Address bus RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus WE (HWR) Write OE (RD) Data bus Note: n = 2 to 5 Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 Row address Column address 1 Column address 2 High High Figure 6.43 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details see section 6.7.9, Wait Control. (2) RAS Down Mode and RAS Up Mode Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again. * RAS Down Mode To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed when the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6.44 shows an example of the timing in RAS down mode. Rev. 1.00 Sep. 19, 2008 Page 231 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Note, however, that the RAS signal will go high if: a refresh operation is initiated in the RAS down state self-refreshing is performed the chip enters software standby mode the external bus is released the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction. Normal space read Tc2 T1 T2 DRAM space read Tc1 Tc2 DRAM space read Tp Tr Tc1 Address bus Row address Column address 1 External address Column address 2 RASn (CSn) UCAS, LCAS RD OE Data bus Note: n = 2 to 5 Figure 6.44 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 232 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) * RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.45 shows an example of the timing in RAS up mode. DRAM space read Tc2 Tc1 Tc2 Normal space read T1 T2 DRAM space read Tp Tr Tc1 Address bus Row address Column address 1 Column address 2 External address RASn (CSn) UCAS, LCAS RD OE Data bus Note: n = 2 to 5 Figure 6.45 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 233 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.7.12 Refresh Control This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. (1) CAS-before-RAS (CBR) Refreshing To select CBR refreshing, set the RFSHE bit to 1 in REFCR. With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0. Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the DRAM used. When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is shown in figure 6.46, compare match timing in figure 6.47, and CBR refresh timing in figure 6.48. When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is performed in parallel during the CBR refresh period. RTCNT RTCOR H'00 Refresh request Figure 6.46 RTCNT Operation Rev. 1.00 Sep. 19, 2008 Page 234 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.47 Compare Match Timing TRp TRr TRc1 TRc2 CSn (RASn) UCAS, LCAS Figure 6.48 CBR Refresh Timing Rev. 1.00 Sep. 19, 2008 Page 235 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations. Figure 6.49 shows the timing when bits RCW1 and RCW0 are set. TRp TRrw TRr TRc1 TRc2 CSn (RASn) UCAS, CAS Figure 6.49 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) Rev. 1.00 Sep. 19, 2008 Page 236 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Depending on the DRAM used, modification of the WE signal may not be permitted during the refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.50 shows an example of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and retains its value prior to the start of the refresh period. Normal space access request A23 to A0 CS AS RD HWR (WE) Refresh period RAS CAS Figure 6.50 Example of CBR Refresh Timing (CBRM = 1) Rev. 1.00 Sep. 19, 2008 Page 237 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6.51. When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is exited automatically. If a CBR refresh request occurs when making a transition to software standby mode, CBR refreshing is executed, and then self-refresh mode is entered. When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register. Software standby TRp TRr TRc3 CSn (RASn) UCAS, LCAS HWR (WE) Note: n = 2 to 5 High Figure 6.51 Self-Refresh Timing Rev. 1.00 Sep. 19, 2008 Page 238 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time. In this case, too, normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum post-self-refresh precharge time, including this time. Figure 6.52 shows an example of the timing when the precharge time immediately after self-refreshing is extended by 2 states. Software standby DRAM space write TRc3 TRp1 TRp2 Tp Tr Tc1 Tc2 Address bus RASn (CSn) UCAS, LCAS OE (RD) WR (HWR) Data bus Note: n = 2 to 5 Figure 6.52 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States Rev. 1.00 Sep. 19, 2008 Page 239 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (3) Refreshing and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in MSTPCRH. 6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC or EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed. (1) When DDS = 1 or EDDS = 1 Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low from the Tc1 state. Figure 6.53 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or EDDS = 1. Rev. 1.00 Sep. 19, 2008 Page 240 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) High Data bus WE (HWR) Write OE (RD) Data bus High DACK or EDACK Note: n = 2 to 5 Figure 6.53 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 (RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 241 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) When DDS = 0 or EDDS = 0 When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.54 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or EDDS = 0. Tp Address bus Row address Column address Tr Tc1 Tc2 Tc3 RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High DACK or EDACK Note: n = 2 to 5 Figure 6.54 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 (RAST = 0, CAST = 1) Rev. 1.00 Sep. 19, 2008 Page 242 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8 Synchronous DRAM Interface In the H8S/2426R Group, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Synchronous DRAM of CAS latency 1 to 4 can be connected. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. 6.8.1 Setting Continuous Synchronous DRAM Space Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and synchronous DRAM space is shown in table 6.8. Possible synchronous DRAM interface settings are and continuous area (areas 2 to 5). Table 6.8 RMTS2 0 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM Space RMTS1 0 1 RMTS0 1 0 1 Area 5 Normal space Normal space DRAM space Area 4 Normal space Normal space DRAM space Area 3 Normal space DRAM space DRAM space Area 2 DRAM space DRAM space DRAM space 1 0 0 1 Continuous synchronous DRAM space Mode settings of synchronous DRAM Reserved (setting prohibited) Continuous DRAM space 1 0 1 With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE signal. The (OE) pin of the synchronous DRAM is used as the CKE signal, and the CS5 pin is used as synchronous DRAM clock (SDRAM). The bus specifications for continuous synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for the continuous synchronous DRAM are invalid. Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and address-precharge-setting command (Precharge-sel) output on the upper column addresses. Rev. 1.00 Sep. 19, 2008 Page 243 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT), and mode-register write (MRS). Commands for bank control cannot be used. 6.8.2 Address Multiplexing With continuous synchronous DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. The address-precharge-setting command (Precharge-sel) can be output on the upper column address. Table 6.9 shows the relation between the settings of MXC2 to MXC0 and the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used. Table 6.9 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR MXC2 Row address 0 1 MXC1 x 0 MXC0 x 0 8 bits 9 bits 10 bits 11 bits A23 to A16 A23 to A16 A23 to A16 A23 to A16 Shift Size A23 to A16 A15 A14 A13 A12 A11 A10 Address Pins A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Reserved (setting prohibited) A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 1 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 1 0 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 1 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Column address 0 1 x 0 x 0 A23 to A16 A23 to A16 A23 to A16 A23 to A16 P P P P Reserved (setting prohibited) P P P A8 A7 A6 A5 A4 A3 A2 A1 A0 1 P P P P P P A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 P P P P P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 P P P P A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Legend: x: Don't care. P: Precharge-sel Rev. 1.00 Sep. 19, 2008 Page 244 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.3 Data Bus If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, areas 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, x16-bit configuration synchronous DRAM can be connected directly. In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data Size and Data Alignment. 6.8.4 Pins Used for Synchronous DRAM Interface Table 6.10 shows pins used for the synchronous DRAM interface and their functions. Since the CS2 to CS4 pins are in the input state after a reset, set DDR to 1 when RAS, CAS, and WE signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR register to 1 when the CKE signal is output. Rev. 1.00 Sep. 19, 2008 Page 245 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Table 6.10 Synchronous DRAM Interface Pins With Synchronous DRAM Setting RAS Pin CS2 Name Row address strobe I/O Output Function Row address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space Column address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space Write enable strobe when areas 2 to 5 are designated as continuous synchronous DRAM space Clock only for synchronous DRAM Clock enable signal when areas 2 to 5 are designated as continuous synchronous DRAM space Upper data mask enable for 16-bit continuous synchronous DRAM space access/data mask enable for 8-bit continuous synchronous DRAM space access Lower data mask enable signal for 16-bit continuous synchronous DRAM space access Row address/column address multiplexed output pins Data input/output pins CS3 CAS Column address strobe Output CS4 WE Write enable Output CS5 (OE) SDRAM (CKE) Clock Clock enable Output Output UCAS DQMU Upper data mask enable Output LCAS DQML Lower data mask enable Output A15 to A0 D15 to D0 A15 to A0 D15 to D0 Address pins Data pins Output I/O Rev. 1.00 Sep. 19, 2008 Page 246 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.5 Synchronous DRAM Clock The synchronous clock (SDRAM) is output from the CS5 pin. SDRAM is shifted by 90 phase from . Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks. Figure 6.55 shows the relationship between and SDRAM. Tcyc 1/4 Tcyc (90) SDRAM Figure 6.55 Relationship between and SDRAM 6.8.6 Basic Timing The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored. Figure 6.56 shows the basic timing for synchronous DRAM. Rev. 1.00 Sep. 19, 2008 Page 247 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE Read CKE DQMU, DQML High Data bus PALL ACTV READ NOP RAS CAS WE Write CKE DQMU, DQML High Data bus PALL ACTV NOP WRIT Figure 6.56 Basic Access Timing of Synchronous DRAM (CAS Latency 1) Rev. 1.00 Sep. 19, 2008 Page 248 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.7 CAS Latency Control CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.11, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the AST2 bit of ASTCR. Figure 6.57 shows the CAS latency control timing when synchronous DRAM of CAS latency 3 is connected. The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of synchronous DRAM to be connected. Table 6.11 Setting CAS Latency W22 0 W21 0 W20 0 1 1 0 1 1 0 0 1 1 0 1 Description Connect synchronous DRAM of CAS latency 1 Connect synchronous DRAM of CAS latency 2 Connect synchronous DRAM of CAS latency 3 Connect synchronous DRAM of CAS latency 4 Reserved (must not be used) Reserved (must not be used) Reserved (must not be used) Reserved (must not be used) CAS Latency Control Cycle Inserted 0 state 1 state 2 states 3 states Rev. 1.00 Sep. 19, 2008 Page 249 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl1 Tcl2 Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE Read CKE DQMU, DQML High Data bus PALL ACTV READ NOP RAS CAS WE Write CKE DQMU, DQML High Data bus PALL ACTV NOP WRIT NOP Figure 6.57 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) Rev. 1.00 Sep. 19, 2008 Page 250 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.8 Row Address Output State Control When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR. Use the optimum setting for the wait time according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.58 shows an example of the timing when the one Trw state is set. Tp Tr Trw Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU, DQML High Read Data bus PALL ACTV NOP READ NOP RAS CAS WE CKE DQMU, DQML High Write Data bus PALL ACTV NOP WRIT NOP Figure 6.58 Example of Access Timing when Row Address Output Hold State Is 1 State (RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 251 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.9 Precharge State Count When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.59 shows the timing when two Tp states are inserted. Rev. 1.00 Sep. 19, 2008 Page 252 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Tp2 Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU, DQML High Read Data bus PALL NOP ACTV READ NOP RAS CAS WE CKE DQMU, DQML High Write Data bus PALL NOP ACTV NOP WRIT NOP Figure 6.59 Example of Timing with Two-State Precharge Cycle (TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 253 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.10 Bus Cycle Control in Write Cycle By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access. Figure 6.60 shows the write access timing when the CAS latency control cycle is disabled. Tp Tr Tc1 Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU, DQML High Data bus PALL ACTV NOP WRIT Figure 6.60 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled (SDWCD = 1) Rev. 1.00 Sep. 19, 2008 Page 254 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.11 Byte Access Control When synchronous DRAM with a x16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.61 and 6.62 show the control timing for DQM, and figure 6.63 shows an example of connection of byte control by DQMU and DQML. Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU High DQML Upper data bus Lower data bus High High impedance PALL ACTV NOP WRIT NOP Figure 6.61 DQMU and DQML Control Timing (Upper Byte Write Access: SDWCD = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 255 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU High High DQML Upper data bus Lower data bus High impedance PALL ACTV READ NOP Figure 6.62 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 256 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) This LSI (Address shift size set to 8 bits) 16-Mbit synchronous DRAM 1 Mword x 16 bits x 4-bank configuration 8-bit column address CS2 (RAS) CS3 (CAS) CS4 (WE) UCAS (DQMU) LCAS (DQML) CS5 (SDRAM) A23 A21 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 RAS CAS WE DQMU DQML CLK A13 (BS1) A12 (BS0) A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ15 to DQ0 Row address input: A11 to A0 Column address input: A7 to A0 Bank select address: A13/A12 DCTL OE (CKE) CKE I/O PORT CS Notes: 1. Bank control is not available. 2. The CKE and CS pins must be fixed to 1 when the power supply is input. 3. The CS pin must be fixed to 0 before accessing synchronous DRAM. Figure 6.63 Example of DQMU and DQML Byte Control Rev. 1.00 Sep. 19, 2008 Page 257 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.12 Burst Operation With synchronous DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, burst access is also provided which can be used when making consecutive accesses to the same row address. This access enables fast access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR. DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal cannot be specified to the Tc2 cycle data output if the Tc1 cycle is executed for second or following column address when the CAS latency is set to 1 to issue the READ command. Do not set the BE bit to 1 when synchronous DRAM of CAS latency 1 is connected. (1) Burst Access Operation Timing Figure 6.64 shows the operation timing for burst access. When there are consecutive access cycles for continuous synchronous DRAM space, the column address output cycles continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR. Rev. 1.00 Sep. 19, 2008 Page 258 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 Tc1 Tcl Tc2 SDRAM Address bus Column address 1 Row address Column address Column address 2 Precharge-sel Row address RAS CAS WE CKE DQMU, DQML High Read Data bus PALL ACTV READ NOP READ NOP RAS CAS WE CKE DQMU, DQML High Write Data bus PALL ACTV NOP WRIT NOP WRIT NOP Figure 6.64 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 259 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) RAS Down Mode Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space. In this case, if the row address active state is held during the access to the other space, the read or write command can be issued without ACTV command generation similarly to DRAM RAS down mode. To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings. The operation corresponding to DRAM RAS up mode is not supported by this LSI. Figure 6.65 shows an example of the timing in RAS down mode. Note, however, the next continuous synchronous DRAM space access is a full access if: * * * * * * a refresh operation is initiated in the RAS down state self-refreshing is performed the chip enters software standby mode the external bus is released the BE bit is cleared to 0 the mode register of the synchronous DRAM is set There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not guaranteed that other row address are accessed in a period in which program execution ensures the value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of the maximum active state time of each bank must be satisfied. When refresh is not used, programs must be developed so that the bank is not in the active state for more than the specified time. Rev. 1.00 Sep. 19, 2008 Page 260 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Tc2 T1 T2 Tc1 Tcl Tc2 Address bus Column Row address address Row address Column address External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP Figure 6.65 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2) 6.8.13 Refresh Control This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as continuous synchronous DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. Rev. 1.00 Sep. 19, 2008 Page 261 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (1) Auto Refreshing To select auto refreshing, set the RFSHE bit to 1 in REFCR. With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0. Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the synchronous DRAM used. When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown in figure 6.66. Since the refresh counter operation is the same as the operation in the DRAM interface, see section 6.7.12, Refresh Control. When the continuous synchronous DRAM space is set, access to external address space other than continuous synchronous DRAM space cannot be performed in parallel during the auto refresh period, since the setting of the CBRM bit of REFCR is ignored. Rev. 1.00 Sep. 19, 2008 Page 262 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) TRp TRr TRc1 TRc2 SDRAM Address bus Precharge-sel RAS CAS WE CKE PALL REF High NOP Figure 6.66 Auto Refresh Timing When the interval specification from the PALL command to the REF command cannot be satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.67 shows the timing when one wait state is inserted. Since the setting of bits TPC1 and TPC0 of DRACCR is also valid in refresh cycles, the command interval can be extended by the RCW1 and RCW0 bits after the precharge cycles. Rev. 1.00 Sep. 19, 2008 Page 263 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) TRp1 TRp2 TRrw TRr TRc1 TRc2 SDRAM Address bus Precharge-sel RAS CAS WE CKE High PALL NOP REF NOP Figure 6.67 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) When the interval specification from the REF command to the ACTV cannot be satisfied, setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.68 shows the timing when one wait state is inserted. Rev. 1.00 Sep. 19, 2008 Page 264 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) TRp TRr TRr1 TRcw TRc2 SDRAM Address bus Precharge-sel RAS CAS WE CKE High PALL REF NOP Figure 6.68 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the synchronous DRAM. To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the SELF command is issued, as shown in figure 6.69. When software standby mode is exited, the SLFRF bit in REFCR is cleared to 0 and self-refresh mode is exited automatically. If an auto refresh request occurs when making a transition to software standby mode, auto refreshing is executed, and then self-refresh mode is entered. When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR. Rev. 1.00 Sep. 19, 2008 Page 265 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) TRp TRr Software standby TRc2 SDRAM Address bus Precharge-sel RAS CAS WE CKE PALL SELF NOP Figure 6.69 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time after self-refreshing from 1 to 7 states longer than the normal precharge time. In this case, too, normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum post-self-refresh precharge time, including this time. Figure 6.70 shows an example of the timing when the precharge time after self-refreshing is extended by 2 states. Rev. 1.00 Sep. 19, 2008 Page 266 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space write Software standby TRc2 TRp1 TRp2 Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU, DQML Data bus NOP PALL ACTV NOP NOP NOP Figure 6.70 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2) (3) Refreshing and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If synchronous DRAM is connected to the external address space and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in MSTPCR. (4) Software Standby When a transition is made to normal software standby, the PALL command is not output. If synchronous DRAM is connected and DRAM data is to be retained in software standby, selfrefreshing must be set. Rev. 1.00 Sep. 19, 2008 Page 267 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.14 Mode Register Setting of Synchronous DRAM To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After that, access the continuous synchronous DRAM space in bytes. When the value to be set in the synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of address H'400000 + 2X for 16-bit bus configuration synchronous DRAM. The value of the address signal is fetched at the issuance time of the MRS command as the setting value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the synchronous DRAM is not supported by this LSI. For setting the mode register of the synchronous DRAM, set the burst read/single write with the burst length of 1. Figure 6.71 shows the setting timing of the mode in the synchronous DRAM. Tp Tr Tc1 Tc2 SDRAM Address bus Mode setting value Precharge-sel Mode setting value RAS CAS WE CKE PALL NOP High MRS NOP Figure 6.71 Synchronous DRAM Mode Setting Timing Rev. 1.00 Sep. 19, 2008 Page 268 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.8.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed. The establishment time for the read data can be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits. (1) Output Timing of DACK or EDACK When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tc1 state. Figure 6.72 shows the DACK or EDACK output timing for the synchronous DRAM interface when DDS = 1 or EDDS = 1. Rev. 1.00 Sep. 19, 2008 Page 269 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE Read CKE DQMU, DQML High Data bus PALL ACTV READ NOP RAS CAS WE Write CKE DQMU, DQML High Data bus PALL DACK or EDACK ACTV NOP WRIT NOP Figure 6.72 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 Rev. 1.00 Sep. 19, 2008 Page 270 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing continuous synchronous DRAM space. Figure 6.73 shows the DACK or EDACK output timing for connecting the synchronous DRAM interface when DDS = 0 or EDDS = 0. Rev. 1.00 Sep. 19, 2008 Page 271 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE Read CKE DQMU, DQML High Data bus PALL ACTV READ NOP RAS CAS WE Write CKE DQMU, DQML High Data bus PALL DACK or RDACK ACTV NOP WRIT NOP Figure 6.73 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 Rev. 1.00 Sep. 19, 2008 Page 272 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) Read Data Extension If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is readaccessed in DMAC/EXDMAC single address mode, the establishment time for the read data can be extended by clock suspend mode. The number of states for insertion of the read data extension cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in DRAMCR when the read data will be extended. The extension of the read data is not in accordance with the bits DDS and EDDS. Figure 6.74 shows the timing chart when the read data is extended by two cycles. Tp Tr Tc1 Tcl Tc2 Tsp1 Tsp2 SDRAM Address bus Row Column address address Row address Column address Precharge-sel RAS CAS WE CKE DQMU, DQML Data bus DACK or EDACK PALL ACTV READ NOP Figure 6.74 Example of Timing when the Read Data Is Extended by Two States (DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 273 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.9 Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for burst access. Settings can be made independently for area 0 and area 1. In burst ROM space, burst access covers only CPU read accesses. 6.9.1 Basic Timing The number of access states in the initial cycle (full access) on the burst ROM interface is determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and CSACRH. When area 0 or area 1 is designated as burst ROM space, the settings in RDNCR and CSACRL are ignored. From 1 to 8 states can be selected for the burst cycle, according to the settings of bits BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, and BSTS10 in BROMCR. The basic access timing for burst ROM space is shown in figures 6.75 and 6.76. Rev. 1.00 Sep. 19, 2008 Page 274 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Full access T1 T2 T3 T1 Burst access T2 T1 T2 Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.75 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Rev. 1.00 Sep. 19, 2008 Page 275 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.76 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.9.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle. 6.9.3 Write Access When a write access to burst ROM space is executed, burst access is interrupted at that point and the write access is executed in line with the basic bus interface settings. Write accesses are not performed in burst mode even though burst ROM space is designated. Rev. 1.00 Sep. 19, 2008 Page 276 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.10 6.10.1 Idle Cycle Operation When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads in Different Areas If consecutive reads in different areas occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle. Figure 6.77 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS (area A) CS (area B) RD Data bus Address bus CS (area A) CS (area B) RD Data bus Data collision Long output floating time (a) No idle cycle insertion (ICIS1 = 0) Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) Figure 6.77 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) Rev. 1.00 Sep. 19, 2008 Page 277 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (2) Write after Read If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.78 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS (area A) CS (area B) RD HWR Data bus Address bus CS (area A) CS (area B) RD HWR Data bus Data collision Long output floating time (a) No idle cycle insertion (ICIS0 = 0) Idle cycle (b) Idle cycle insertion (ICIS0 = 1, initial value) Figure 6.78 Example of Idle Cycle Operation (Write after Read) Rev. 1.00 Sep. 19, 2008 Page 278 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (3) Read after Write If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR, an idle cycle is inserted at the start of the read cycle. Figure 6.79 shows an example of the operation in this case. In this example, bus cycle A is a CPU write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an external device. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS (area A) CS (area B) RD HWR, LWR Data bus Address bus CS (area A) CS (area B) RD HWR Data bus Data collision Long output floating time (a) No idle cycle insertion (ICIS2 = 0) Idle cycle (b) Idle cycle insertion (ICIS2 = 1, initial value) Figure 6.79 Example of Idle Cycle Operation (Read after Write) Rev. 1.00 Sep. 19, 2008 Page 279 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (4) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.80. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS (area A) CS (area B) RD Address bus CS (area A) CS (area B) RD Overlap period between CS (area B) and RD may occur (a) No idle cycle insertion (ICIS1 = 0) Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) Figure 6.80 Relationship between Chip Select (CS) and Read (RD) Rev. 1.00 Sep. 19, 2008 Page 280 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (5) Idle Cycle in Case of DRAM Space Access after Normal Space Access In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to DRAM space, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.81. External read DRAM space read T1 T2 T3 Tp Tr Tc1 Tc2 Address bus RD Data bus Figure 6.81 Example of DRAM Full Access after External Read (CAST = 0) In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is illustrated in figures 6.82 and 6.83. Rev. 1.00 Sep. 19, 2008 Page 281 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) DRAM space read External read DRAM space read Tp Tr Tc1 Tc2 T1 T2 T3 Ti Tc1 Tc2 Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.82 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) DRAM space read External read DRAM space write Tp Tr Tc1 Tc2 T1 T2 T3 Ti Tc1 Tc2 Address bus RD HWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.83 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 282 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (6) Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space Access In a continuous synchronous DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to continuous synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case is shown in figure 6.84. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. External space read Synchronous DRAM space read T1 Address bus T2 T3 Tp Tr Tc1 Tcl Tc2 Row Column address address Row address Column address Precharge-sel RAS CAS WE CKE DQMU, DQML RD Data bus NOP PALL ACTV READ NOP Figure 6.84 Example of Synchronous DRAM Full Access after External Read (CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 283 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.85 and 6.86. In write access, DQMU and DQML are not in accordance with the settings of the IDLC bit. The timing in this case is illustrated in figure 6.87. Continuous synchronous DRAM space read Continuous synchronous DRAM space read External space read Tp Tr Tc1 Tcl Tc2 T1 T2 T3 Ti Tc1 TCl Tc2 Address bus Row Column address address Row address Column address 1 External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus High PALL ACTV READ NOP READ NOP Idle cycle Figure 6.85 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 284 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Tc2 T1 T2 T3 Ti Ti Tc1 TCl Tc2 Row Column address address Row address Address bus Column address 1 External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus High PALL ACTV READ NOP READ NOP Idle cycle Figure 6.86 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 1, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 285 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space write Tp Tr Tc1 Tcl Tc2 T1 T2 T3 Ti Tc1 TCl Tc2 Row Column address address Row address Address bus Column address 1 External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus High PALL ACTV READ NOP WRIT NOP Idle cycle Figure 6.87 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 286 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (7) (a) Idle Cycle in Case of Normal Space Access after DRAM Space Access Normal space access after DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.88 and 6.89 show examples of idle cycle operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if bits ICIS1 and ICIS0 are set to 1. DRAM space read External address space read DRAM space read Tp Tr Tc1 Tc2 Ti T1 T2 T3 Ti Tc1 Tc2 Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.88 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 287 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) DRAM space read External address space write DRAM space read Tp Tr Tc1 Tc2 Ti T1 T2 T3 Tc1 Tc2 Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.89 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) Rev. 1.00 Sep. 19, 2008 Page 288 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (b) Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR. Figure 6.90 shows an example of idle cycle operation when the ICIS2 bit is set to 1. DRAM space read External space read DRAM space read Tp Tr Tc1 Tc2 Ti T1 T2 T3 Tc1 Tc2 Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.90 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) (8) Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM Space Access: Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 289 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (a) Normal space access after a continuous synchronous DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM space read access can be enabled by setting the DRMI bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and IDLC in RCR. Figure 6.91 shows an example of idle cycle operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous DRAM space read access even if bits ICIS1 and ICIS0 are set to 1. Continuous synchronous DRAM space read Continuous synchronous DRAM space read External space read Tp Tr Tc1 Tcl Tc2 Ti T1 T2 T3 Ti Tc1 TCl Tc2 Address bus Precharge-sel RAS Row Column address address Row address Column address 1 External address External address Column address 2 CAS WE CKE High DQMU, DQML RD Data bus PALL ACTV READ NOP READ NOP Idle cycle Figure 6.91 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 290 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (b) Normal space access after a continuous synchronous DRAM space write access If a normal space read cycle occurs after a continuous synchronous DRAM space write access while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is not in accordance with the DRMI bit in DRACCR. Figure 6.92 shows an example of idle cycle operation when the ICIS2 bit is set to 1. Continuous synchronous DRAM space write Synchronous External address space read DRAM space read Tp Tr Tc1 Tc2 Ti T1 T2 T3 Tc1 TCl Tc2 Address bus Row Column address address Row address Column address External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus PALL ACTV NOP WRIT NOP READ NOP Idle cycle Figure 6.92 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 291 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Table 6.12 shows whether there is an idle cycle insertion or not in the case of mixed accesses to normal space and DRAM space/continuous synchronous DRAM space. Table 6.12 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous Synchronous DRAM Space Previous Access Normal space read Next Access Normal space read (different area) ICIS2 ICIS1 0 1 ICIS0 DRMI 0 1 IDLC 0 1 DRAM*/continuous synchronous DRAM space read Normal space write 0 1 0 1 0 1 0 1 DRAM*/continuous synchronous DRAM space write DRAM/continuous synchronous DRAM* space read Normal space read 0 1 0 1 0 1 0 1 DRAM*/continuous synchronous DRAM space read 0 1 0 1 0 1 Normal space write 0 1 0 1 0 1 DRAM*/continuous synchronous DRAM space write 0 1 0 1 0 1 Idle cycle Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Disabled Disabled 1 state inserted 2 states inserted Disabled Disabled 1 state inserted 2 states inserted Disabled Disabled 1 state inserted 2 states inserted Disabled Disabled 1 state inserted 2 states inserted Rev. 1.00 Sep. 19, 2008 Page 292 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Previous Access Normal space write Next Access Normal space read ICIS2 0 1 ICIS1 ICIS0 DRMI IDLC 0 1 DRAM*/continuous synchronous DRAM space read DRAM/continuous synchronous DRAM* space write Normal space read 0 1 0 1 0 1 0 1 DRAM*/continuous synchronous DRAM space read 0 1 0 1 Idle cycle Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Note: * Not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 293 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of consecutive read and write operations in DRAM/continuous synchronous DRAM space burst access. Figures 6.93 and 6.94 show an example of the timing for idle cycle insertion in the case of consecutive read and write accesses to DRAM/continuous synchronous DRAM space. DRAM space read DRAM space write Tp Tr Tc1 Tc2 Ti Tc1 Tc2 Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus Note: n = 2 to 5 Idle cycle Figure 6.93 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode Rev. 1.00 Sep. 19, 2008 Page 294 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Continuous synchronous DRAM space write Tp Tr Tc1 Tcl Tc2 Ti Tc1 Tc2 Address bus Precharge-sel RAS Column Row address address Row address Column address External address CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP WRIT Idle cycle Figure 6.94 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode (SDWCD = 1, CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 295 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.10.2 Pin States in Idle Cycle Table 6.13 shows the pin states in an idle cycle. Table 6.13 Pin States in Idle Cycle Pins A23 to A0 D15 to D0 CSn (n = 7 to 0) UCAS, LCAS AS/AH RD OE HWR, LWR DACKn (n = 1, 0) EDACKn (n = 3 to 0) Pin State Contents of following bus cycle High impedance High*1 *2 High*2 High High High High High High Notes: 1. Remains low in DRAM space RAS down mode. 2. Remains low in a DRAM space refresh cycle. Rev. 1.00 Sep. 19, 2008 Page 296 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.11 Write Data Buffer Function This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit to 1 in BCR. Figure 6.95 shows an example of the timing when the write data buffer function is used. When this function is used, if an external address space write or DMA single address mode transfer continues for two states or longer, and there is an internal access next, an external write only is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external address space write rather than waiting until it ends. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 Internal address bus Internal memory Internal read signal Internal I/O register address A23 to A0 External address CSn External space write HWR, LWR D15 to D0 Figure 6.95 Example of Timing when Write Data Buffer Function Is Used Rev. 1.00 Sep. 19, 2008 Page 297 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.12 Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters except the EXDMAC* continue to operate as long as there is no external access. If any of the following requests are issued in the external bus released state, the BREQO signal can be driven low to output a bus request externally. * When an internal bus master wants to perform an external access * When a refresh request is generated * When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode Note: * Not supported by the H8S/2424 Group. 6.12.1 Operation In externally expanded mode, the bus can be released to an external device by setting the BRLE bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state. In the external bus released state, internal bus masters except the EXDMAC can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. If a refresh request is generated in the external bus released state, or if a SLEEP instruction is executed to place the chip in software standby mode or all-module-clocksstopped mode, refresh control and software standby or all-module-clocks-stopped control is deferred until the bus request from the external bus master is canceled. If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the following requests are issued, to request cancellation of the bus request externally. * When an internal bus master wants to perform an external access * When a refresh request is generated * When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode Rev. 1.00 Sep. 19, 2008 Page 298 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > External access by internal bus master (Low) If a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh > External bus release (Low) 6.12.2 Pin States in External Bus Released State Table 6.14 shows pin states in the external bus released state. Table 6.14 Pin States in Bus Released State Pins A23 to A0 D15 to D0 CSn (n = 7 to 0) UCAS, LCAS AS/AH RD OE HWR, LWR DACKn (n = 1, 0) EDACKn (n = 3, 2) Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High High Rev. 1.00 Sep. 19, 2008 Page 299 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.12.3 Transition Timing Figure 6.96 shows the timing for transition to the bus released state. External space access cycle External bus released state T1 T2 CPU cycle High impedance Address bus High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO [1] [2] [3] [4] [5] [6] [7] [8] [1] Low level of BREQ signal is sampled at rise of . [2] Bus control signal returns to be high at end of external space access cycle. At least one state from sampling of BREQ signal. [3] BACK signal is driven low, releasing bus to external bus master. [4] BREQ signal state is also sampled in external bus released state. [5] High level of BREQ signal is sampled. [6] BACK signal is driven high, ending external bus release cycle. [7] When there is external access or refresh request of internal bus master during external bus release while BREQOE bit is set to 1, BREQO signal goes low. [8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal. Figure 6.96 Bus Released State Transition Timing Rev. 1.00 Sep. 19, 2008 Page 300 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) Figure 6.97 shows the timing for transition to the bus released state with the synchronous DRAM interface. CPU cycle External space read T1 T2 External bus released state SDRAM High impedance Address bus High impedance Data bus High impedance Precharge-sel Row address High impedance RAS High impedance CAS High impedance WE High impedance CKE High impedance DQMU, DQML BREQ BACK BREQO NOP [1] [2] PALL [3] NOP [4] [5] [8] [6] [7] NOP [9] [1] Low level of BREQ signal is sampled at rise of . [2] PALL command is issued. [3] Bus control signal returns to be high at end of external space access cycle. At least one state from sampling of BREQ signal. [4] BACK signal is driven low, releasing bus to external bus master.. [5] BREQ signal state is also sampled in external bus released state. [6] High level of BREQ signal is sampled. [7] BACK signal is driven high, ending external bus release cycle. [8] When there is external access or refresh request of internal bus master during external bus release while the BREQOE bit is set to 1, BREQO signal goes low. [9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up. Figure 6.97 Bus Release State Transition Timing when Synchronous DRAM Interface Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 301 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.13 Bus Arbitration This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration). There are four bus mastersthe CPU, DTC, DMAC, and EXDMAC*that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. Note: * The EXDMAC is not supported by the H8S/2424 Group. 6.13.1 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus mastership is as follows: (High) EXDMAC* > DMAC > DTC > CPU (Low) An internal bus access by internal bus masters except the EXDMAC* and external bus release, a refresh when the CBRM bit is 0, and an external bus access by the EXDMAC* can be executed in parallel. If an external bus release request, a refresh request, and an external access by an internal bus master occur simultaneously, the order of priority is as follows: (High) Refresh > EXDMAC* > External bus release (Low) (High) External bus release > External access by internal bus master except EXDMAC* (Low) As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to DRAM space by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Note: * The EXDMAC is not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 302 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.13.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can relinquish the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, DMAC, or EXDMAC*, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. * With bit manipulation instructions such as BSET and BCLR, the sequence of operations is: data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is not transferred during this read-modify-write cycle, which is executed as a series of bus cycles. * If the CPU is in sleep mode, the bus is transferred immediately. Note: * The EXDMAC is not supported by the H8S/2424 Group. (2) DTC The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). (3) DMAC The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of the transfer. However, in the event of an EXDMAC or external bus release request, which have a higher priority than the DMAC, the bus may be transferred to the bus master even if block or burst transfer is in progress. Rev. 1.00 Sep. 19, 2008 Page 303 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) (4) EXDMAC The EXDMAC sends the bus arbiter a request for the bus when an activation request is generated. As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in parallel. In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst transfer mode, after completion of the transfer. By setting the BGUP bit to 1 in EDMDR, it is possible to specify temporary release of the bus in the event of an external access request from an internal bus master. For details see section 8, EXDMA Controller (EXDMAC). Note: The EXDMAC is not supported by the H8S/2424 Group. (5) External Bus Release When the BREQ pin goes low and an external bus release request is issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter. External bus release can be performed on completion of an external bus cycle. 6.14 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. Rev. 1.00 Sep. 19, 2008 Page 304 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.15 6.15.1 Usage Notes External Bus Release Function and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus controller and I/O ports. In this state, the external bus release function is halted. To use the external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in allmodule-clocks-stopped mode is executed in the external bus released state, the transition to allmodule-clocks-stopped mode is deferred and performed until after the bus is recovered. 6.15.2 External Bus Release Function and Software Standby In this LSI, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP instruction to place the chip in software standby mode is executed while the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered. Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode, indicating an external bus release request, the request cannot be answered until the chip has recovered from the software standby state. 6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR refresh/auto refresh request is issued. Note: The auto refresh control function is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 305 of 1270 REJ09B0466-0100 Section 6 Bus Controller (BSC) 6.15.4 BREQO Output Timing When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before the BACK signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of BREQ. 6.15.5 (1) Notes on Usage of the Synchronous DRAM Connection Clock Be sure to set the clock to be connected to the synchronous DRAM to SDRAM. (2) WAIT Pin In the continuous synchronous DRAM space, insertion of the wait state by the WAIT pin is disabled regardless of the setting of the WAITE bit in BCR. (3) Bank Control This LSI cannot carry out the bank control of the synchronous DRAM. All banks are selected. (4) Burst Access The burst read/burst write mode of the synchronous DRAM is not supported. When setting the mode register of the synchronous DRAM, set to the burst read/single write and set the burst length to 1. (5) CAS Latency When connecting a synchronous DRAM having CAS latency of 1, set the BE bit to 0 in the DRAMCR. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 306 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC), which can carry out data transfer on up to 4 channels. 7.1 Features * Selectable as short address mode or full address mode Short address mode Maximum of 4 channels can be used Dual address mode or single address mode can be selected In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as 16 bits In single address mode, transfer source or transfer destination address only is specified as 24 bits In single address mode, transfer can be performed in one bus cycle Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode Maximum of 2 channels can be used Transfer source and transfer destination addresses as specified as 24 bits Choice of normal mode or block transfer mode * 16-Mbyte address space can be specified directly * Byte or word can be set as the transfer unit * Activation sources: internal interrupt, external request, auto-request (depending on transfer mode) Six compare match/input capture interrupts of 16-bit timer-pulse unit (TPU0 to 5). Transmission complete interrupt and reception complete interrupt of serial communication interface (SCI_0, SCI_1) External request Auto-request * Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 307 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1. Internal address bus Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI ADI0 External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DMTEND0A DMTEND0B DMTEND1A DMTEND1B Address buffer Processor Channel 1B Channel 1A Channel 0B Channel 0A Control logic Channel 0 MAR_0AH MAR_0AL ETCR_0A Module data bus IOAR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B DMAWER DMATCR Channel 1 DMACR_0A DMACR_0B DMACR_1A DMACR_1B DMABCR Data buffer MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B Internal data bus Legend: DMAWER DMATCR DMABCR DMACR MAR IOAR ETCR : DMA write enable register : DMA terminal control register : DMA band control register (for all channels) : DMA control register : Memory address register : I/O address register : Execute transfer count register Figure 7.1 Block Diagram of DMAC Rev. 1.00 Sep. 19, 2008 Page 308 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.2 Input/Output Pins Table 7.1 shows the pin configuration of the interrupt controller. Table 7.1 Channel 0 Pin Configuration Pin Name DMA request 0 DMA transfer acknowledge 0 DMA transfer end 0 Symbol DREQ0 DACK0 TEND0 DREQ1 DACK1 TEND1 I/O Input Output Output Input Output Output Function Channel 0 external request Channel 0 single address transfer acknowledge Channel 0 transfer end Channel 1 external request Channel 1 single address transfer acknowledge Channel 1 transfer end 1 DMA request 1 DMA transfer acknowledge 1 DMA transfer end 1 Rev. 1.00 Sep. 19, 2008 Page 309 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3 * * * * * * * * * * * * * * * * * * * * * * * * Register Descriptions Memory address register_0AH (MAR_0AH) Memory address register_0AL (MAR_0AL) I/O address register_0A (IOAR_0A) Transfer count register_0A (ECTR_0A) Memory address register_0BH (MAR_0BH) Memory address register_0BL (MAR_0BL) I/O address register_0B (IOAR_0B) Transfer count register_0B (ECTR_0B) Memory address register_1AH (MAR_1AH) Memory address register_1AL (MAR_1AL) I/O address register_1A (IOAR_1A) Transfer count register_1A (ETCR_1A) Memory address register_1BH (MAR_1BH) Memory address register_1BL (MAR_1BL) I/O address register_1B (IOAR_1B) Transfer count register_1B (ETCR_1B) DMA control register_0A (DMACR_0A) DMA control register_0B (DMACR_0B) DMA control register_1A (DMACR_1A) DMA control register_1B (DMACR_1B) DMA band control register H (DMABCRH) DMA band control register L (DMABCRL) DMA write enable register (DMAWER) DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode). The transfer mode can be selected by means of the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and full address mode of channel 0 are shown in table 7.2. Rev. 1.00 Sep. 19, 2008 Page 310 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Table 7.2 FAE0 0 Short Address Mode and Full Address Mode (Channel 0) Description Short address mode specified (channels 0A and 0B operate independently) Channel 0A MAR_0AH MAR_0AL IOAR_0A ETCR_0A DMACR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B DMACR_0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source. Channel 0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source. 1 Full address mode specified (channels 0A and 0B operate in combination as channel 0) MAR_0AH MAR_0BH Channel 0 MAR_0AL MAR_0BL IOAR_0A IOAR_0B ETCR_0A ETCR_0B Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. DMACR_0A DMACR_0B Rev. 1.00 Sep. 19, 2008 Page 311 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.1 Memory Address Registers (MARA and MARB) MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0 (channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B). MAR is not initialized by a reset or in standby mode. Short Address Mode: In short address mode, MARA and MARB operate independently. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. Full Address Mode: In full address mode, MARA functions as the source address register, and MARB as the destination address register. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination address is constantly updated. Rev. 1.00 Sep. 19, 2008 Page 312 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.2 I/O Address Registers (IOARA and IOARB) IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address (transfer source address) or destination address (transfer destination address). The upper 8 bits of the transfer address are automatically set to H'FF. The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0 (channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B). Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is not incremented or decremented each time a data transfer is executed, so the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode. IOAR can be used in short address mode but not in full address mode. 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0 (channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B). ETCR is not initialized by a reset or in standby mode. Rev. 1.00 Sep. 19, 2008 Page 313 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (1) Short Address Mode The function of ETCR in sequential mode and idle mode differs from that in repeat mode. In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit in DMABCRL is cleared, and transfer ends. In repeat mode, ETCRL functions as an 8-bit transfer counter and ETCRH functions as a transfer count holding register. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCRL is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. (2) Full Address Mode The function of ETCR in normal mode differs from that in block transfer mode. In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a data transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used in normal mode. In block transfer mode, ETCRA functions as an 8-bit block size counter (ETCRAL) and ETCRAH functions as a block size holding register. ETCRAL is decremented by 1 each time a 1-byte or 1word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. In block transfer mode, ETCRB functions as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. Rev. 1.00 Sep. 19, 2008 Page 314 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.4 DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together. The bit functions in the DMACR registers differ according to the transfer mode. (1) Short Address Mode: * DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B Bit 7 Bit Name DTSZ Initial Value 0 R/W R/W Description Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer 6 DTID 0 R/W Data Transfer Increment/Decrement Selects incrementing or decrementing of MAR after every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. 0: MAR is incremented after a data transfer (Initial value) * * * * When DTSZ = 0, MAR is incremented by 1 When DTSZ = 1, MAR is incremented by 2 When DTSZ = 0, MAR is decremented by 1 When DTSZ = 1, MAR is decremented by 2 1: MAR is decremented after a data transfer Rev. 1.00 Sep. 19, 2008 Page 315 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 5 Bit Name RPE Initial Value 0 R/W R/W Description Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. * When DTIE = 0 (no transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in repeat mode * When DTIE = 1 (with transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in idle mode 4 DTDIR 0 R/W Data Transfer Direction Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. * When SAE = 0 0: Transfer with MAR as source address and IOAR as destination address 1: Transfer with IOAR as source address and MAR as destination address * When SAE = 1 0: Transfer with MAR as source address and DACK pin as write strobe 1: Transfer with DACK pin as read strobe and MAR as destination address Rev. 1.00 Sep. 19, 2008 Page 316 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 3 2 1 0 Bit Name DTF3 DTF2 DTF1 DTF0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Data Transfer Factor 3 to 0 These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and channel B. * Channel A 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Setting prohibited 0011: Setting prohibited 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited Rev. 1.00 Sep. 19, 2008 Page 317 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 3 2 1 0 Bit Name DTF3 DTF2 DTF1 DTF0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description * Channel B 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled)* 0011: Activated by DREQ pin low-level input* 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Rev. 1.00 Sep. 19, 2008 Page 318 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (2) Full Address Mode * DMACR_0A and DMACR_1A Bit 15 Bit Name DTSZ Initial Value 0 R/W R/W Description Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer 14 13 SAID SAIDE 0 0 R/W R/W Source Address Increment/Decrement Source Address Increment/Decrement Enable These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARA is fixed 01: MARA is incremented after a data transfer * * When DTSZ = 0, MARA is incremented by 1 When DTSZ = 1, MARA is incremented by 2 10: MARA is fixed 11: MARA is decremented after a data transfer * * 12 11 BLKDIR BLKE 0 0 R/W R/W When DTSZ = 0, MARA is decremented by 1 When DTSZ = 1, MARA is decremented by 2 Block Direction Block Enable These bits specify whether normal mode or block transfer mode is to be used for data transfer. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. x0: Transfer in normal mode 01: Transfer in block transfer mode (destination side is block area) 11: Transfer in block transfer mode (source side is block area) Rev. 1.00 Sep. 19, 2008 Page 319 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 10 to 8 Bit Name Initial Value All 0 R/W R/W Description Reserved These bits can be read from or written to. However, the write value should always be 0. Legend: x: Don't care * DMACR_0B and DMACR_1B Bit 7 Bit Name Initial Value 0 R/W R/W Description Reserved This bit can be read from or written to. However, the write value should always be 0. 6 5 DAID DAIDE 0 0 R/W R/W Destination Address Increment/Decrement Destination Address Increment/Decrement Enable These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARB is fixed 01: MARB is incremented after a data transfer * * When DTSZ = 0, MARB is incremented by 1 When DTSZ = 1, MARB is incremented by 2 10: MARB is fixed 11: MARB is decremented after a data transfer * * 4 -- 0 R/W When DTSZ = 0, MARB is decremented by 1 When DTSZ = 1, MARB is decremented by 2 Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 320 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 3 2 1 0 Bit Name DTF3 DTF2 DTF1 DTF0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Data Transfer Factor 3 to 0 These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. * Normal Mode 0000: Setting prohibited 0001: Setting prohibited 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled)* 0011: Setting prohibited 010x: Setting prohibited 0110: Auto-request (cycle steal) 0111: Auto-request (burst) 1xxx: Setting prohibited Rev. 1.00 Sep. 19, 2008 Page 321 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 3 2 1 0 Bit Name DTF3 DTF2 DTF1 DTF0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description * Block Transfer Mode 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 322 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL) DMABCR controls the operation of each DMAC channel. The bit functions in the DMABCR registers differ according to the transfer mode. (1) Short Address Mode: * DMABCRH Bit 15 Bit Name FAE1 Initial Value 0 R/W R/W Description Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B can be used as independent channels. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B can be used as independent channels. 0: Short address mode 1: Full address mode 13 SAE1 0 R/W Single Address Enable 1 Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode 12 SAE0 0 R/W Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode Rev. 1.00 Sep. 19, 2008 Page 323 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 11 10 9 8 Bit Name DTA1B DTA1A DTA0B DTA0A Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Data Transfer Acknowledge 1B Data Transfer Acknowledge 1A Data Transfer Acknowledge 0B Data Transfer Acknowledge 0A These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR. If the DTA bit is set to 1 when DTE = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. If the DTA bit is cleared to 0 when DTE = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. Rev. 1.00 Sep. 19, 2008 Page 324 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) * DMABCRL Bit 7 6 5 4 Bit Name DTE1B DTE1A DTE0B DTE0A Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Data Transfer Enable 1B Data Transfer Enable 1A Data Transfer Enable 0B Data Transfer Enable 0A If the DTE bit is cleared to 0 when DTIE = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. When DTE = 0, data transfer is disabled and the DMAC ignores the activation source selected by the DTF3 to DTF0 bits in DMACR. When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the DTF3 to DTF0 bits in DMACR. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions] * * When initialization is performed When the specified number of transfers have been completed in a transfer mode other than repeat mode When 0 is written to the DTE bit to forcibly suspend the transfer, or for a similar reason * [Setting condition] When 1 is written to the DTE bit after reading DTE =0 Rev. 1.00 Sep. 19, 2008 Page 325 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 3 2 1 0 Bit Name DTIE1B DTIE1A DTIE0B DTIE0A Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Data Transfer End Interrupt Enable 1B Data Transfer End Interrupt Enable 1A Data Transfer End Interrupt Enable 0B Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. (2) Full Address Mode: * DMABCRH Bit 15 Bit Name FAE1 Initial Value 0 R/W R/W Description Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as channel 1. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as channel 0. 0: Short address mode 1: Full address mode Rev. 1.00 Sep. 19, 2008 Page 326 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 13, 12 Bit Name -- Initial Value All 0 R/W R/W Description Reserved These bits can be read from or written to. However, the write value should always be 0. 11 DTA1 0 R/W Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1. It the DTA1 bit is set to 1 when DTE1 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE1 = 1 and DTA1 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. It the DTA1 bit is cleared to 0 when DTE1 = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE1 = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA1 bit setting. The state of the DTME1 bit does not affect the above operations. 10 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 327 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 9 Bit Name DTA0 Initial Value 0 R/W R/W Description Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE0 = 1 and DTA0 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. It the DTA0 bit is cleared to 0 when DTE0 = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE0 = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA0 bit setting. The state of the DTME0 bit does not affect the above operations. 8 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 328 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) * DMABCRL Bit 7 Bit Name DTME1 Initial Value 0 R/W R/W Description Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1. If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME1 bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME1 bit is not cleared by an NMI interrupt, and transfer is not interrupted. [Clearing conditions] * * * When initialization is performed When NMI is input in burst mode When 0 is written to the DTME1 bit [Setting condition] When 1 is written to DTME1 after reading DTME1 =0 Rev. 1.00 Sep. 19, 2008 Page 329 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 6 Bit Name DTE1 Initial Value 0 R/W R/W Description Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTE1 bit is cleared to 0 when DTIE1 = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. When DTE1 = 1 and DTME1 = 1, data transfer is enabled and the DMAC waits for a request by the activation source. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions] * * * When initialization is performed When the specified number of transfers have been completed When 0 is written to the DTE1 bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE1 bit after reading DTE1 = 0 Rev. 1.00 Sep. 19, 2008 Page 330 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 5 Bit Name DTME0 Initial Value 0 R/W R/W Description Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0. If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME0 bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME0 bit is not cleared by an NMI interrupt, and transfer is not interrupted. [Clearing conditions] * * * When initialization is performed When NMI is input in burst mode When 0 is written to the DTME0 bit [Setting condition] When 1 is written to DTME0 after reading DTME0 =0 Rev. 1.00 Sep. 19, 2008 Page 331 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 4 Bit Name DTE0 Initial Value 0 R/W R/W Description Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTE0 bit is cleared to 0 when DTIE0 = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. When DTE0 = 1 and DTME0 = 1, data transfer is enabled and the DMAC waits for a request by the activation source. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions] * * * When initialization is performed When the specified number of transfers have been completed When 0 is written to the DTE0 bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE0 bit after reading DTE0 = 0 3 DTIE1B 0 R/W Data Transfer Interrupt Enable 1B Enables or disables an interrupt to the CPU or DTC when transfer on channel 1 is interrupted. If the DTME1 bit is cleared to 0 when DTIE1B = 1, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIE1B bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME1 bit to 1. Rev. 1.00 Sep. 19, 2008 Page 332 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bit 2 Bit Name DTIE1A Initial Value 0 R/W R/W Description Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE1 bit is cleared to 1 when DTIE1A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE1A bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE1 bit to 1. 1 DTIE0B 0 R/W Data Transfer Interrupt Enable 0B Enables or disables an interrupt to the CPU or DTC when transfer on channel 1 is interrupted. If the DTME0 bit is cleared to 0 when DTIE0B = 1, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIE0B bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME0 bit to 1. 0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE0 bit is cleared to 0 when DTIE0A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE0A bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE0 bit to 1. Rev. 1.00 Sep. 19, 2008 Page 333 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Bit 7 to 4 Bit Name Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 3 WE1B 0 R/W Write Enable 1B Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR. 0: Writes are disabled 1: Writes are enabled 2 WE1A 0 R/W Write Enable 1A Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR. 0: Writes are disabled 1: Writes are enabled 1 WE0B 0 R/W Write Enable 0B Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR. 0: Writes are disabled 1: Writes are enabled 0 WE0A 0 R/W Write Enable 0A Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. 0: Writes are disabled 1: Writes are enabled Rev. 1.00 Sep. 19, 2008 Page 334 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt request, and reactivating channel 0A. The address register and count register areas are set again during the first DTC transfer, then the control register area is set again during the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of other channels. MAR_0AH First transfer area MAR_0AL IOAR_0A ETCR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B MAR_1AH MAR_1AL DTC IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B DMAWER DMACR_0A DMACR_1A Second transfer area using chain transfer DMATCR DMACR_0B DMACR_1B DMABCR Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A) Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. Rev. 1.00 Sep. 19, 2008 Page 335 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When modifying these registers, the channel to be modified should be halted. 7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The TEND pin is available only for channel B in short address mode. Except for the block transfer mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal asserts in the transfer cycle in which the block counter contents reaches 0. Bit 7, 6 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 5 TEE1 0 R/W Transfer End Enable 1 Enables or disables transfer end pin 1 (TEND1) output. 0: TEND1 pin output disabled 1: TEND1 pin output enabled 4 TEE0 0 R/W Transfer End Enable 0 Enables or disables transfer end pin 0 (TEND0) output. 0: TEND0 pin output disabled 1: TEND0 pin output enabled 3 to 0 All 0 Reserved These bits are always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 336 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.4 Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.3 DMAC Activation Sources Short Address Mode Channels 0A and 1A Channels 0B and 1B Full Address Mode Normal Mode x x x x x x x x x x x x x x x x Block Transfer Mode Activation Source Internal interrupts ADI0 TXI0 RXI0 TXI1 RXI1 TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A External requests Auto-request Legend: : Can be specified x: Cannot be specified DREQ pin falling edge input DREQ pin low-level input Rev. 1.00 Sep. 19, 2008 Page 337 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.4.1 Activation by Internal Interrupt Request An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt request, the DMAC accepts the interrupt request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant. If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0 after completion of a transfer, an interrupt request from the selected activation source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant interrupt request is sent to the CPU or DTC. When an interrupt request signal for DMAC activation is also used for an interrupt request to the CPU or DTC activation (DTA = 0), the interrupt request flag is not cleared by the DMAC. Rev. 1.00 Sep. 19, 2008 Page 338 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Activation by External Request If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port should be set to input mode in advance*. Level sensing or edge sensing can be used for external requests. External request operation in normal mode of short address mode or full address mode is described below. When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is detected on the DREQ pin. The next data transfer may not be performed if the next edge is input before data transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. Note: * If the relevant port is set as an output pin for another function, DMA transfers using the channel in question cannot be guaranteed. 7.4.2 Activation by Auto-Request Auto-request is activated by register setting only, and transfer continues to the end. With autorequest activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC keeps possession of the bus until the end of the transfer so that transfer is performed continuously. 7.5 7.5.1 Operation Transfer Modes Table 7.4 lists the DMAC transfer modes. Rev. 1.00 Sep. 19, 2008 Page 339 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Table 7.4 DMAC Transfer Modes Transfer Source * TPU channel 0 to 5 compare match/input capture A interrupt * SCI transmission complete interrupt * SCI reception complete interrupt * A/D converter conversion end interrupt * External request Remarks * Up to 4 channels can operate independently * External request applies to channel B only * Single address mode applies to channel B only Transfer Mode Short address mode Dual address mode * 1-byte or 1-word transfer for a single transfer request * Specify source and destination addresses to transfer data in two bus cycles. (1) Sequential mode * Memory address incremented or decremented by 1 or 2 * Number of transfers: 1 to 65,536 (2) Idle mode * Memory address fixed * Number of transfers: 1 to 65,536 (3) Repeat mode * Memory address incremented or decremented by 1 or 2 * Continues transfer after sending number of transfers (1 to 256) and restoring the initial value Single address mode * 1-byte or 1-word transfer for a single transfer request * 1-bus cycle transfer by means of DACK pin instead of using address for specifying I/O * Sequential mode, idle mode, or repeat mode can be specified * External request Rev. 1.00 Sep. 19, 2008 Page 340 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Transfer Mode Full address mode Normal mode (1) Auto-request * Transfer request is internally held * Number of transfers (1 to 65,536) is continuously sent * Burst/cycle steal transfer can be selected (2) External request * 1-byte or 1-word transfer for a single transfer request * Number of transfers: 1 to 65,536 Block transfer mode * Transfer of 1-block, size selected for a single transfer request * Number of transfers: 1 to 65,536 * Source or destination can be selected as block area * Block size: 1 to 256 bytes or word Transfer Source * Auto-request Remarks * Max. 2-channel operation, combining channels A and B * External request * TPU channel 0 to 5 compare match/input capture A interrupt * SCI transmission complete interrupt * SCI reception complete interrupt * A/D converter conversion end interrupt * External request Rev. 1.00 Sep. 19, 2008 Page 341 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.5 summarizes register functions in sequential mode. Table 7.5 Register Functions in Sequential Mode Function Register 23 MAR 0 DTDIR = 0 DTDIR = 1 Initial Setting Source address register Operation Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer Start address of Fixed transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 23 H'FF 15 IOAR 0 Destination Source address address register register Transfer counter 15 ETCR 0 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Rev. 1.00 Sep. 19, 2008 Page 342 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (-1)DTID * (2DTSZ * (N - 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Rev. 1.00 Sep. 19, 2008 Page 343 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.4 shows an example of the setting procedure for sequential mode. [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Clear the RPE bit to 0 to select sequential mode. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts with the DTIE bit. * Set the DTE bit to 1 to enable transfer. Sequential mode setting Set DMABCRH Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Sequential mode Figure 7.4 Example of Sequential Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 344 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.6 Register Functions in Idle Mode Function Register 23 MAR 0 DTDIR = 0 DTDIR = 1 Initial Setting Source address register Operation Destination Start address of Fixed address transfer destination register or transfer source Start address of Fixed transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 23 H'FF 15 IOAR 0 Destination Source address address register register Transfer counter 15 ETCR 0 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. Rev. 1.00 Sep. 19, 2008 Page 345 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 7.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Rev. 1.00 Sep. 19, 2008 Page 346 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.6 shows an example of the setting procedure for idle mode. Idle mode setting [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Set the RPE bit to 1. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. * Set the DTIE bit to 1. * Set the DTE bit to 1 to enable transfer. Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Idle mode Figure 7.6 Example of Idle Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 347 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRL. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in repeat mode. Table 7.7 Register Functions in Repeat Mode Function Register 23 MAR 0 DTDIR = 0 DTDIR = 1 Initial Setting Source address register Operation Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer. Initial setting is restored when the value reaches H'0000 Start address of Fixed transfer source or transfer destination Number of transfers Fixed 23 H'FF 15 IOAR 0 Destination Source address address register register Holds number of transfers 7 0 ETCRAH Transfer counter 7 ETCRAL 0 Number of transfers Decremented every transfer. Loaded with ETCRH value when the value reaches H'00 Rev. 1.00 Sep. 19, 2008 Page 348 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR - (-1)DTID * 2DTSZ * ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Rev. 1.00 Sep. 19, 2008 Page 349 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (-1)DTID * (2DTSZ * (N - 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.7 Operation in Repeat mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Rev. 1.00 Sep. 19, 2008 Page 350 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL. [2] [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Set the RPE bit to 1. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. * Clear the DTIE bit to 0. * Set the DTE bit to 1 to enable transfer. Repeat mode setting Set DMABCRH Set transfer source and transfer destination addresses Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Repeat mode Figure 7.8 Example of Repeat Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 351 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.8 Register Functions in Single Address Mode Function Register 23 MAR 0 DTDIR = 0 DTDIR = 1 Initial Setting Source address register Operation Destination Start address of See sections 7.5.2, address transfer destination Sequential Mode, register or transfer source 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. Read strobe (Set automatically by SAE bit in DMABCRH; IOAR is invalid) Strobe for external device DACK pin Write strobe 15 ETCR 0 Transfer counter Number of transfers See sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output. Rev. 1.00 Sep. 19, 2008 Page 352 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.9 illustrates operation in single address mode (when sequential mode is specified). Address T Transfer DACK 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (-1)DTID * (2DTSZ * (N - 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified) Rev. 1.00 Sep. 19, 2008 Page 353 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Single address mode setting Set DMABCRH [1] [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Set the SAE bit to 1 to select single address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR. Set transfer source and transfer destination addresses [2] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Clear the RPE bit to 0 to select sequential mode. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts with the DTIE bit. * Set the DTE bit to 1 to enable transfer. Set DMABCRL [6] Single address mode Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential Mode Is Specified) Rev. 1.00 Sep. 19, 2008 Page 354 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9 summarizes register functions in normal mode. Table 7.9 Register 23 MARA 23 MARB 15 ETCRA 0 0 0 Register Functions in Normal Mode Function Source address register Destination address register Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed Start address of Incremented/decremented transfer destination every transfer, or fixed Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536. Rev. 1.00 Sep. 19, 2008 Page 355 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.11 illustrates operation in normal mode. Address TA Transfer Address TB Address BA Legend: Address Address Address Address Where : Address BB TA TB BA BB LA LB N = LA = LB = LA + SAIDE * (-1)SAID * (2DTSZ * (N - 1)) = LB + DAIDE * (-1)DAID * (2DTSZ * (N - 1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.11 Operation in Normal Mode Rev. 1.00 Sep. 19, 2008 Page 356 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Transfer requests (activation sources) are external requests and auto-requests. With auto-requests, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-requests, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. Rev. 1.00 Sep. 19, 2008 Page 357 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.12 shows an example of the setting procedure for normal mode. Normal mode setting [1] Set each bit in DMABCRH. * Set the FAE bit to 1 to select full address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACRA and DMACRB. * Set the transfer data size with the DTSZ bit. * Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. * Clear the BLKE bit to 0 to select normal mode. * Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. * Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Read DMABCRL [5] Set DMABCRL [6] [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts with the DTIE bit. * Set both the DTME bit and the DTE bit to 1 to enable transfer. Normal mode Figure 7.12 Example of Normal Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 358 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.7 Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode Register 23 MARA 23 MARB 7 0 ETCRAH Function 0 Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed Source address register Destination address register Holds block size Block size counter 0 Start address of Incremented/decremented transfer destination every transfer, or fixed Block size Fixed Block size 7 ETCRAL 15 ETCRB 0 Decremented every transfer; ETCRAH value copied when count reaches H'00 Decremented every block transfer; transfer ends when count reaches H'0000 0 Block transfer counter Number of block transfers MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Rev. 1.00 Sep. 19, 2008 Page 359 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area. Address TA 1st block Transfer Block area Address TB 2nd block Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE * (-1)SAID * (2DTSZ * (M*N - 1)) = LB + DAIDE * (-1)DAID * (2DTSZ * (N - 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) Rev. 1.00 Sep. 19, 2008 Page 360 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area. Address TA Block area Address BA Address TB Transfer Consecutive transfer of M bytes or words is performed in response to one request 2nd block 1st block Nth block Address BB Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE * (-1)SAID * (2DTSZ * (N - 1)) = LB + DAIDE * (-1)DAID * (2DTSZ * (M*N - 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) Rev. 1.00 Sep. 19, 2008 Page 361 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Rev. 1.00 Sep. 19, 2008 Page 362 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.15 shows the operation flow in block transfer mode. Start (DTE = DTME = 1) No Transfer request? Yes Acquire bus Read address specified by MARA MARA = MARA + SAIDE*(-1)SAID*2DTSZ Write to address specified by MARB MARB = MARB + DAIDE*(-1)DAID *2DTSZ ETCRAL = ETCRAL - 1 No ETCRAL = H'00 Yes Release bus ETCRAL = ETCRAH BLKDIR = 0 Yes No MARB = MARB - DAIDE*(-1)DAID*2DTSZ*ETCRAH MARA = MARA - SAIDE*(-1)SAID*2DTSZ*ETCRAH ETCRB = ETCRB - 1 No ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer Figure 7.15 Operation Flow in Block Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 363 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. * Set the FAE bit to 1 to select full address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL. Set the number of transfers in ETCRB. [4] Set each bit in DMACRA and DMACRB. * Set the transfer data size with the DTSZ bit. * Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. * Set the BLKE bit to 1 to select block transfer mode. * Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit. * Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. * Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Set DMABCRL [6] [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts to the CPU with the DTIE bit. * Set both the DTME bit and the DTE bit to 1 to enable transfer. Block transfer mode setting Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Block transfer mode Figure 7.16 Example of Block Transfer Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 364 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings. The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. CPU cycle T1 DMAC cycle (1-word transfer) T2 T1 T2 T3 T1 T2 T3 CPU cycle Source address Address bus RD HWR LWR Destination address Figure 7.17 Example of DMA Transfer Bus Timing Rev. 1.00 Sep. 19, 2008 Page 365 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.9 (1) DMA Transfer (Dual Address Mode) Bus Cycles Short Address Mode Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read Address bus RD HWR LWR TEND DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.18 Example of Short Address Mode Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle. Rev. 1.00 Sep. 19, 2008 Page 366 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (2) Full Address Mode (Cycle Steal Mode) Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read Address bus RD HWR LWR TEND DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one bus cycle is executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev. 1.00 Sep. 19, 2008 Page 367 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (3) Full Address Mode (Burst Mode) Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead Address bus RD HWR LWR TEND Bus release Burst transfer Last transfer cycle Bus release Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI interrupt is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit in DMABCRL is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared. Rev. 1.00 Sep. 19, 2008 Page 368 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (4) Full Address Mode (Block Transfer Mode) Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read Address bus RD HWR LWR TEND Bus release Block transfer Bus release Last block transfer Bus release DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) A one-block transfer is performed for a single transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated during data transfer, block transfer operation is not affected until data transfer for one block has ended. (5) DREQ Pin Falling Edge Activation Timing Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge. Rev. 1.00 Sep. 19, 2008 Page 369 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bus release DREQ Address bus DMA control Channel DMA read DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Idle Read Write Idle Request Minimum of 2 cycles [1] [2] [3] Request clear period Request Minimum of 2 cycles [4] [5] [6] Request clear period [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA write cycle ends, acceptance resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling edge. Rev. 1.00 Sep. 19, 2008 Page 370 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 1 block transfer Bus release DREQ Address bus DMA control Channel DMA read DMA write DMA Bus dead release DMA read 1 block transfer DMA write DMA dead Bus release Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Dead Idle Read Write Dead Idle Request Request clear period Request Minimum of 2 cycles Request clear period Minimum of 2 cycles [1] [2] [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 1.00 Sep. 19, 2008 Page 371 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (6) DREQ Pin Low Level Activation Timing (Normal Mode) Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level. Bus release DREQ Address bus DMA control Channel Idle DMA read DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination Transfer source Transfer destination Read Write Idle Read Write Idle Request Minimum of 2 cycles [1] [2] Request clear period Request Minimum of 2 cycles Request clear period [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 1.00 Sep. 19, 2008 Page 372 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level. 1 block transfer Bus release DREQ Address bus DMA control Channel DMA read DMA write DMA Bus dead release DMA read 1 block transfer DMA write DMA dead Bus release Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Dead Idle Read Write Dead Idle Request Minimum of 2 cycles [1] [2] [3] Request clear period Request Minimum of 2 cycles [4] [5] [6] Request clear period [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 1.00 Sep. 19, 2008 Page 373 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.10 (1) DMA Transfer (Single Address Mode) Bus Cycles Single Address Mode (Read) Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA DMA read dead DMA read DMA read DMA read Address bus RD DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.26 Example of Single Address Mode Transfer (Byte Read) Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. Rev. 1.00 Sep. 19, 2008 Page 374 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) DMA read Address bus RD DACK TEND DMA read DMA read DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.27 Example of Single Address Mode (Word Read) Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev. 1.00 Sep. 19, 2008 Page 375 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (2) Single Address Mode (Write) Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA DMA write dead DMA write DMA write DMA write Address bus HWR LWR DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.28 Example of Single Address Mode Transfer (Byte Write) Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. Rev. 1.00 Sep. 19, 2008 Page 376 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) DMA write Address bus HWR LWR DACK TEND DMA write DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.29 Example of Single Address Mode Transfer (Word Write) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. (3) DREQ Pin Falling Edge Activation Timing Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling edge. Rev. 1.00 Sep. 19, 2008 Page 377 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Bus release DREQ Address bus DACK DMA single Bus release DMA single Bus release Transfer source/ destination Transfer source/ destination DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle ends, acceptance resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 1.00 Sep. 19, 2008 Page 378 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (4) DREQ Pin Low Level Activation Timing Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low level. Bus release Bus release DREQ DMA single Bus release DMA single Address bus DACK Transfer source/ destination Transfer source/ destination DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes [1] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMAC cycle is started. [4] [7] Acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. Rev. 1.00 Sep. 19, 2008 Page 379 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.11 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfer and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus mastership, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7.32 shows an example of dual address transfer using the write data buffer function. The data is transferred from on-chip RAM to external memory. DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead Internal address Internal read signal External address HWR, LWR TEND Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function Rev. 1.00 Sep. 19, 2008 Page 380 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) Figure 7.33 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. DMA read DMA single CPU read DMA single CPU read Internal address Internal read signal External address RD DACK Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer. 7.5.12 Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.11 summarizes the priority order for DMAC channels. Table 7.11 DMAC Channel Priority Order Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High Rev. 1.00 Sep. 19, 2008 Page 381 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released, the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA DMA write read DMA read Address bus RD HWR LWR DMA control Idle Read Channel 0A Channel 0B Channel 1 Bus release Write DMA write DMA read DMA write DMA read Idle Read Write Idle Read Write Read Request clear Request hold Request hold Selection Nonselection Request clear Request hold Bus release Selection Request clear Bus release Channel 1 transfer Channel 0A transfer Channel 0B transfer Figure 7.34 Example of Multi-Channel Transfer Rev. 1.00 Sep. 19, 2008 Page 382 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle, or external bus release cycle may arise. In this case, the bus controller will suspend the transfer and insert a refresh cycle, EXDMAC cycle, or external bus release cycle, in accordance with the external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed until the DMAC releases the external bus.) When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after an external write cycle. The external read cycle and external write cycle are inseparable, and so the bus cannot be released between these two cycles. When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC cycle may be executed at the same time as a refresh cycle, EXDMAC cycle, or external bus release cycle. Rev. 1.00 Sep. 19, 2008 Page 383 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit in DMABCRLare set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7.35 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. [1] [2] [1] No Check that DTE = 1 and DTME = 0 in DMABCRL. Write 1 to the DTME bit. Resumption of transfer on interrupted channel DTE bit = 1 DTME bit = 0 Yes Set DTME bit to 1 [2] Transfer continues Transfer ends Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt Rev. 1.00 Sep. 19, 2008 Page 384 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.15 Forced Termination of DMAC Operation If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL. Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software. Forced termination of DMAC [1] Clear the DTE bit in DMABCRL to 0. To prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Clear DTE bit to 0 [1] Forced termination Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation Rev. 1.00 Sep. 19, 2008 Page 385 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.5.16 Clearing Full Address Mode Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. Clearing full address mode [1] Clear both the DTE bit and DTME bit in DMABCRL to 0, or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [1] [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0 Stop the channel Initialize DMACR [2] Clear FAE bit to 0 [3] Initialization; operation halted Figure 7.37 Example of Procedure for Clearing Full Address Mode Rev. 1.00 Sep. 19, 2008 Page 386 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.6 Interrupt Sources The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12 shows the interrupt sources and their priority order. Table 7.12 Interrupt Sources and Priority Order Interrupt Source Interrupt Name DMTEND0A DMTEND0B DMTEND1A DMTEND1B Short Address Mode Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0B Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1B Full Address Mode Interrupt due to end of transfer on channel 0 Interrupt due to break in transfer on channel 0 Interrupt due to end of transfer on channel 1 Interrupt due to break in transfer on channel 1 Low Interrupt Priority Order High Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt controller independently. The priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.12. Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0. DTE/ DTME Transfer end/transfer break interrupt DTIE Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0 while the DTIE bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting. Rev. 1.00 Sep. 19, 2008 Page 387 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) 7.7 (1) Usage Notes DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. * DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 7.39 shows an example of the update timing for DMAC registers in dual address transfer mode. DMA transfer cycle DMA last transfer cycle DMA dead DMA read DMA Internal address DMA control DMA register operation Idle Transfer source Read Transfer destination Write DMA write DMA read DMA write Transfer source Idle Read Transfer destination Write Dead Idle [1] [2] [1] [2'] [3] [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented) Block size counter ETCR operation (decremented in block transfer mode) [2] Transfer destination address register MAR operation (incremented/decremented/fixed) [2']Transfer destination address register MAR operation (incremented/decremented/fixed) Block transfer counter ETCR operation (decremented, in last transfer cycle of a block in block transfer mode) [3] Transfer address register MAR restore operation (in block or repeat transfer mode) Transfer counter ETCR restore (in repeat transfer mode) Block size counter ETCR restore (in block transfer mode) Note: In single address transfer mode, the update timing is the same as [1]. The MAR operation is post-incrementing/decrementing of the DMA internal address value. Figure 7.39 DMAC Register Update Timing Rev. 1.00 Sep. 19, 2008 Page 388 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) * If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.40. CPU longword read MAR upper word read DMA internal address DMA control DMA register operation Idle Transfer destination Write MAR lower word read DMA transfer cycle DMA read DMA write Transfe source Read Idle [1] [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.40 Contention between DMAC Register Update and CPU Read (2) Module Stop When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. * Transfer end/break interrupt (DTE = 0 and DTIE = 1) * TEND pin enable (TEE = 1) * DACK pin enable (FAE = 0 and SAE = 1) Rev. 1.00 Sep. 19, 2008 Page 389 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (3) Write Data Buffer Function When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. * Write data buffer function and DMAC register setting If the setting of a register that controls external accesses is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. Registers that control external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access. * Write data buffer function and next DMAC operation The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. (4) TEND Output If the last transfer cycle is for an internal address, note that even if low-level output at the TEND pin has been set, a low level may not be output at the TEND pin under the following external bus conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed in parallel. 1. 2. 3. 4. 5. EXDMAC cycle Write cycle with write buffer mode enabled DMAC single address cycle for a different channel with write buffer mode enabled Bus release cycle CBR refresh cycle Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2 above. If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in synchronization with the bus cycle. However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in this case for the refresh cycle. Rev. 1.00 Sep. 19, 2008 Page 390 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) DMA read Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. DMA write Figure 7.41 Example in which Low Level Is Not Output at TEND Pin (5) Activation by Falling Edge on DREQ Pin DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed on detection of a low level. Rev. 1.00 Sep. 19, 2008 Page 391 of 1270 REJ09B0466-0100 Section 7 DMA Controller (DMAC) (6) Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before write to DMABCRL to enable transfer. When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. (7) Internal Interrupt after End of Transfer When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible termination, the selected internal interrupt request will be sent to the CPU or DTC even if the DTA bit in DMABCRH is set to 1. Also, if internal DMAC activation has already been initiated when operation is forcibly terminated, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if the DTA bit is set to 1. An internal interrupt request following the end of transfer or a forcible termination should be handled by the CPU as necessary. (8) Channel Re-Setting To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write 1 to them. Rev. 1.00 Sep. 19, 2008 Page 392 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Section 8 EXDMA Controller (EXDMAC) This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility. Note: This EXDMAC is not supported by the H8S/2424 Group. 8.1 * * * * * * * * * * * Features Direct specification of 16-Mbyte address space Selection of byte or word transfer data length Maximum number of transfers: 16M (16,777,215)/infinite (free-running) Selection of dual address mode or single address mode Selection of cycle steal mode or burst mode as bus mode Selection of normal mode or block transfer mode as transfer mode Two kinds of transfer requests: external request and auto-request An interrupt request can be sent to the CPU at the end of the specified number of transfers. Repeat area designation function: Operation in parallel with internal bus master: Acceptance of a transfer request and the start of transfer processing can be reported to an external device via the EDRAK pin. * Module stop mode can be set. Rev. 1.00 Sep. 19, 2008 Page 393 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Figure 8.1 shows a block diagram of the EXDMAC. Bus controller Data buffer External pins EDREQ EDRAK ETEND EDACK Interrupt request signals to CPU for individual channels Control logic Address buffer Processor EDSAR EDDAR EDMDR EDACR EDTCR Internal data bus Legend: EDSAR: EDDAR: EDTCR: EDMDR: EDACR: EXDMA source address register EXDMA destination address register EXDMA transfer count register EXDMA mode control register EXDMA address control register Figure 8.1 Block Diagram of EXDMAC Rev. 1.00 Sep. 19, 2008 Page 394 of 1270 REJ09B0466-0100 Module data bus Section 8 EXDMA Controller (EXDMAC) 8.2 Input/Output Pins Table 8.1 shows the pin configuration of the EXDMAC. Table 8.1 Channel 2 Pin Configuration Name EXDMA transfer request 2 EXDMA transfer acknowledge 2 EXDMA transfer end 2 EDREQ2 acceptance acknowledge Abbreviation EDREQ2 EDACK2 ETEND2 EDRAK2 I/O Input Output Output Output Function Channel 2 external request Channel 2 single address transfer acknowledge Channel 2 transfer end Notification to external device of channel 2 external request acceptance and start of transfer processing Channel 3 external request Channel 3 single address transfer acknowledge Channel 3 transfer end Notification to external device of channel 3 external request acceptance and start of transfer processing 3 EXDMA transfer request 3 EXDMA transfer acknowledge 3 EXDMA transfer end 3 EDREQ3 acceptance acknowledge EDREQ3 EDACK3 ETEND3 EDRAK3 Input Output Output Output Rev. 1.00 Sep. 19, 2008 Page 395 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.3 Register Descriptions The EXDMAC has the following registers. * * * * * * * * * * EXDMA source address register_2 (EDSAR_2) EXDMA destination address register_2 (EDDAR_2) EXDMA transfer count register_2 (EDTCR_2) EXDMA mode control register_2 (EDMDR_2) EXDMA address control register_2 (EDACR_2) EXDMA source address register_3 (EDSAR_3) EXDMA destination address register_3 (EDDAR_3) EXDMA transfer count register_3 (EDTCR_3) EXDMA mode control register_3 (EDMDR_3) EXDMA address control register_3 (EDACR_3) EXDMA Source Address Register (EDSAR) 8.3.1 EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when a device with DACK is specified as the transfer source. The upper 8 bits of EDSAR are reserved; they are always read as 0 and cannot be modified. Only 0 should be written to these bits. EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDSAR for a channel on which EXDMA transfer is in progress. The initial values of EDSAR are undefined. Rev. 1.00 Sep. 19, 2008 Page 396 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.3.2 EXDMA Destination Address Register (EDDAR) EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An address update function is provided that updates the register contents to the next transfer destination address each time transfer processing is performed. In single address mode, the EDDAR value is ignored when a device with DACK is specified as the transfer destination. The upper 8 bits of EDDAR are reserved; they are always read as 0 and cannot be modified. Only 0 should be written to these bits. EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR are undefined. 8.3.3 EXDMA Transfer Count Register (EDTCR) EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do not write to EDTCR for a channel on which EXDMA transfer is in progress. (1) Bit 31 to 24 Normal Transfer Mode Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 23 to 0 All 0 R/W 24-Bit Transfer Counter These bits specify the number of transfers. Setting H'000001 specifies one transfer. Setting H'000000 means no specification for the number of transfers, and the transfer counter function is halted. In this case, there is no transfer end interrupt by the transfer counter. Setting H'FFFFFF specifies the maximum number of transfers, that is 16,777,215. During EXDMA transfer, this counter shows the remaining number of transfers. This counter can be read at all times. When reading EDTCR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Rev. 1.00 Sep. 19, 2008 Page 397 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Bit Block Transfer Mode Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 31 to 24 23 to 16 Undefined R/W Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256. The register value always indicates the specified block size. 15 to 0 Undefined R/W 16-Bit Transfer Counter These bits specify the number of block transfers. Setting H'0001 specifies one block transfer. Setting H'0000 means no specification for the number of transfers, and the transfer counter function is halted. In this case, there is no transfer end interrupt by the transfer counter. Setting H'FFFF specifies the maximum number of block transfers, that is 65,535. During EXDMA transfer, this counter shows the remaining number of block transfers. Rev. 1.00 Sep. 19, 2008 Page 398 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.3.4 EXDMA Mode Control Register (EDMDR) EDMDR controls EXDMAC operations. Bit 15 Bit Name EDA Initial Value 0 R/W R/(W) Description EXDMA Active Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto request mode is specified (by bits MDS1 and MDS0), transfer processing begins when this bit is set to 1. With external requests, transfer processing begins when a transfer request is issued after this bit has been set to 1. When this bit is cleared to 0 during an EXDMA operation, transfer is halted. If this bit is cleared to 0 during an EXDMA operation in block transfer mode, transfer processing is continued for the currently executing one-block transfer, and the bit is cleared on completion of the currently executing one-block transfer. If an external source that ends (aborts) transfer occurs, this bit is automatically cleared to 0 and transfer is terminated. Do not change the operating mode, transfer method, or other parameters while this bit is set to 1. 0: Data transfer disabled on corresponding channel [Clearing conditions] * * * When the specified number of transfers end When operation is halted by a repeat area overflow interrupt When 0 is written to EDA while EDA = 1 (In block transfer mode, write is effective after end of one-block transfer) Reset, NMI interrupt, hardware standby mode * 1: Data transfer enabled on corresponding channel Note: The value written in the EDA bit may not be effective immediately. Rev. 1.00 Sep. 19, 2008 Page 399 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit 14 Bit Name BEF Initial Value 0 R/W R/(W)* Description Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1. The address registers indicate the next transfer addresses, but the data for which transfer has been performed within the block size is lost. 0: No block transfer error [Clearing condition] Writing 0 to BEF after reading BEF = 1 1: Block transfer error [Setting condition] NMI interrupt during block transfer 13 EDRAKE 0 R/W EDRAK Pin Output Enable Enables output from the EDREQ acknowledge/transfer processing start (EDRAK) pin. 0: EDRAK pin output disabled 1: EDRAK pin output enabled 12 ETENDE 0 R/W ETEND Pin Output Enable Enables output from the EXDMA transfer end (ETEND) pin. 0: ETEND pin output disabled 1: ETEND pin output enabled 11 EDREQS 0 R/W EDREQ Select Specifies low level sensing or falling edge sensing as the sampling method for the EDREQ pin used in external request mode. 0: Low level sensing (Low level sensing is used for the first transfer after transfer is enabled.) 1: Falling edge sensing Rev. 1.00 Sep. 19, 2008 Page 400 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit 10 Bit Name AMS Initial Value 0 R/W R/W Description Address Mode Select Selects single address mode or dual address mode. When single address mode is selected, the EDACK pin is valid. 0: Dual address mode 1: Single address mode 9 8 MDS1 MDS0 0 0 R/W R/W Mode Select 1 and 0 These bits specify the activation source, bus mode, and transfer mode. 00: Auto request, cycle steal mode, normal transfer mode 01: Auto request, burst mode, normal transfer mode 10: External request, cycle steal mode, normal transfer mode 11: External request, cycle steal mode, block transfer mode 7 EDIE 0 R/W EXDMA Interrupt Enable Enables or disables interrupt requests. When this bit is set to 1, an interrupt is requested when the IRF bit is set to 1. The interrupt request is cleared by clearing this bit or the IRF bit to 0. 0: Interrupt request is not generated 1: Interrupt request is generated Rev. 1.00 Sep. 19, 2008 Page 401 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit 6 Bit Name IRF Initial Value 0 R/W R/(W)* Description Interrupt Request Flag Flag indicating that an interrupt request has occurred and transfer has ended. 0: No interrupt request [Clearing conditions] * * Writing 1 to the EDA bit Writing 0 to IRF after reading IRF = 1 1: Interrupt request occurrence [Setting conditions] * * * 5 TCEIE 0 R/W Transfer end interrupt request generated by transfer counter Source address repeat area overflow interrupt request Destination address repeat area overflow interrupt request Transfer Counter End Interrupt Enable Enables or disables transfer end interrupt requests by the transfer counter. When transfer ends according to the transfer counter while this bit is set to 1, the IRF bit is set to 1, indicating that an interrupt request has occurred. 0: Transfer end interrupt requests by transfer counter are disabled 1: Transfer end interrupt requests by transfer counter are enabled 4 SDIR 0 R/W Single Address Direction Specifies the data transfer direction in single address mode. In dual address mode, the specification by this bit is ignored. 0: Transfer direction: EDSAR external device with DACK 1: Transfer direction: External device with DACK EDDAR Rev. 1.00 Sep. 19, 2008 Page 402 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit 3 Bit Name DTSIZE Initial Value 0 R/W R/W Description Data Transmit Size Specifies the size of data to be transferred. 0: Byte-size 1: Word-size 2 BGUP 0 R/W Bus Give-Up When this bit is set to 1, the bus can be transferred to an internal bus master in burst mode or block transfer mode. This setting is ignored in normal mode and cycle steal mode. 0: Bus is not released 1: Bus is transferred if requested by an internal bus master 1 0 Note: -- -- * 0 0 R/W R/W Reserved These bits are always read as 0. The initial values should not be modified. Only 0 can be written, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 403 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.3.5 EXDMA Address Control Register (EDACR) EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit 15 14 Bit Name SAT1 SAT0 Initial Value 0 0 R/W R/W R/W Description Source Address Update Mode These bits specify incrementing/decrementing of the transfer source address (EDSAR). When an external device with DACK is designated as the transfer source in single address mode, the specification by these bits is ignored. 0x: Fixed 10: Incremented (+1 in byte transfer, +2 in word transfer) 11: Decremented (-1 in byte transfer, -2 in word transfer) 13 SARIE 0 R/W Source Address Repeat Interrupt Enable When this bit is set to 1, in the event of source address repeat area overflow, the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1, an interrupt request is sent to the CPU. When used together with block transfer mode, a source address repeat interrupt is requested at the end of a block-size transfer. If the EDA bit is set to 1 in EDMDR for the channel on which transfer is terminated by a source address repeat interrupt, transfer can be resumed from the state in which it ended. If a source address repeat area has not been designated, this bit is ignored. 0: Source address repeat interrupt is not requested 1: When source address repeat area overflow occurs, the IRF bit in EDMDR is set to 1 and an interrupt is requested Rev. 1.00 Sep. 19, 2008 Page 404 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit 12 11 10 9 8 Bit Name SARA4 SARA3 SARA2 SARA1 SARA0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Source Address Repeat Area These bits specify the source address (EDSAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power-of-two number of bytes. When repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last address of the repeat area in the case of address decrementing. If the SARIE bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: Not designated as repeat area 00001: Lower 1 bit (2-byte area) designated as repeat area 00010: Lower 2 bits (4-byte area) designated as repeat area 00011: Lower 3 bits (8-byte area) designated as repeat area 00100: Lower 4 bits (16-byte area) designated as repeat area : : 10011: Lower 19 bits (512-Kbyte area) designated as repeat area 10100: Lower 20 bits (1-Mbyte area) designated as repeat area 10101: Lower 21 bits (2-Mbyte area) designated as repeat area 10110: Lower 22 bits (4-Mbyte area) designated as repeat area 10111: Lower 23 bits (8-Mbyte area) designated as repeat area 11xxx: Setting prohibited Rev. 1.00 Sep. 19, 2008 Page 405 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit 7 6 Bit Name DAT1 DAT0 Initial Value 0 0 R/W R/W R/W Description Destination Address Update Mode These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored. 0x: Fixed 10: Incremented (+1 in byte transfer, +2 in word transfer) 11: Decremented (-1 in byte transfer, -2 in word transfer) 5 DARIE 0 R/W Destination Address Repeat Interrupt Enable When this bit is set to 1, in the event of destination address repeat area overflow the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1, an interrupt request is sent to the CPU. When used together with block transfer mode, a destination address repeat interrupt is requested at the end of a block-size transfer. If the EDA bit is set to 1 in EDMDR for the channel on which transfer is terminated by a destination address repeat interrupt, transfer can be resumed from the state in which it ended. If a destination address repeat area has not been designated, this bit is ignored. 0: Destination address repeat interrupt is not requested 1: When destination address repeat area overflow occurs, the IRF bit in EDMDR is set to 1 and an interrupt is requested Rev. 1.00 Sep. 19, 2008 Page 406 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Bit 4 3 2 1 0 Bit Name DARA4 DARA3 DARA2 DARA1 DARA0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Destination Address Repeat Area These bits specify the destination address (EDDAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a powerof-two number of bytes. When repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last address of the repeat area in the case of address decrementing. If the DARIE bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: Not designated as repeat area 00001: Lower 1 bit (2-byte area) designated as repeat area 00010: Lower 2 bits (4-byte area) designated as repeat area 00011: Lower 3 bits (8-byte area) designated as repeat area 00100: Lower 4 bits (16-byte area) designated as repeat area : : 10011: Lower 19 bits (512-Kbyte area) designated as repeat area 10100: Lower 20 bits (1-Mbyte area) designated as repeat area 10101: Lower 21 bits (2-Mbyte area) designated as repeat area 10110: Lower 22 bits (4-Mbyte area) designated as repeat area 10111: Lower 23 bits (8-Mbyte area) designated as repeat area 11xxx: Setting prohibited Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 407 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4 8.4.1 Operation Transfer Modes The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.2 EXDMAC Transfer Modes Transfer Origin Auto request External request External request 1 to 65,535 or no specification Number of Transfers Address Registers Source Destination EDDAR Transfer Mode Dual address mode Normal transfer mode Auto request mode * Burst/cycle steal mode External request mode * Cycle steal mode Block transfer mode External request mode * Burst transfer of specified block size for a single transfer request * Block size: 1 to 256 bytes or words Single address mode 1 to EDSAR 16,777,215 or no specification * Direct data transfer to/from external device using EDACK pin instead of source or destination address register * Above transfer mode can be specified in addition to address register setting * One transfer possible in one bus cycle (Transfer mode variations are the same as in dual address mode.) EDSAR/ EDACK EDACK/ EDDAR The transfer mode can be set independently for each channel. In normal transfer mode, a one-byte or one-word transfer is executed in response to one transfer request. With auto requests, burst or cycle steal transfer mode can be set. In burst transfer mode, continuous, high-speed transfer can be performed until the specified number of transfers have been executed or the transfer enable bit is cleared to 0. Rev. 1.00 Sep. 19, 2008 Page 408 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode. When the "no specification" setting (EDTCR = H'000000) is made for the number of transfers, the transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be performed endlessly. Incrementing or decrementing the memory address by 1 or 2, or leaving the address unchanged, can be specified independently for each address register. In all transfer modes, it is possible to set a repeat area comprising a power-of-two number of bytes. 8.4.2 (1) Address Modes Dual Address Mode In dual address mode, both the transfer source and transfer destination are specified by registers in the EXDMAC, and one transfer is executed in two bus cycles. The transfer source address is set in the source address register (EDSAR), and the transfer destination address is set in the transfer destination address register (EDDAR). In a transfer operation, the value in external memory specified by the transfer source address is read in the first bus cycle, and is written to the external memory specified by the transfer destination address in the next bus cycle. These consecutive read and write cycles are indivisible: another bus cycle (external access by an internal bus master, refresh cycle, or external bus release cycle) does not occur between these two cycles. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for two consecutive bus cycles. The EDACK signal is not output. Figure 8.2 shows an example of the timing in dual address mode. Rev. 1.00 Sep. 19, 2008 Page 409 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) EXDMA read cycle Address bus RD WR ETEND EDSAR EXDMA write cycle EDDAR Figure 8.2 Example of Timing in Dual Address Mode (2) Single Address Mode In single address mode, the EDACK signal is used instead of the source or destination address register to transfer data directly between an external device and external memory. In this mode, the EXDMAC accesses the transfer source or transfer destination external device by outputting the external I/O strobe signal (EDACK), and at the same time accesses the other external device in the transfer by outputting an address. In this way, DMA transfer can be executed in one bus cycle. In the example of transfer between external memory and an external device with DACK shown in figure 8.3, data is output to the data bus by the external device and written to external memory in the same bus cycle. The transfer direction, that is whether the external device with DACK is the transfer source or transfer destination, can be specified with the SDIR bit in EDMDR. Transfer is performed from the external memory (EDSAR) to the external device with DACK when SDIR = 0, and from the external device with DACK to the external memory (EDDAR) when SDIR = 1. The setting in the source or destination address register not used in the transfer is ignored. The EDACK pin becomes valid automatically when single address mode is selected. The EDACK pin is active-low. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for one bus cycle. Rev. 1.00 Sep. 19, 2008 Page 410 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the timing. External address bus External data bus Microcomputer External memory EXDMAC External device with DACK EDACK EDREQ Data flow Figure 8.3 Data Flow in Single Address Mode Rev. 1.00 Sep. 19, 2008 Page 411 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Transfer from external memory to external device with DACK EXDMA cycle Address bus RD WR EDACK Data bus ETEND Data output from external memory EDSAR Address to external memory space RD signal to external memory space Transfer from external device with DACK to external memory EXDMA cycle Address bus RD WR EDACK Data bus ETEND Data output from external device with DACK WR signal to external memory space EDDAR Address to external memory space Figure 8.4 Example of Timing in Single Address Mode Rev. 1.00 Sep. 19, 2008 Page 412 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.3 (1) DMA Transfer Requests Auto Request Mode In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR. In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode. Block transfer mode cannot be used. (2) External Request Mode In external request mode, transfer is started by a transfer request signal (EDREQ) from a device external to this LSI. DMA transfer is started when EDREQ is input while DMA transfer is enabled (EDA = 1). The transfer request source need not be the data transfer source or data transfer destination. The transfer request signal is accepted via the EDREQ pin. Either falling edge sensing or low level sensing can be selected for the EDREQ pin by means of the EDREQS bit in EDMDR (low level sensing when EDREQS = 0, falling edge sensing when EDREQS = 1). Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance to be output from the EDRAK pin. The EDRAK signal is output when acceptance and transfer processing has been started in response to a single external request. The EDRAK signal enables the external device to determine the timing of EDREQ signal negation, and makes it possible to provide handshaking between the transfer request source and the EXDMAC. In external request mode, block transfer mode can be used instead of burst mode. Block transfer mode allows continuous execution (burst operation) of the specified number of transfers (the block size) in response to a single transfer request. In block transfer mode, the EDRAK signal is output only once for a one-block transfer, since the transfer request via the EDREQ pin is for a block unit. Rev. 1.00 Sep. 19, 2008 Page 413 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.4 Bus Modes There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto request, either cycle steal mode or burst mode can be selected. When the activation source is an external request, cycle steal mode is used. (1) Cycle Steal Mode In cycle steal mode, the EXDMAC releases the bus at the end of each transfer of a transfer unit (byte, word, or block). If there is a subsequent transfer request, the EXDMAC takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This procedure is repeated until the transfer end condition is satisfied. If a transfer request occurs in another channel during DMA transfer, the bus is temporarily released, then transfer is performed on the channel for which the transfer request was issued. If there is no external space bus request from another bus master, a one-cycle bus release interval is inserted. For details on the operation when there are requests for a number of channels, see section 8.4.8, Channel Priority Order. Figure 8.5 shows an example of the timing in cycle steal mode. EDREQ EDRAK Bus cycle CPU CPU EXDMAC CPU CPU EXDMAC Bus returned temporarily to CPU Transfer conditions: * Single address mode, normal transfer mode * EDREQ low level sensing * CPU internal bus master is operating in external space Figure 8.5 Example of Timing in Cycle Steal Mode Rev. 1.00 Sep. 19, 2008 Page 414 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Burst Mode In burst mode, once the EXDMAC acquires the bus it continues transferring data, without releasing the bus, until the transfer end condition is satisfied. There is no burst mode in external request mode. In burst mode, once transfer is started it is not interrupted even if there is a transfer request from another channel with higher priority. When the burst mode channel finishes its transfer, it releases the bus in the next cycle in the same way as in cycle steal mode. When the EDA bit is cleared to 0 in EDMDR, DMA transfer is halted. However, DMA transfer is executed for all transfer requests generated within the EXDMAC up until the EDA bit was cleared to 0. If a repeat area overflow interrupt is generated, the EDA bit is cleared to 0 and transfer is terminated. When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another bus master during burst transfer. If there is no bus request, burst transfer is executed even if the BGUP bit is set to 1. Figure 8.6 shows examples of the timing in burst mode. Bus cycle CPU CPU EXDMAC EXDMAC EXDMAC CPU CPU CPU cycle not generated Transfer conditions: Auto request mode, BGUP = 0 Bus cycle CPU EXDMAC CPU EXDMAC CPU EXDMAC CPU EXDMAC operates alternately with CPU Transfer conditions: Auto request mode, BGUP = 1 Figure 8.6 Examples of Timing in Burst Mode Rev. 1.00 Sep. 19, 2008 Page 415 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.5 Transfer Modes There are two transfer modes: normal transfer mode and block transfer mode. When the activation source is an external request, either normal transfer mode or block transfer mode can be selected. When the activation source is an auto request, normal transfer mode is used. (1) Normal Transfer Mode In normal transfer mode, transfer of one transfer unit is processed in response to one transfer request. EDTCR functions as a 24-bit transfer counter. The ETEND signal is output only for the last DMA transfer. The EDRAK signal is output each time a transfer request is accepted and transfer processing is started. Figure 8.7 shows examples of DMA transfer timing in normal transfer mode. EXDMA transfer cycle Bus cycle ETEND Transfer conditions: Dual address mode, auto request mode Read Write Last EXDMA transfer cycle Read Write EDREQ EDRAK Bus cycle EDACK Transfer conditions: Single address mode, external request mode EXDMA EXDMA Figure 8.7 Examples of Timing in Normal Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 416 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Block Transfer Mode In block transfer mode, the number of bytes or words specified by the block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256 can be specified. During transfer of a block, transfer requests for other higher-priority channels are held pending. When transfer of one block is completed, the bus is released in the next cycle. When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another bus master during block transfer. Address register values are updated in the same way as in normal mode. There is no function for restoring the initial address register values after each block transfer. The ETEND signal is output for each block transfer in the DMA transfer cycle in which the block ends. The EDRAK signal is output once for one transfer request (for transfer of one block). Caution is required when setting the repeat area overflow interrupt of the repeat area function in block transfer mode. See section 8.4.6, Repeat Area Function, for details. Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA Transfer, for details. Figure 8.8 shows an example of DMA transfer timing in block transfer mode. EDREQ EDRAK One-block transfer cycle Bus cycle CPU CPU CPU EXDMAC EXDMAC EXDMAC CPU CPU cycle not generated ETEND Transfer conditions: * Single address mode * BGUP = 0 * Block size (EDTCR[23:16]) = 3 Figure 8.8 Example of Timing in Block Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 417 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.6 Repeat Area Function The EXDMAC has a function for designating a repeat area for source addresses and/or destination addresses. When a repeat area is designated, the address register values repeat within the range specified as the repeat area. Normally, when a ring buffer is involved in a transfer, an operation is required to restore the address register value to the buffer start address each time the address register value is the last address in the buffer (i.e. when ring buffer address overflow occurs), but if the repeat area function is used, the operation that restores the address register value to the buffer start address is performed automatically within the EXDMAC. The repeat area function can be set independently for the source address register and the destination address register. The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat area can be specified independently. When the address register value is the last address in the repeat area and repeat area overflow occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU. If the SARIE bit in EDACR is set to 1, when the source address register overflows the repeat area, the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1 in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to the destination address register. Rev. 1.00 Sep. 19, 2008 Page 418 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) If the EDA bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 8.9 illustrates the operation of the repeat area function. When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3) External memory : H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 : H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 Repeat area overflow interrupt can be requested Repeated Range of EDSAR values Figure 8.9 Example of Repeat Area Function Operation Caution is required when the repeat area overflow interrupt function is used together with block transfer mode. If transfer is always terminated when repeat area overflow occurs in block transfer mode, the block size must be a power of two, or alternatively, the address register value must be set so that the end of a block coincides with the end of the repeat area range. Rev. 1.00 Sep. 19, 2008 Page 419 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure 8.10 shows an example in which block transfer mode is used together with the repeat area function. When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3), and block size of 5 (EDTCR[23-16] = 5) is set in block transfer mode External memory : H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 : H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 Block transfer in progress H'240000 H'240001 Interrupt requested Range of EDSAR values First block transfer Second block transfer Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 420 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.7 Registers during DMA Transfer Operation EXDMAC register values are updated as DMA transfer processing is performed. The updated values depend on various settings and the transfer status. The following registers and bits are updated: EDSAR, EDDAR, EDTCR, and bits EDA, BEF, and IRF in EDMDR, (1) EXDMA Source Address Register (EDSAR) When the EDSAR address is accessed as the transfer source, after the EDSAR value is output, EDSAR is updated with the address to be accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented when SAT1 = 1 and SAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred. When the DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by 2. When a repeat area setting is made, the operation conforms to that setting. The upper part of the address set for the repeat area function is fixed, and is not affected by address updating. When EDSAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output. Do not write to EDSAR for a channel on which a transfer operation is in progress. (2) EXDMA Destination Address Register (EDDAR) When the EDDAR address is accessed as the transfer destination, after the EDDAR value is output, EDDAR is updated with the address to be accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The address is fixed when DAT1 = 0, incremented when DAT1 = 1 and DAT0 = 0, and decremented when DAT1 = 1 and DAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred. When the DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by 2. When a repeat area setting is made, the operation conforms to that setting. The upper part of the address set for the repeat area function is fixed, and is not affected by address updating. Rev. 1.00 Sep. 19, 2008 Page 421 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) When EDDAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output. Do not write to EDDAR for a channel on which a transfer operation is in progress. (3) EXDMA Transfer Count Register (EDTCR) When a DMA transfer is performed, the value in EDTCR is decremented by 1. However, when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change. EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to specify the block size, and their value does not change. The lower 16 bits, EDTCR[15:0], function as a transfer counter, the value of which is decremented by 1 when a DMA transfer is performed. However, when the EDTCR[15:0] value is 0, transfers are not counted and the EDTCR[15:0] value does not change. In normal transfer mode, all of the lower 24 bits of EDTCR may change, so when EDTCR is read by the CPU during DMA transfer, a longword access must be used. During a transfer operation, EDTCR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDTCR value to ensure that the correct value is output. In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word access. Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is contention between an address update associated with DMA transfer and a write by the CPU, the CPU write has priority. In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value) by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated. Transfer does not end if the CPU writes 0 to EDTCR. Rev. 1.00 Sep. 19, 2008 Page 422 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode. EDTCR in normal transfer mode Before update 23 EDTCR 23 EDTCR 1 to H'FFFFFF 0 0 -1 23 0 to H'FFFFFE 0 Fixed 23 0 0 After update 0 EDTCR in block transfer mode Before update 23 16 15 Block 0 size 23 16 15 Block 1 to H'FFFF size After update 23 16 15 Block 0 size 23 16 15 Block 0 to H'FFFE size 0 Fixed 0 EDTCR 0 -1 0 EDTCR Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and Block Transfer Mode (4) EDA Bit in EDMDR The EDA bit in EDMDR is written to by the CPU to control enabling and disabling of data transfer, but may be cleared automatically by the EXDMAC due to the DMA transfer status. There are also periods during transfer when a 0-write to the EDA bit by the CPU is not immediately effective. Conditions for EDA bit clearing by the EXDMAC include the following: * * * * * * When the EDTCR value changes from 1 to 0, and transfer ends When a repeat area overflow interrupt is requested, and transfer ends When an NMI interrupt is generated, and transfer halts A reset Hardware standby mode When 0 is written to the EDA bit, and transfer halts Rev. 1.00 Sep. 19, 2008 Page 423 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA transfer period. In block transfer mode, since a block-size transfer is carried out without interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current block-size transfer. In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0 is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until the end of the last DMA cycle. Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that the EDA bit has been cleared to 0. Figure 8.12 shows the procedure for changing register settings in an operating channel. Changing register settings in operating channel Write 0 to EDA bit [1] [1] Write 0 to the EDA bit in EDMDR. [2] Read the EDA bit. [3] Confirm that EDA = 0. If EDA = 1, this indicates that DMA transfer is in progress. [4] Write the required set values to the registers. Read EDA bit [2] EDA bit = 0? Yes Change register settings Register setting changes completed [3] No [4] Figure 8.12 Procedure for Changing Register Settings in Operating Channel Rev. 1.00 Sep. 19, 2008 Page 424 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (5) BEF Bit in EDMDR In block transfer mode, the specified number of transfers (equivalent to the block size) is performed in response to a single transfer request. To ensure that the correct number of transfers is carried out, a block-size transfer is always executed, except in the event of a reset, transition to standby mode, or generation of an NMI interrupt. If an NMI interrupt is generated during block transfer, operation is halted midway through a block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1. (6) IRF Bit in EDMDR The IRF bit in EDMDR is set to 1 when an interrupt request source occurs. If the EDIE bit in EDMDR is 1 at this time, an interrupt is requested. The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer ends following the end of the DMA transfer bus cycle in which the source generating the interrupt occurred. If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is automatically cleared to 0 and the interrupt request is cleared. For details on interrupts, see section 8.5, Interrupt Sources. 8.4.8 Channel Priority Order The priority order of the EXDMAC channels is: channel 2 > channel 3. Table 8.3 shows the EXDMAC channel priority order. Table 8.3 Channel Channel 2 Channel 3 EXDMAC Channel Priority Order Priority High Low If transfer requests occur simultaneously for a number of channels, the highest-priority channel according to the priority order in table 8.3 is selected for transfer. Rev. 1.00 Sep. 19, 2008 Page 425 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (1) Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode) If transfer requests for different channels are issued during a transfer operation, the highestpriority channel (excluding the currently transferring channel) is selected. The selected channel begins transfer after the currently transferring channel releases the bus. If there is a bus request from a bus master other than the EXDMAC at this time, a cycle for the other bus master is initiated. If there is no other bus request, the bus is released for one cycle. Channel switching does not take place during a burst transfer or a block transfer of a single block. Figure 8.13 shows a case in which transfer requests for channels 2 and 3 are issued simultaneously. The example shown in the figure illustrates the handling of external requests in the cycle steal mode. Channel 2 transfer Channel 3 transfer Address bus Channel 2 Bus release Channel 3 Bus release EXDMA control Idle Channel 2 Channel 3 Channel 2 Request cleared Channel 3 Request Selected held Request cleared Figure 8.13 Example of Channel Priority Timing (2) Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode If transfer requests for different channels are issued during a transfer in auto request cycle steal mode, the operation depends on the channel priority. If the channel that made the transfer request is of higher priority than the channel currently performing transfer, the channel that made the transfer request is selected. If the channel that made the transfer request is of lower priority than the channel currently performing transfer, that channel's transfer request is held pending, and the currently transferring channel remains selected. Rev. 1.00 Sep. 19, 2008 Page 426 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) The selected channel begins transfer after the currently transferring channel releases the bus. If there is a bus request from a bus master other than the EXDMAC at this time, a cycle for the other bus master is initiated. If there is no other bus request, the bus is released for one cycle. Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode. Conditions (1) Channel 2: Auto request, cycle steal mode Channel 3: External request, cycle steal mode, low level activation Bus Channel 2 * Channel 2 * Channel 2 * Channel 3 * Channel 3 * Channel 2 EDA bit Channel 3/ EDREQ3 pin Conditions (2) Channel 2: External request, cycle steal mode, low level activation Channel 3: Auto request, cycle steal mode Bus Channel 3 * Channel 3 * Channel 2 * Channel 3 * Channel 2 * Channel 2 Channel 2/ EDREQ2 pin Channel 2 EDA bit Conditions (3) Channel 2: Auto request, cycle steal mode Channel 3: Auto request, cycle steal mode Bus Channel 3 * Channel 3 * Channel 2 * Channel 2 * Channel 3 * Channel 2 EDA bit Channel 3 EDA bit *: Bus release Figure 8.14 Examples of Channel Priority Timing Rev. 1.00 Sep. 19, 2008 Page 427 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.9 (1) EXDMAC Bus Cycles (Dual Address Mode) Normal Transfer Mode (Cycle Steal Mode) Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released. While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated. DMA read DMA write Address bus RD HWR LWR ETEND Bus release Bus release Bus release Last transfer cycle DMA read DMA write DMA read DMA write Bus release Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer Rev. 1.00 Sep. 19, 2008 Page 428 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Normal Transfer Mode (Burst Mode) Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. In burst mode, one-byte or one-word transfers are executed continuously until transfer ends. Once burst transfer starts, requests from other channels, even of higher priority, are held pending until transfer ends. DMA read DMA write DMA read DMA write DMA read DMA write Address bus RD HWR LWR ETEND Bus release Last transfer cycle Burst transfer Bus release Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer If an NMI interrupt is generated while a channel designated for burst transfer is enabled for transfer, the EDA bit is cleared and transfer is disabled. If a block transfer has already been initiated within the EXDMAC, the bus is released on completion of the currently executing byte or word transfer, and burst transfer is aborted. If the last transfer cycle in burst transfer has been initiated within the EXDMAC, transfer is executed to the end even if the EDA bit is cleared. Rev. 1.00 Sep. 19, 2008 Page 429 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (3) Block Transfer Mode (Cycle Steal Mode) Figure 8.17 shows an example of transfer when ETEND output is enabled, and word-size, block transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. One block is transferred in response to one transfer request, and after the transfer, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. DMA read Address bus RD HWR LWR ETEND Bus release Block transfer Bus release Last block transfer Bus release DMA write DMA read DMA write DMA read DMA write DMA read DMA write Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer Rev. 1.00 Sep. 19, 2008 Page 430 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (4) EDREQ Pin Falling Edge Activation Timing Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge. Bus release EDREQ Address bus DMA control Channel Idle Request [1] [2] Transfer source Transfer destination Transfer source Transfer destination DMA read DMA write Bus release DMA read DMA write Bus release Read Write Idle Request [4] Acceptance resumed [5] Read Write Idle Request clearance period Request clearance period Minimum 3 cycles [3] Minimum 3 cycles [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle start; EDREQ pin high level sampling is started at rise of . When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Figure 8.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling edge. Rev. 1.00 Sep. 19, 2008 Page 431 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) One block transfer Bus release EDREQ Address bus DMA control Idle Channel Request [1] [2] Transfer source Transfer destination One block transfer Bus release DMA read DMA write Bus release DMA read DMA write Transfer source Transfer destination Read Write Idle Request [4] Acceptance resumed [5] Read Write Idle Request clearance period Request clearance period Minimum 3 cycles [3] Minimum 3 cycles [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle start; EDREQ pin high level sampling is started at rise of . When EDREQ pin high level has been sampled, acceptance is resumed after completion of dead cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 1.00 Sep. 19, 2008 Page 432 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (5) EDREQ Pin Low Level Activation Timing Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level. Bus release EDREQ Address bus DMA control Idle Channel Transfer source Transfer destination Transfer source Transfer destination DMA read DMA write Bus release DMA read DMA write Bus release Read Write Idle Read Write Idle Request clearance period Request Minimum 3 cycles [1] [2] [3] Request clearance period Request Minimum 3 cycles [4] [5] [6] [7] Acceptance resumed Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle is started. Acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Figure 8.21 shows an example of block transfer mode transfer activated by the EDREQ pin low level. Rev. 1.00 Sep. 19, 2008 Page 433 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) One block transfer Bus release EDREQ Address bus DMA control Channel Idle Request [1] [2] Transfer source Transfer destination One block transfer Bus release DMA read DMA write Bus release DMA read DMA write Transfer source Transfer destination Read Write Idle Request [4] Acceptance resumed [5] Read Write Idle Request clearance period Request clearance period Minimum 3 cycles [3] Minimum 3 cycles [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle is started. Acceptance is resumed after completion of dead cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 1.00 Sep. 19, 2008 Page 434 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.10 (1) EXDMAC Bus Cycles (Single Address Mode) Single Address Mode (Read) Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read Address bus RD EDACK ETEND Bus release Bus release Bus release Bus release Bus release Last transfer cycle DMA read DMA read DMA read Figure 8.22 Example of Single Address Mode (Byte Read) Transfer Figure 8.23 shows an example of transfer when ETEND output is enabled, and word-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read Address bus RD EDACK ETEND Bus release Bus release Bus release Last transfer cycle DMA read DMA read Bus release Figure 8.23 Example of Single Address Mode (Word Read) Transfer Rev. 1.00 Sep. 19, 2008 Page 435 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. (2) Single Address Mode (Write) Figure 8.24 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Bus release Last Bus release transfer cycle DMA write DMA write DMA write Figure 8.24 Example of Single Address Mode (Byte Write) Transfer Rev. 1.00 Sep. 19, 2008 Page 436 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Last transfer cycle DMA write DMA write Bus release Figure 8.25 Example of Single Address Mode (Word Write) Transfer After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Rev. 1.00 Sep. 19, 2008 Page 437 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (3) EDREQ Pin Falling Edge Activation Timing Figure 8.26 shows an example of single address mode transfer activated by the EDREQ pin falling edge. Bus release EDREQ Address bus EDACK DMA control Channel Idle Request Single Transfer source/ destination Transfer source/ destination DMA single Bus release DMA single Bus release Idle Request Single Idle Request clearance period Request clearance period Minimum 3 cycles [1] [2] [3] Minimum 3 cycles [4] Acceptance resumed [5] [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle start; EDREQ pin high level sampling is started at rise of . When EDREQ pin high level has been sampled, acceptance is resumed after completion of single cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.26 Example of Single Address Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA single cycle, acceptance resumes after the end of the single cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 1.00 Sep. 19, 2008 Page 438 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (4) EDREQ Pin Low Level Activation Timing Figure 8.27 shows an example of single address mode transfer activated by the EDREQ pin low level. Bus release EDREQ Address bus EDACK DMA control Channel Idle Request Single Transfer source/ destination Transfer source/ destination DMA single Bus release DMA single Bus release Idle Request Single Idle Request clearance period Request clearance period Minimum 3 cycles [1] [2] [3] Minimum 3 cycles [4] Acceptance resumed [5] [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle is started. Acceptance is resumed after completion of single cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.27 Example of Single Address Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the single cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 1.00 Sep. 19, 2008 Page 439 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.11 (1) Examples of Operation Timing in Each Mode Auto Request/Cycle Steal Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one-cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer. If there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. Transfer on the original channel is resumed on completion of the higher-priority channel transfer. Figures 8.28 to 8.30 show operation timing examples for various conditions. pin 3 cycles EXDMA read EXDMA write Bus release CPU operation EDA = 1 write Internal bus space cycles 1 cycle EXDMA read EXDMA write Bus release Last transfer cycle EXDMA read EXDMA write Bus cycle Bus release ETEND EDA bit 0 1 0 Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode) Rev. 1.00 Sep. 19, 2008 Page 440 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) pin 1 bus cycle CPU cycle EXDMA single transfer cycle CPU cycle EXDMA single transfer cycle CPU cycle Last transfer cycle EXDMA single transfer cycle CPU cycle Bus cycle CPU operation External space External space External space External space EDACK ETEND Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode) pin 1 cycle EXDMA single cycle Bus release Current channel EDACK EXDMA single cycle Bus release 1 cycle EXDMA single cycle Bus release 1 cycle EXDMA single cycle Bus release Bus release Bus cycle Higher-priority channel EXDMA cycle Other channel transfer request (EDREQ) Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) Rev. 1.00 Sep. 19, 2008 Page 441 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (2) Auto Request/Burst Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another bus master. Transfer requests for other channels are held pending until the end of transfer on the current channel. Figures 8.31 to 8.34 show operation timing examples for various conditions. pin Last transfer cycle Bus cycle CPU cycle CPU cycle EXDMA read EXDMA write EXDMA read EXDMA write Repeated EXDMA read EXDMA write CPU cycle CPU operation External space External space External space ETEND EDA bit 1 0 Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP = 0) Rev. 1.00 Sep. 19, 2008 Page 442 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) pin 1 bus cycle EXDMA read EXDMA write EXDMA read EXDMA write 1 bus cycle EXDMA read EXDMA write Bus cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU operation External space External space External space External space Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP = 1) pin 1 bus cycle Last transfer cycle Bus cycle EXDMA EXDMA EXDMA EXDMA EXDMA CPU cycle CPU cycle single cycle single cycle CPU cycle single cycle single cycle CPU cycle single cycle CPU cycle CPU operation External space External space External space External space External space EDACK ETEND Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/BGUP = 1) Rev. 1.00 Sep. 19, 2008 Page 443 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) pin Last transfer cycle Bus cycle Bus release EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Bus release Original channel EDACK 1 cycle Bus release Other channel EXDMA cycle Original channel ETEND Other channel transfer request (EDREQ) Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) Rev. 1.00 Sep. 19, 2008 Page 444 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (3) External Request/Cycle Steal Mode/Normal Transfer Mode In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The next transfer request is accepted after the end of a one-transferunit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA cycle. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next EXDMA cycle. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.35 to 8.38 show operation timing examples for various conditions. pin EDREQ EDRAK 3 cycles Bus cycle Bus release EXDMA read EXDMA write Bus release Last transfer cycle EXDMA read EXDMA write Bus release ETEND EDA bit 1 0 Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing) Rev. 1.00 Sep. 19, 2008 Page 445 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) pin EDREQ EDRAK 2 bus cycles Bus cycle CPU cycle CPU cycle CPU cycle EXDMA single transfer cycle CPU cycle CPU cycle Last transfer cycle EXDMA single transfer cycle CPU cycle CPU operation External space External space External space External space External space External space EDACK ETEND Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing) pin EDREQ EDRAK EDREQ acceptance internal processing state Bus cycle Edge confirmation Start of transfer processing Start of high level sensing Edge confirmation Start of transfer processing Start of high level sensing Edge confirmation Start of transfer processing Start of high level sensing Bus release EXDMA single transfer cycle Bus release EXDMA single transfer cycle Bus release EXDMA single transfer cycle EDACK Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing) Rev. 1.00 Sep. 19, 2008 Page 446 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) pin Original channel EDREQ Original channel EDRAK 3 cycles Bus cycle EXDMA transfer cycle Bus release EXDMA read EXDMA write Bus release Other channel EDREQ Other channel EDRAK 1 cycle Other channel transfer cycle Bus release 1 cycle EXDMA read EXDMA write Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention with Another Channel/Dual Address Mode/Low Level Sensing (4) External Request/Cycle Steal Mode/Block Transfer Mode In block transfer mode, transfer of one block is performed continuously in the same way as in burst mode. The timing of the start of the next block transfer is the same as in normal transfer mode. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next block transfer. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.39 to 8.44 show operation timing examples for various conditions. Rev. 1.00 Sep. 19, 2008 Page 447 of 1270 REJ09B0466-0100 REJ09B0466-0100 1-block-size transfer period Last transfer in block EXDMA read Repeated EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write 3 cycles Bus release EXDMA read EXDMA write Last block Last transfer cycle EXDMA read Repeated EXDMA write Bus release 0 Section 8 EXDMA Controller (EXDMAC) pin Rev. 1.00 Sep. 19, 2008 Page 448 of 1270 EDREQ EDRAK Bus cycle Bus release ETEND Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0) EDA bit 1 pin EDREQ EDRAK 1-block-size transfer period Last transfer in block EXDMA single transfer cycle Repeated EXDMA single transfer cycle EXDMA single transfer cycle 3 cycles Bus release EXDMA single transfer cycle Last block Last transfer cycle EXDMA single transfer cycle Repeated Bus release Bus cycle Bus release EDACK Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 449 of 1270 ETEND REJ09B0466-0100 REJ09B0466-0100 1-block-size transfer period Last transfer in block 2 bus cycles CPU cycle CPU cycle EXDMA single transfer cycle CPU cycle Repeated External space External space External space External space External space CPU cycle EXDMA single transfer cycle EXDMA single transfer cycle 1-block-size transfer period Last transfer in block EXDMA single transfer cycle Repeated CPU cycle pin Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 450 of 1270 EDREQ EDRAK Bus cycle CPU cycle CPU operation External space EDACK Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) ETEND pin EDREQ EDRAK 1-block-size transfer period 1 bus cycle CPU cycle EXDMA read EXDMA write EXDMA read EXDMA write CPU cycle CPU cycle CPU cycle 1 bus cycle EXDMA read Repeated External space External space External space External space External space External space External space 1 bus cycle CPU cycle Last transfer in block EXDMA read EXDMA write CPU cycle CPU cycle Bus cycle CPU cycle CPU operation External space Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 451 of 1270 ETEND REJ09B0466-0100 REJ09B0466-0100 1-block-size transfer period 1 bus cycle CPU cycle EXDMA EXDMA transfer cycle transfer cycle EXDMA EXDMA transfer cycle transfer cycle pin Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 452 of 1270 1 bus cycle 1 bus cycle Last transfer in block CPU cycle EXDMA transfer cycle EXDMA EXDMA transfer cycle transfer cycle EDREQ EDRAK Bus cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle Repeated CPU cycle CPU operation External space External space External space External space External space External space External space External space EDACK Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) ETEND pin EDREQ EDRAK 1-block-size transfer period Last transfer in block EXDMA read Repeated Bus release EXDMA write EXDMA read EXDMA write Other channel EXDMA cycle EXDMA read Bus release EXDMA write 1-block-size transfer period Last transfer in block EXDMA read Repeated EXDMA write Bus cycle Bus release ETEND Other channel EDREQ Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing) Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 453 of 1270 Other channel EDRAK REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.4.12 Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has ended. (1) Transfer End by 1 0 Transition of EDTCR When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0. If the TCEIE bit in EDMDR is set at this time, a transfer end interrupt request is generated by the transfer counter and the IRF bit in EDMDR is set to 1. In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in EDTCR changes from 1 to 0. DMA transfer does not end if the EDTCR value has been 0 since before the start of transfer. (2) Transfer End by Repeat Area Overflow Interrupt If an address overflows the repeat area when a repeat area specification has been made and repeat interrupts have been enabled (with the SARIE or DARIE bit in EDACR), a repeat area overflow interrupt is requested. DMA transfer ends, the EDA bit in EDMDR is cleared to 0, and the IRF bit in EDMDR is set to 1. In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the following write cycle processing is still executed. In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block, transfer continues to the end of the block. Transfer end by means of a repeat area overflow interrupt occurs between block-size transfers. (3) Transfer End by 0-Write to EDA Bit in EDMDR When 0 is written to the EDA bit in EDMDR by the CPU, etc., transfer ends after completion of the DMA cycle in which transfer is in progress or a transfer request was accepted. In block transfer mode, DMA transfer halts after completion of one-block-size transfer. The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that point, the value of the EDA bit will be read as 1. Rev. 1.00 Sep. 19, 2008 Page 454 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (4) Transfer Abort by NMI Interrupt DMA transfer is aborted when an NMI interrupt is generated. The EDA bit is cleared to 0 in all channels. In external request mode, DMA transfer is performed for all transfer requests for which EDRAK has been output. In dual address mode, processing is executed for the write cycle following the read cycle. In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the block transfer was not carried out normally. When transfer is aborted, register values are retained, and as the address registers indicate the next transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit is 1 in EDMDR, transfer can be resumed from midway through a block. (5) Hardware Standby Mode and Reset Input The EXDMAC is initialized in hardware standby mode and by a reset. DMA transfer is not guaranteed in these cases. 8.4.13 Relationship between EXDMAC and Other Bus Masters The read and write operations in a DMA transfer cycle are indivisible, and a refresh cycle, external bus release cycle, or internal bus master (CPU, DTC, or DMAC) external space access cycle never occurs between the two. When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or external bus release state may be inserted after the write cycle. As the internal bus masters are of lower priority than the EXDMAC, external space accesses by internal bus masters are not executed until the EXDMAC releases the bus. The EXDMAC releases the bus in the following cases: 1. 2. 3. 4. 5. When DMA transfer is performed in cycle steal mode When switching to a different channel When transfer ends in burst transfer mode When transfer of one block ends in block transfer mode When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1 (however, the bus is not released between read and write cycles) Rev. 1.00 Sep. 19, 2008 Page 455 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.5 Interrupt Sources EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area overflow interrupts. Table 8.4 shows the interrupt sources and their priority order. Table 8.4 Interrupt EXDMTEND2 Interrupt Sources and Priority Order Interrupt source Transfer end indicated by channel 2 transfer counter Channel 2 source address repeat area overflow Channel 2 destination address repeat area overflow Interrupt Priority High EXDMTEND3 Transfer end indicated by channel 3 transfer counter Channel 3 source address repeat area overflow Channel 3 destination address repeat area overflow Low Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant channel, and can be sent to the interrupt controller independently. The relative priority order of the channels is determined by the interrupt controller (see table 8.4). Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR. IRF bit Transfer end interrupt EDIE bit Figure 8.45 Transfer End Interrupt Logic Interrupt source settings are made individually with the interrupt enable bits in the registers for the relevant channels. The transfer counter's transfer end interrupt is enabled or disabled by means of the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding interrupt enable bit is set to 1, the IRF bit in EDMDR is set to 1. The IRF bit is set by all interrupt sources indiscriminately. Rev. 1.00 Sep. 19, 2008 Page 456 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the interrupt handling routine, or by re-setting the transfer counter and address registers and then setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46. Transfer end interrupt exception handling routine Transfer continuation processing Change register settings Write 1 to EDA bit End of interrupt handling routine (RTE instruction execution) [1] [2] Transfer restart after end of interrupt handling routine Clear IRF bit to 0 End of interrupt handling routine Change register settings [4] [5] [3] [6] Write 1 to EDA bit End of transfer restart processing [7] End of transfer restart processing [1] Write set values to the registers (transfer counter, address registers, etc.). [2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the EDA bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared. [3] The interrupt handling routine is ended with an RTE instruction, etc. [4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0. [5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is cleared. [6] Write set values to the registers (transfer counter, address registers, etc.). [7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer End Interrupt Occurred Rev. 1.00 Sep. 19, 2008 Page 457 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) 8.6 (1) Usage Notes EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. (2) Module Stop State When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC enters the module stop state. However, 1 cannot be written to the MSTP14 bit when any of the EXDMAC's channels is enabled for transfer, or when an interrupt is being requested. Before setting the MSTP14 bit, first clear the EDA bit in EDMDR to 0, then clear the IRF or EDIE bit in EDMDR to 0. When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following EXDMAC register settings remain valid in the module stop state, and so should be changed, if necessary, before making the module stop transition. * ETENDE = 1 in EDMDR (ETEND pin enable) * EDRAKE = 1 in EDMDR (EDRAK pin enable) * AMS = 1 in EDMDR (EDACK pin enable) (3) EDREQ Pin Falling Edge Activation Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal operations, as indicated below. [1] Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2]. [2] Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3]. [3] Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1]. After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used for the initial activation after transfer is enabled. Rev. 1.00 Sep. 19, 2008 Page 458 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) (4) Activation Source Acceptance At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transferenabled state. When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the EDREQ pin from the previous end of transfer, etc. (5) Enabling Interrupt Requests when IRF = 1 in EDMDR When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be requested since EDIE = 1 and IRF = 1. To prevent the occurrence of an erroneous interrupt request when transfer starts, ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1. (6) ETEND Pin and CBR Refresh Cycle If the last EXDMAC transfer cycle and a CBR refresh cycle occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, ETEND may also go low in this case for the refresh cycle. Rev. 1.00 Sep. 19, 2008 Page 459 of 1270 REJ09B0466-0100 Section 8 EXDMA Controller (EXDMAC) Rev. 1.00 Sep. 19, 2008 Page 460 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. 9.1 Features * Transfer possible over any number of channels * Three transfer modes 1. Normal mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. From 1 to 65,536 transfers can be specified. 2. Repeat mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and transfer is repeated. 3. Block transfer mode One operation transfers one block of data. The block size is 1 to 256 bytes or words. From 1 to 65,536 transfers can be specified. Either the transfer source or the transfer destination is designated as a block area. * One activation source can trigger a number of data transfers (chain transfer) * Direct specification of 16-Mbyte address space possible * Activation by software is possible * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC * Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 461 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 Kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Internal address bus Interrupt controller DTC On-chip RAM DTC activation request CPU interrupt request Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERI DTVECR DTCCR : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to I : DTC vector register : DTC control register Figure 9.1 Block Diagram of DTC Rev. 1.00 Sep. 19, 2008 Page 462 of 1270 REJ09B0466-0100 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTCERA to DTCERI DTVECR DTCCR Section 9 Data Transfer Controller (DTC) 9.2 Register Descriptions DTC has the following registers. * * * * * * DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set of register information that is stored in an on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to the RAM. * DTC enable registers A to I (DTCERA to DTCERI) * DTC vector register (DTVECR) * DTC control register (DTCCR) 9.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit 7 6 Bit Name SM1 SM0 Initial Value Undefined Undefined R/W -- -- Description Source Address Mode 1 and 0 These bits specify an SAR operation after a data transfer. 0x: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Rev. 1.00 Sep. 19, 2008 Page 463 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Bit 5 4 Bit Name DM1 DM0 Initial Value Undefined Undefined R/W -- -- Description Destination Address Mode 1 and 0 These bits specify a DAR operation after a data transfer. 0x: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 3 2 MD1 MD0 Undefined Undefined -- -- DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined -- DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area 0 Sz Undefined -- DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Legend: x : Don't care Rev. 1.00 Sep. 19, 2008 Page 464 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit 7 Bit Name CHNE Initial Value Undefined R/W -- Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 9.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTCER is not performed. 6 DISEL Undefined -- DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time after a data transfer ends. When this bit is set to 0, a CPU interrupt request is generated at the time when the specified number of data transfer ends. 5 CHNS Undefined -- DTC Chain Transfer Select Specifies the chain transfer condition. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0 4 to 0 -- Undefined -- Reserved These bits have no effect on DTC operation, and should always be written with 0. 9.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 9.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev. 1.00 Sep. 19, 2008 Page 465 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 9.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. The CRB is not available in normal and repeat modes. Rev. 1.00 Sep. 19, 2008 Page 466 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.2.7 DTC Enable Registers A to I (DTCERA to DTCERI) DTCER which is comprised of registers, DTCERA to DTCERI, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 9.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Bit 7 6 5 4 3 2 1 0 Bit Name DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. [Clearing conditions] * When the DISEL bit is 1 and the data transfer has ended * When the specified number of transfers have ended These bits are not automatically cleared when the DISEL bit is 0 and the specified number of transfers have not ended * When 0 is written to DTCE after reading DTCE = 1 9.2.8 DTC Vector Register (DTVECR) DTVECR sets a vector number for the software activation interrupt. Bit 7 6 5 4 3 2 1 0 Bit Name DTVEC7 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Software Activation Vectors 7 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC7 to DTVEC0 = H'10, the vector address is H'0420. These bits can be written to only when the SWDTE bit is 0. Rev. 1.00 Sep. 19, 2008 Page 467 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.2.9 DTC Control Register (DTCCR) DTCCR enables or disables DTC activation by software. Bit 7 Bit Name SWDTE Initial Value 0 R/W R/W Description DTC Software Activation Enable Setting this bit to 1 activates the DTC. Only 1 can be written to this bit. [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. When the DISEL bit is 1 and data transfer has ended or when the specified number of transfers have ended, this bit will not be cleared. 6 to 0 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 468 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR or DTCCR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0. When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Table 9.1 shows a relationship between activation sources and DTCER clear conditions. Figure 9.2 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Table 9.1 Relationship between Activation Sources and DTCER Clearing DISEL = 0 and Specified Number of Transfers Has Not Ended SWDTE bit is cleared to 0 * * DISEL = 1 or Specified Number of Transfers Has Ended * * Activation by an interrupt Corresponding DTCER bit remains set to 1. Activation source flag is cleared to 0. * * * SWDTE bit remains set to 1 Interrupt request to CPU Corresponding DTCER bit is cleared to 0. Activation source flag remains set to 1. Interrupt that became the activation source is requested to the CPU. Activation Source Activation by software Rev. 1.00 Sep. 19, 2008 Page 469 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Source flag cleared Clear controller Clear DTCER Select Clear request IRQ interrupt Interrupt request Selection circuit On-chip peripheral modules DTC DTVECR DTCCR Interrupt controller Interrupt mask CPU Figure 9.2 Block Diagram of DTC Activation Source Control Rev. 1.00 Sep. 19, 2008 Page 470 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF). Register information should be located at the address that is multiple of four within the range. Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 9.3 and the register information start address should be located at the corresponding vector address to the activation source. Figure 9.4 shows correspondences between the DTC vector address and register information. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[7:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the register information start address. Note: * Not available in this LSI. Lower addresses 0 Start address of register information MRA MRB CRA Chain transfer MRA MRB CRA Four bytes SAR DAR CRB Register information for second transfer in case of chain transfer 1 2 SAR DAR CRB Register information 3 Figure 9.3 Correspondence between DTC Vector Address and Register Information Rev. 1.00 Sep. 19, 2008 Page 471 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) DTC vector address Register information start address Register information Chain transfer Figure 9.4 Correspondence between DTC Vector Address and Register Information Table 9.2 Origin of Activation Source Software External pin Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Activation Source Write to DTVECR IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8* IRQ9* 2 2 Vector Number DTVECR 16 17 18 19 20 21 22 23 24 25 DTC Vector Address H'0400 + (DTVECR[7:0] x 2) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0430 H'0432 H'0434 H'0436 H'0438 H'043A H'043C H'043E H'044C DTCE* -- 1 Priority High DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC6 Low IRQ10* IRQ11* 2 26 17 18 19 30 31 38 2 IRQ12*2 IRQ13* IRQ14* IRQ15* A/D_0 ADI0 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 472 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Origin of Activation Source TPU_0 Activation Source TGI0A TGI0B TGI0C TGI0D Vector Number 40 41 42 43 48 49 52 53 56 57 58 59 64 65 68 69 72 73 76 77 80 81 82 83 89 90 93 94 97 98 DTC Vector Address H'0450 H'0452 H'0454 H'0456 H'0460 H'0462 H'0468 H'046A H'0470 H'0472 H'0474 H'0476 H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0498 H'049A H'04A0 H'04A2 H'04A4 H'04A6 H'04B2 H'04B4 H'04BA H'04BC H'04C2 H'04C4 DTCE* 1 Priority High DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0 DTCEG7 DTCEG6 TPU_1 TGI1A TGI1B TPU_2 TGI2A TGI2B TPU_3 TGI3A TGI3B TGI3C TGI3D TPU_4 TGI4A TGI4B TPU_5 TGI5A TGI5B TMR_0 CMIA0 CMIB0 TMR_1 CMIA1 CMIB1 DMAC DMTEND0A DMTEND0B DMTEND1A DMTEND1B SCI_0 RXI0 TXI0 SCI_1 RXI1 TXI1 SCI_2 RXI2 TXI2 Low Rev. 1.00 Sep. 19, 2008 Page 473 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Origin of Activation Source SCI_3 Activation Source RXI3 TXI3 Vector Number 101 102 105 106 112 120 121 122 123 125 126 129 130 133 134 135 136 138 139 142 143 DTC Vector Address H'04CA H'04CC H'04D2 H'04D4 H'04E0 H'04F0 H'04F2 H'04F4 H'04F6 H'04FA H'04FC H'0502 H'0504 H'050A H'050C H'050E H'0510 H'0514 H'0516 H'051C H'051E DTCE* 1 Priority High DTCEF5 DTCEF4 DTCEG3 DTCEG2 DTCEG1 DTCEG0 DTCEH7 DTCEH6 DTCEH5 DTCEH4 DTCEH3 DTCEH2 DTCEH1 DTCEH0 DTCEI7 DTCEI6 DTCEI5 DTCEI4 DTCEI3 DTCEI2 DTCEI1 SCI_4 RXI4 TXI4 A/D_1 TPU_6 ADI1 TGI6A TGI6B TGI6C TGI6D TPU_7 TGI7A TGI7B TPU_8 TGI8A TGI8B TPU_9 TGI9A TGI9B TGI9C TGI9D TPU_10 TGI10A TGI10B TPU_11 TGI11A TGI11B Low Notes: 1. DTCE bits with no corresponding interrupt are reserved, and 0 should be written to. When clearing the software standby state or all-module-clocks-stop mode with an interrupt, write 0 to the corresponding DTCE bit. 2. Not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 474 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5 Operation The DTC stores register information in the on-chip RAM. When activated, the DTC reads register information that is already stored in the on-chip RAM and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to the onchip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer data over any required number of channels. There are three transfer modes: normal mode, repeat mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). A setting can also be made to have chain transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be performed by the DTC itself. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Figure 9.5 shows a flowchart of DTC operation, and table 9.3 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted). Rev. 1.00 Sep. 19, 2008 Page 475 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? No Yes CHNS = 0? Yes Transfer counter = 0 or DISEL = 1? No No Yes Transfer counter = 0? No DISEL = 1? Yes No Yes Clear activation flag Clear DTCER End Interrupt exception handling Figure 9.5 Flowchart of DTC Operation Rev. 1.00 Sep. 19, 2008 Page 476 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Table 9.3 Chain Transfer Conditions 1st Transfer 2nd Transfer CR Not 0 0 -- -- CHNE -- -- -- 0 0 0 CHNS -- -- -- -- -- -- -- -- -- -- -- DISEL -- -- -- 0 0 1 -- 0 0 1 -- CR -- -- -- Not 0 0 -- -- Not 0 0 -- -- DTC Transfer Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Interrupt request to CPU CHNE 0 0 0 1 CHNS -- -- -- 0 DISEL 0 0 1 -- 1 1 1 1 0 -- Not 0 0 -- 0 0 0 1 1 1 Not 0 -- Rev. 1.00 Sep. 19, 2008 Page 477 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt can be requested. Table 9.4 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Function in Normal Mode Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used SAR Transfer DAR Figure 9.6 Memory Mapping in Normal Mode Rev. 1.00 Sep. 19, 2008 Page 478 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 9.5 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 9.5 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Function in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 9.7 Memory Mapping in Repeat Mode Rev. 1.00 Sep. 19, 2008 Page 479 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.6 lists the register function in block transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt is requested. Table 9.6 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Function in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds block size Designates block size count Designates transfer count First block SAR or DAR Block area Transfer DAR or SAR Nth block Figure 9.8 Memory Mapping in Block Transfer Mode Rev. 1.00 Sep. 19, 2008 Page 480 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.9 shows the operation of chain transfer. When activated, the DTC reads the register information start address stored at the vector address, and then reads the first register information at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is 1, the next register information, which is located consecutively, is read and transfer is performed. This operation is repeated until the end of data transfer of register information with CHNE = 0. It is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Source Destination Register information CHNE=1 DTC vector address Register information start address Register information CHNE=0 Source Destination Figure 9.9 Operation of Chain Transfer Rev. 1.00 Sep. 19, 2008 Page 481 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 9.5.6 DTC activation request DTC request Data transfer Read Write Operation Timing Vector read Address Transfer information read Transfer information write Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) Rev. 1.00 Sep. 19, 2008 Page 482 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) DTC activation request DTC request Vector read Address Data transfer Read Write Read Write Transfer information read Transfer information write Figure 9.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) DTC activation request DTC request Vector read Address Read Write Read Write Data transfer Data transfer Transfer information read Transfer information write Transfer information read Transfer information write Figure 9.12 DTC Operation Timing (Example of Chain Transfer) 9.5.7 Number of DTC Execution States Table 9.7 lists execution status for a single DTC data transfer, and table 9.8 shows the number of states required for each execution status. Rev. 1.00 Sep. 19, 2008 Page 483 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Table 9.7 DTC Execution Status Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer Legend: N: Block size (initial setting of CRAH and CRAL) Table 9.8 Number of States Required for Each Execution Status OnChip RAM 32 1 SI -- 1 1 1 1 1 OnChip On-Chip I/O ROM Registers 16 1 1 -- 1 1 1 1 8 2 -- -- 2 4 2 4 16 2 -- -- 2 2 2 2 1 2 4 -- 2 4 2 4 Object to be Accessed Bus width Access states Execution status Vector read External Devices 8 3 6+2m -- 3+m 6+2m 3+m 6+2m 2 2 -- 2 2 2 2 16 3 3+m -- 3+m 3+m 3+m 3+m Register information read/write SJ Byte data read Word data read Byte data write Word data write Internal operation SK SK SL SL SM The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. Rev. 1.00 Sep. 19, 2008 Page 484 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.6 9.6.1 Procedures for Using DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software 9.6.2 The procedure for using the DTC with software activation is as follows: 1. 2. 3. 4. 5. 6. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Check that the SWDTE bit is 0. Write 1 to SWDTE bit and the vector number to DTVECR. Check the vector number written to DTVECR. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. Rev. 1.00 Sep. 19, 2008 Page 485 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.7 9.7.1 Examples of Use of the DTC Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. Rev. 1.00 Sep. 19, 2008 Page 486 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.7.2 Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to NDR of the PPG is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). 1. Perform settings for transfer to NDR of the PPG. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer register information consecutively after the NDR transfer register information. 4. Set the start address of the NDR transfer register information to the DTC vector address. 5. Set the bit corresponding to TGIA in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. Rev. 1.00 Sep. 19, 2008 Page 487 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.7.3 Chain Transfer when Counter = 0 By executing a second data transfer, and performing re-setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-Kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 9.13 shows the chain transfer when the counter value is 0. 1. For the first transfer, set the normal mode for input data. Set fixed transfer source address (G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, an interrupt request is not sent to the CPU. Rev. 1.00 Sep. 19, 2008 Page 488 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 9.13 Chain Transfer when Counter = 0 Rev. 1.00 Sep. 19, 2008 Page 489 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.7.4 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTCCR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'60. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. Rev. 1.00 Sep. 19, 2008 Page 490 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) 9.8 9.8.1 Usage Notes Module Stop Mode Setting DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 24, Power-Down Modes. 9.8.2 On-Chip RAM The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. 9.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. 9.8.4 DMAC Transfer End Interrupt When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer counter and DISEL bit, the DMAC's DTE bit is not subject to DTC control, and the write data has priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer counter reaches 0. 9.8.5 Chain Transfer When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. SCI and high-speed A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the prescribed register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained. Rev. 1.00 Sep. 19, 2008 Page 491 of 1270 REJ09B0466-0100 Section 9 Data Transfer Controller (DTC) Rev. 1.00 Sep. 19, 2008 Page 492 of 1270 REJ09B0466-0100 Section 10 I/O Ports Section 10 I/O Ports Table 10.1 summarizes the port functions of the H8S/2426 Group and H8S/2426R Group. Table 10.2 summarizes the port functions of the H8S/2424 Group. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and a port function control register (PFCR) used to set input/output destination. Before enabling each input/output pins, select the input/output destination by PFCR. The input-only ports do not have a DR or DDR register. Ports A to E have a built-in pull-up MOS function and a pull-up MOS control register (PCR) to control the on/off state of the input pull-up MOS. Ports 1 to 3, 5 to 8, and A to J include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports 1 to 3, 5 (P50 to P53), 6, and 8 can drive a single TTL load and 30-pF capacitive load. Ports A to H can drive a single TTL load and 50-pF capacitive load. All of the I/O ports can drive a Darlington transistor when outputting data. Ports 1 and 2 are Schmitt-triggered inputs. * H8S/2426 Group and H8S/2426R Group Ports 5 (P50 to P52), 8 (P81, P83, and P85), B, and C are Schmitt-triggered inputs when used as TPU inputs. Ports 2, 5, 6, 8, A (PA4 to PA7), F (PF1 and PF2), and H (PH2 and PH3) are Schmitt-triggered inputs when used as IRQ inputs. Ports 3 (P32 to P35) and 5 (P50 and P51) are Schmitt-triggered inputs when used as I2C inputs. Ports 5 (P50 and P51), 6 (P60 to P63), and 8 (P81 and P83) are Schmitt-triggered inputs when used as 8-bit timer inputs. * H8S/2424 Group Ports 5 (P50 to P52), 8 (P81, P83, and P85), B, and C are Schmitt-triggered inputs when used as TPU inputs. Ports 4, 5, 8, and A (PA4 to PA7) are Schmitt-triggered inputs when used as IRQ inputs. Ports 3 (P32 to P35) and 5 (P50 and P51) are Schmitt-triggered inputs when used as I2C inputs. Ports 2 (P20 to P23), 5 (P50 and P51), and 8 (P81 and P83) are Schmitt-triggered inputs when used as 8-bit timer inputs. Rev. 1.00 Sep. 19, 2008 Page 493 of 1270 REJ09B0466-0100 Section 10 I/O Ports Table 10.1 Port Functions of H8S/2426 Group and H8S/2426R Group Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 P17/PO15/TIOCB2/ TCLKD/SCS0-A P16/PO14/TIOCA2/ SSCK0-A Input/ Output Type Schmitt-triggered inputs when used as general input port and TPU inputs. Open-drain output capability. Port 1 General I/O port also functioning as PPG outputs, TPU I/Os, EXDMAC outputs, and SSU I/Os P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A P16/PO14/TIOCA2/EDRAK2/SSCK0-A P15/PO13/TIOCB1/TCLKC/SSI0-A P14/PO12/TIOCA1/SSO0-A P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 Port 2 General I/O port also functioning as PPG outputs, TPU I/Os, interrupt inputs, SCI I/Os, I2C I/Os, A/D converter inputs, and bus control signal I/Os P27/IRQ15-B/PO7/TIOCB5/SCL2 P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A P22/IRQ10-B/PO2-A/TIOCC3-A P21/IRQ9-B/PO1-A/TIOCB3-A P20/IRQ8-B/PO0-A/TIOCA3-A P35/OE-B/CKE-B*1/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD P25/IRQ13-B/PO5-A/ TIOCB4-A Schmitt-triggered inputs when used as general input port, TPU inputs, interrupt inputs, and I2C inputs. Open-drain output capability. 5-V tolerance. Port 3 General I/O port also functioning as SCI I/Os, I2C I/Os, and bus control signal I/Os P35/SCK1/SCL0 Open-drain output capability. Only P32 to P35 are Schmitttriggered inputs when used as I2C inputs. P32 to P35 have 5-V tolerance. Port 4 General I/O port also functioning as A/D converter analog inputs P47/AN7_0 P46/AN6_0 P45/AN5_0 P44/AN4_0 P43/AN3_0 P42/AN2_0 P41/AN1_0 P40/AN0_0 Rev. 1.00 Sep. 19, 2008 Page 494 of 1270 REJ09B0466-0100 Section 10 I/O Ports Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Schmitt-triggered inputs when used as IRQ inputs. Only P50 and P51 are Schmitttriggered inputs when used as I2C inputs. Open-drain output capability. Only P50 to P52 are Schmitttriggered inputs when used as TPU inputs. Only P50 and P51 are Schmitttriggered inputs when used as 8bit timer inputs. P50 and P51 have 5-V tolerance. Schmitt-triggered inputs when used as IRQ inputs. Open-drain output capability. Only P60 to P63 are Schmitttriggered inputs when used as 8bit timer inputs. Port 5 General I/O port also functioning as interrupt inputs, A/D converter inputs, SCI I/Os, PPG outputs, TPU I/Os, TMR I/Os, I2C I/Os, bus control signal I/Os, and JTAG inputs P53/IRQ3-A/ADTRG0-A/TRST*3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/ TMO0-B/SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/ TMCI0-B/RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/ TMRI0-B/TxD2/SDA3 P52/IRQ2-A/PO4-B/ TIOCA4-B/TMO0-B/ SCK2 P51/IRQ1-A/PO2-B/ TIOCC3-B/TMCI0-B/ RxD2/SCL3 P50/IRQ0-A/PO0-B/ TIOCA3-B/TMRI0-B/ TxD2/SDA3 Port 6 General I/O port also functioning as interrupt inputs, TMR I/Os, and DMAC I/Os P65/IRQ13-A/DACK1/TMO1-A P64/IRQ12-A/DACK0/TMO0-A P63/IRQ11-A/TEND1/TMCI1-A P62/IRQ10-A/TEND0/TMCI0-A P61/IRQ9-A/DREQ1/TMRI1-A P60/IRQ8-A/DREQ0/TMRI0-A Port 8 General I/O port also functioning as EXDMAC I/Os, PPG outputs, TPU I/Os, TMR I/Os, SCI I/Os and interrupt inputs P85/IRQ5-B /PO5-B/TIOCB4-B/TMO1-B/SCK3/ EDACK3 P84/IRQ4-B/EDACK2 P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ ETEND3 P82/IRQ2-B/ETEND2 P81/IRQ1-B/PO1-B/TIOCB3-B/ TMRI1-B/TxD3/ EDREQ3 P80/IRQ0-B/EDREQ2 P85/IRQ5-B/PO5-B/ TIOCB4-B/TMO1-B/ SCK3 P84/IRQ4-B P83/IRQ3-B/PO3-B/ TIOCD3-B/TMCI1-B/ RxD3 P82/IRQ2-B P81/IRQ1-B/PO1-B/ TIOCB3-B/TMRI1-B/ TxD3 P80/IRQ0-B Schmitt-triggered inputs when used as IRQ inputs. Open-drain output capability. Only P81, P83, and P85 are Schmitt-triggered inputs when used as TPU inputs. Rev. 1.00 Sep. 19, 2008 Page 495 of 1270 REJ09B0466-0100 Section 10 I/O Ports Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Port 9 Dedicated input port also functioning as A/D converter analog inputs and D/A converter analog outputs P97/AN15_1 P96/AN14_1 P95/AN13_1/DA3 P94/AN12_1/DA2 P93/AN11_1 P92/AN10_1 P91/AN9_1 P90/AN8_1 Port A General I/O port also functioning as address outputs, interrupt inputs, SSU I/Os, and SCI I/Os PA7/A23/IRQ7-A/ SSO0-B PA6/A22/IRQ6-A/ SSI0-B PA5/A21/IRQ5-A/ SSCK0-B A20/IRQ4-A A19 A18 A17 A16 PA7/A23/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 Only PA4 to PA7 are Schmitttriggered inputs PA5/IRQ5-A/SSCK0-B when used as PA4/IRQ4-A/SCS0-B IRQ inputs. Built-in input pullPA3/SCK4-B up MOS. PA2/RxD4-B Open-drain output PA1/TxD4-B capability. PA7/IRQ7-A/SSO0-B PA6/IRQ6-A/SSI0-B PA0 Port B General I/O port also functioning as address outputs and TPU I/Os A15 A14 A13 A12 A11 A10 A9 A8 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PB7/TIOCB8/TCLKH PB6/TIOCA8 PB5/TIOCB7/TCLKG PB4/TIOCA7 PB3/TIOCD6/TCLKF PB2/TIOCC6/TCLKE PB1/TIOCB6 PB0/TIOCA6 PC7/TIOCB11 PC6/TIOCA11 PC5/TIOCB10 PC4/TIOCA10 PC3/TIOCD9 PC2/TIOCC9 PC1/TIOCB9 PC0/TIOCA9 Built-in input pullup MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. Port C General I/O port also functioning as address outputs and TPU I/Os A7 A6 A5 A4 A3 A2 A1 A0 Built-in input pullup MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. Rev. 1.00 Sep. 19, 2008 Page 496 of 1270 REJ09B0466-0100 Section 10 I/O Ports Mode 7 Port Description Mode 1 D15 D14 D13 D12 D11 D10 D9 D8 Port E General I/O port also functioning as data I/Os PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port F General I/O port also functioning as interrupt inputs, bus control signal I/Os, SSU I/Os, and A/D converter inputs PF7/ PF6/AS/AH RD HWR PF3/LWR/SSO0-C PF2/LCAS/DQML/IRQ15-A/SSI0-C PF1/UCAS/DQMU/IRQ14-A/SSCK0-C PF0/WAIT-A/ADTRG0-B/SCS0-C PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Mode 2 Mode 4 EXPE = 1 EXPE = 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7/ PF6 PF5 PF4 PF3/SSO0-C PF2/IRQ15-A/SSI0-C PF1/IRQ14-A/ SSCK0-C PF0/ADTRG0-B/ SCS0-C Port G General I/O port also functioning as bus control signal I/Os and JTAG inputs PG6/BREQ-A/TDI*3 PG5/BACK-A/TMS* 3 Input/ Output Type Built-in input pullup MOS. Open-drain output capability. Port D General I/O port also functioning as data I/Os Built-in input pullup MOS. Open-drain output capability. Only PF1 and PF2 are Schmitttriggered inputs when used as IRQ inputs. Open-drain output capability. PG6/TDI*3 PG5/TMS*3 PG4/TCK*3 1 Open-drain output capability. PG4/BREQO-A/TCK*3 PG3/CS3/RAS3/CAS* PG1/CS1 PG0/CS0 PH3/CS7/OE-A/CKE-A*1/IRQ7-B PH2/CS6/IRQ6-B PH1/CS5/RAS5/SDRAM*1 PH0/CS4/RAS4/WE* 1 PG3 PG2 PG1 PG0 PH3/IRQ7-B PH2/IRQ6-B PH1/SDRAM*1 PH0 Only PH2 and PH3 are Schmitttriggered inputs when used as IRQ inputs. Open-drain output capability. Open-drain output capability for only PJ0 and PJ1. 5-V tolerance. PG2/CS2/RAS2/RAS*1 Port H General I/O port also functioning as interrupt inputs and bus control signal I/Os Port J General I/O port PJ2*2 PJ1 PJ0 Rev. 1.00 Sep. 19, 2008 Page 497 of 1270 REJ09B0466-0100 Section 10 I/O Ports Notes: 1. Not supported in the H8S/2426 Group. 2. Not supported in the 145-pin package. 3. Supported only in the 145-pin package. Table 10.2 Port Functions of H8S/2424 Group Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Schmitt-triggered inputs. Open-drain output capability. Port 1 General I/O port also functioning as PPG outputs, TPU I/Os, DMAC I/Os, and SSU I/Os P17/PO15/TIOCB2/TCLKD/SCS0-A P16/PO14/TIOCA2/SSCK0-A P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A P14/DACK0/PO12/TIOCA1/SSO0-A P13/TEND1/PO11/TIOCD0/TCLKB P12/TEND0/PO10/TIOCC0/TCLKA P11/DREQ1/PO9/TIOCB0 P10/DREQ0/PO8/TIOCA0 Port 2 General I/O port also functioning as PPG outputs, TPU I/Os, SCI I/Os, TMR I/Os, I2C I/Os, A/D converter inputs, and bus control signal I/Os P27/PO7/TIOCB5/SCL2 P26/PO6/TIOCA5/SDA2/ADTRG1 P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A P22/PO2-A/TIOCC3-A/TMCI0-A P21/PO1-A/TIOCB3-A/TMRI1-A P20/PO0-A/TIOCA3-A/TMRI0 Schmitt-triggered inputs. Open-drain output P25/PO5-A/TIOCB4-A/ capability. TMO1-A 5-V tolerance. Port 3 General I/O port also functioning as SCI I/Os, I2C I/Os, and bus control signal I/Os P35/OE-B/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD P35/SCK1/SCL0 Open-drain output capability. Only P32 to P35 are Schmitttriggered inputs when used as I2C inputs. P32 to P35 have 5-V tolerance. Schmitt-triggered inputs when used as IRQ inputs. Port 4 General I/O port also functioning as A/D converter analog inputs and interrupt inputs P47/IRQ7-B/AN7_0 P46/IRQ6-B/AN6_0 P45/IRQ5-B/AN5_0 P44/IRQ4-B/AN4_0 P43/IRQ3-B/AN3_0 P42/IRQ2-B/AN2_0 P41/IRQ1-B/AN1_0 P40/IRQ0-B/AN0_0 Rev. 1.00 Sep. 19, 2008 Page 498 of 1270 REJ09B0466-0100 Section 10 I/O Ports Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Schmitt-triggered inputs when used as IRQ inputs. Only P50 and P51 are Schmitttriggered inputs when used as I2C inputs. Open-drain output capability. Only P50 to P52 are Schmitttriggered inputs when used as TPU inputs. Only P50 and P51 are Schmitttriggered inputs when used as 8bit timer inputs. P50 and P51 have 5-V tolerance. Open-drain output capability. Only P81, P83, and P85 are Schmitt-triggered inputs when used as TPU inputs. Only P81 and P83 are Schmitttriggered inputs when used as 8bit timer inputs. P81 and P83 have 5-V tolerance. Port 5 General I/O port also functioning as interrupt inputs, A/D converter inputs, SCI I/Os, PPG outputs, TPU I/Os, TMR I/Os, I2C I/Os, and bus control signal I/Os P53/IRQ3-A /ADTRG0-A P52/BACK-B/IRQ2-A /PO4-B/TIOCA4-B/TMO0-B/ SCK2 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/ RxD2/SCL3 P52/IRQ2-A/PO4-B/ TIOCA4-B/TMO0-B/ SCK2 P51/IRQ1-A/PO2-B/ TIOCC3-B/TMCI0-B/ RxD2/SCL3 P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/ P50/IRQ0-A/PO0-B/ TxD2/SDA3 TIOCA3-B/TMRI0-B/ TxD2/SDA3 Port 8 General I/O port also P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 functioning as PPG P83/PO3-B/TIOCD3-B/ TMCI1-B/RxD3 outputs, P81/PO1-B/TIOCB3-B/ TMRI1-B/TxD3 TPU I/Os, TMR I/Os, and SCI I/Os Port 9 Dedicated input port also functioning as A/D converter analog inputs and D/A converter analog outputs P95/AN13_1/DA3 P94/AN12_1/DA2 Rev. 1.00 Sep. 19, 2008 Page 499 of 1270 REJ09B0466-0100 Section 10 I/O Ports Mode 7 Port Description Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 PA7/IRQ7-A/SSO0-B Input/ Output Type Port A General I/O port also functioning as address outputs, SSU I/Os, SCI I/Os, and bus control signal outputs PA7/A23/CS7/ IRQ7-A/SSO0-B PA6/A22/IRQ6-A/ SSI0-B PA5/A21/IRQ5-A/ SSCK0-B A20/IRQ4-A A19 A18 A17 A16 PA7/A23/CS7/IRQ7A/ SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Only PA4 to PA7 are Schmitttriggered inputs PA6/IRQ6-A/SSI0-B when used as IRQ inputs. PA5/IRQ5-A/SSCK0-B Built-in input pullup MOS. Open-drain output PA4/IRQ4-A/SCS0-B capability. PA3/SCK4-B PA2/RxD4-B PA1/TxD4-B PA0 PB7/TIOCB8/TCLKH PB6/TIOCA8 PB5/TIOCB7/TCLKG PB4/TIOCA7 PB3/TIOCD6/TCLKF PB2/TIOCC6/TCLKE PB1/TIOCB6 PB0/TIOCA6 PC7/TIOCB11 PC6/TIOCA11 PC5/TIOCB10 PC4/TIOCA10 PC3/TIOCD9 PC2/TIOCC9 PC1/TIOCB9 PC0/TIOCA9 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Built-in input pullup MOS. Open-drain output capability. Built-in input pullup MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. Built-in input pullup MOS. Schmitt-triggered inputs when used as TPU inputs. Open-drain output capability. Port B General I/O port also A15 functioning as A14 address outputs and A13 TPU I/Os A12 A11 A10 A9 A8 Port C General I/O port also A7 functioning as A6 address outputs and A5 TPU I/Os A4 A3 A2 A1 A0 Port D General I/O port also D15 functioning as data D14 I/Os D13 D12 D11 D10 D9 D8 Rev. 1.00 Sep. 19, 2008 Page 500 of 1270 REJ09B0466-0100 Section 10 I/O Ports Mode 7 Port Description Mode 1 Mode 2 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Mode 4 EXPE = 1 EXPE = 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7/ PF6 PF5 PF4 PF3/SSO0-C PF2/SSI0-C PF1/SSCK0-C PF0/ADTRG0-B/ SCS0-C PG6 PG5 PG4 PG3 PG2 PG1 PG0 Open-drain output capability. Open-drain output capability. Input/ Output Type Built-in input pullup MOS. Open-drain output capability. Port E General I/O port also PE7/D7 functioning as data PE6/D6 I/Os PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port F General I/O port also functioning as bus control signal I/Os, SSU I/Os, and A/D converter inputs PF7/ PF6/AS/AH RD HWR PF3/LWR/SSO0-C PF2/CS6/LCAS/SSI0-C PF1/CS5/UCAS/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C Port G General I/O port also PG6/BREQ-A functioning as bus PG5/BACK-A control signal I/Os PG4/BREQO-A/CS4 PG3/CS3/RAS3 PG2/CS2/RAS2 PG1/CS1 PG0/CS0 Rev. 1.00 Sep. 19, 2008 Page 501 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.1 Port 1 Port 1 is an 8-bit I/O port that also has other functions. Port 1 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. * * * * * Port 1 data direction register (P1DDR) Port 1 data register (P1DR) Port 1 register (PORT1) Port 1 open drain control register (P1ODR) Port function control register 5 (PFCR5) Port 1 Data Direction Register (P1DDR) 10.1.1 The individual bits of P1DDR specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. Rev. 1.00 Sep. 19, 2008 Page 502 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states of port 1. PORT1 cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P17 P16 P15 P14 P13 P12 P11 P10 * Initial Value * * * * * * * * R/W R R R R R R R R Description If this register is read while a P1DDR bit is set to 1, the corresponding P1DR value is read. If this register is read while a P1DDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins P17 to P10. Rev. 1.00 Sep. 19, 2008 Page 503 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.1.4 Port 1 Open Drain Control Register (P1ODR) P1ODR specifies the output type of each port 1 pin. Bit 7 6 5 4 3 2 1 0 Bit Name P17ODR P16ODR P15ODR P14ODR P13ODR P12ODR P11ODR P10ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting a P1ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P1ODR bit to 0 makes the corresponding pin a CMOS output pin. 10.1.5 Pin Functions Port 1 pins also function as the pins for PPG outputs, TPU I/Os, EXDMAC I/Os (H8S/2426, H8S/2426R), SSU I/Os, and DMAC I/Os (H8S/2424). The correspondence between the register specification and the pin functions is shown below. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group * P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH of the PPG, bit EDRAKE in EDMDR_3 of the EXDMAC, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits SCS0S1 and SCS0S0 in PFCR5, and bit P17DDR. Rev. 1.00 Sep. 19, 2008 Page 504 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Modes 1, 2, 4, and 7 (EXPE = 1) SSU settings EDRAKE TPU channel 2 (1) in table settings below P17DDR NDER15 Pin function TIOCB2 output 0 Can be used as I/O port 0 (2) in table below 1 0 1 1 PO15 output 1 2 Input state Output state 1 EDRAK3 output SCS0-A input*3 0 SCS0-A output*4 P17 input P17 output TIOCB2 input* TCLKD input* * Mode 7 (EXPE = 0) SSU settings EDRAKE TPU channel 2 settings P17DDR NDER15 Pin function (1) in table below TIOCB2 output 0 P17 input Can be used as I/O port 0 (2) in table below 1 0 1 Input state Output state 1 1 0 SCS0-A input*3 SCS0-A output*4 P17 output PO15 output TIOCB2 input* 2 TCLKD input* Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1. 2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. 3. SCSO-A input when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00xx, B'0101, or B'0110. Do not set up for TPU or EXDMAC outputs with SCSO-A input. 4. SCSO-A output when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011x. Rev. 1.00 Sep. 19, 2008 Page 505 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 2 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 SCS pin settings SSUMS MSS CSS1 CSS0 Pin state 0 x x Input 0 0 1 Input 0 Automatic I/O 0 1 1 1 Output 1 x x x Legend: x: Don't care : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 506 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P16/PO14/TIOCA2/EDRAK2/SSCK0-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH of the PPG, bit EDRAKE in EDMDR_2 of the EXDMAC, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR. * Modes 1, 2, 4, and 7 (EXPE = 1) SSU settings EDRAKE TPU channel 2 (1) in table settings below P16DDR NDER14 Pin function TIOCA2 output 0 Can be used as I/O port 0 (2) in table below 1 0 1 1 PO14 output 1 Input state Output state 1 EDRAK2 SSCK0-A input*3 output 0 SSCK0-A output*4 P16 input P16 output TIOCA2 input* * Mode 7 (EXPE = 0) SSU settings EDRAKE TPU channel 2 settings P16DDR NDER14 Pin function (1) in table below TIOCA2 output 0 P16 input Can be used as I/O port 0 (2) in table below 1 0 P16 output TIOCA2 input* 1 Input state 1 1 PO14 output SSCK0-A input*3 0 Output state SSCK0-A output*4 Rev. 1.00 Sep. 19, 2008 Page 507 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 2 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. TIOCB2 output disabled. 3. SSCK0-A input when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. Do not set up for TPU or EXDMAC outputs with SSCK0-A input. 4. SSCK0-A output when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'x11. SSCK pin settings SSUMS MSS SCKS Pin state 0 0 1 Input 0 0 1 1 Output 0 0 1 Input 0 1 1 1 Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 508 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P15/PO13/TIOCB1/TCLKC/SSI0-A The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSI0S1 and SSI0S0 in PFCR5, and bit P15DDR. SSU settings TPU channel 1 settings P15DDR NDER13 Pin function (1) in table below TIOCB1 output 0 P15 input Can be used as I/O port (2) in table below 1 0 P15 output TIOCB1 input* TCLKC input* 2 Input state Output state 1 1 PO13 output 1 0 SSI0-A input*3 SSI0-A output*4 Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111, or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC input when phase counting mode is set for channels 2 and 4. 3. SSI0-A input when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001x1 or B'10xx1. Do not set up for TPU output with SSI0-A input. 4. SSI0-A output when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001x. TPU channel 1 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 509 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSI pin settings SSUMS BIDE MSS TE RE 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 Input Pin state Output Output Input Input Input Input Input Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 510 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P14/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR. SSU settings TPU channel 1 settings P14DDR NDER12 Pin function (1) in table below TIOCA1 output 0 P14 input Can be used as I/O port (2) in table below 1 0 P14 output TIOCA1 input* 1 Input state 1 1 PO12 output SSO0-A input*3 0 Output state SSO0-A output*4 TPU channel 1 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. 2. TIOCB1 output disabled. 3. SSO0-A input when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000x1 or B'01x01. Do not set up for TPU output with SSO0-A input. 4. SSO0-A output when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0011x, B'01x10, or B'10x1x. Rev. 1.00 Sep. 19, 2008 Page 511 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSO pin settings SSUMS BIDE MSS TE RE 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 Pin state Input Input Output Output Input Output Input Output Output Output Output Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 512 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P13/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH of the PPG, and bit P13DDR. TPU channel 0 settings P13DDR NDER11 Pin function (1) in table below TIOCD0 output 0 P13 input 0 P13 output TIOCD0 input* TCLKB input* 2 1 (2) in table below 1 1 PO11 output Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. 2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101. TCLKB input when phase counting mode is set for channels 1 and 5. TPU channel 0 settings MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function Other than B'110 PWM mode 2 output B'110 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 513 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH of the PPG, and bit P12DDR. TPU channel 0 settings P12DDR NDER10 Pin function (1) in table below TIOCC0 output 0 P12 input 0 P12 output TIOCC0 input* TCLKA input* 2 1 (2) in table below 1 1 PO10 output TPU channel 0 settings MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'101 B'101 PWM*3 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100. TCLKA input when phase counting mode is set for channels 1 and 5. 3. TIOCD0 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0. Rev. 1.00 Sep. 19, 2008 Page 514 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of the PPG, and bit P11DDR. TPU channel 0 settings P11DDR NDER9 Pin function Note: * (1) in table below TIOCB0 output 0 P11 input 0 P11 output TIOCB0 input* TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx. (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) (2) in table below 1 1 PO9 output TPU channel 0 settings MD3 to MD0 IOB3 to IOB0 CCLR2 to CCLR0 Output function Other than B'010 PWM mode 2 output B'010 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 515 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of the PPG, and bit P10DDR. TPU channel 0 settings P10DDR NDER8 Pin function (1) in table below TIOCA0 output 0 P10 input 0 P10 output TIOCA0 input* 1 (2) in table below 1 1 PO8 output TPU channel 0 settings MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'001 B'001 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. 2. TIOCB0 output disabled. Rev. 1.00 Sep. 19, 2008 Page 516 of 1270 REJ09B0466-0100 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group * P17/PO15/TIOCB2/TCLKD/SCS0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH of the PPG, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits SCS0S1 and SCS0S0 in PFCR5, and bit P17DDR. SSU settings TPU channel 2 settings P17DDR NDER15 Pin function (1) in table below TIOCB2 output 0 P17 input Can be used as I/O port (2) in table below 1 0 P17 output TIOCB2 input* TCLKD input* 2 1 Input state 1 1 PO15 output SCS0-A input*3 0 Output state SCS0-A output*4 Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1. 2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. 3. SCS0-A input when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00xx, B'0101, or B'0110. Do not set up for TPU output with SCS0-A input. 4. SCS0-A output when SCS0S1 and SCS0S0 = B'00 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011x. TPU channel 2 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Rev. 1.00 Sep. 19, 2008 Page 517 of 1270 REJ09B0466-0100 Section 10 I/O Ports SCS pin settings SSUMS MSS CSS1 CSS0 Pin state 0 x x Input 0 0 1 Input 0 Automatic I/O 0 1 1 1 Output 1 x x x Legend: x: Don't care : Pin is not used by the SSU (can be used as I/O port) * P16/PO14/TIOCA2/SSCK0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH of the PPG, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR. SSU settings TPU channel 2 (1) in table settings below P16DDR NDER14 Pin function TIOCA2 output 0 P16 input Can be used as I/O port (2) in table below 1 0 P16 output TIOCA2 input*1 1 1 PO14 output SSCK0-A input*3 0 SSCK0-A output*4 Input state Output state Rev. 1.00 Sep. 19, 2008 Page 518 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 2 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. TIOCB2 output disabled. 3. SSCK0-A input when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. Do not set up for TPU output with SSCK0-A input. 4. SSCK0-A output when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'x11. SSCK pin settings SSUMS MSS SCKS Pin state 0 0 1 Input 0 0 1 1 Output 0 0 1 Input 0 1 1 1 Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 519 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A The pin function is switched as shown below according to the combination of bit SAE1 in DMABCRH of the DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSI0S1 and SSI0S0 in PFCR5, and bit P15DDR. SSU settings SAE1 TPU channel 1 (1) in table settings below P15DDR NDER13 Pin function TIOCB1 output 0 P15 input Can be used as I/O port 0 (2) in table below 1 0 P15 output 2 Input state Output state 1 0 SSI0-A input*3 SSI0-A output*4 1 1 PO13 output 1 DACK1 output TIOCB1 input* TCLKC input* Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111, or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC input when phase counting mode is set for channels 2 and 4. 3. SSI0-A input when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001x1 or B'10xx1. Do not set up for TPU or DMAC output with SSI0-A input. 4. SSI0-A output when SSI0S1 and SSI0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001x. Rev. 1.00 Sep. 19, 2008 Page 520 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 1 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care SSI pin settings SSUMS BIDE MSS TE RE Pin state 0 1 0 0 1 1 0 1 0 0 0 1 1 1 Input 0 1 0 1 0 0 1 0 1 1 1 0 0 1 Input 0 0 1 1 0 1 0 1 0 1 1 1 Input Output Output Input Input Input Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 521 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P14/DACK0/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of the DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR. SSU settings SAE0 TPU channel 1 (1) in table settings below P14DDR NDER12 Pin function TIOCA1 output 0 P14 input Can be used as I/O port 0 (2) in table below 1 0 P14 output 1 1 PO12 output 1 Input state Output state 1 DACK0 output SSO0-A input*3 0 SSO0-A output*4 TIOCA1 input* TPU channel 1 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. 2. TIOCB1 output disabled. 3. SSO0-A input when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000x1 or B'01x01. Do not set up for TPU or DMAC output with SSO0-A input. 4. SSO0-A output when SSO0S1 and SSO0S0 = B'00 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0011x, B'01x10, or B'10x1x. Rev. 1.00 Sep. 19, 2008 Page 522 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSO pin settings SSUMS BIDE MSS TE RE Pin state 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 1 0 1 Input Input Output Output Input Output Input Output Output Output Output Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 523 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P13/TEND1/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of bit TEE1 in DMATCR of the DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH of the PPG, and bit P13DDR. TEE1 TPU channel 0 settings P13DDR NDER11 Pin function (1) in table below TIOCD0 output 0 P13 input 0 (2) in table below 1 0 P13 output 2 1 1 1 PO11 output TIOCD0 input*1 TCLKB input* TEND1 output Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. 2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101. TCLKB input when phase counting mode is set for channels 1 and 5. TPU channel 0 settings MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function Other than B'110 PWM mode 2 output B'110 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 524 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P12/TEND0/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of bit TEE0 in DMATCR of the DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH of the PPG, and bit P12DDR. TEE0 TPU channel 0 settings P12DDR NDER10 Pin function (1) in table below TIOCC0 output 0 P12 input 0 (2) in table below 1 0 P12 output 2 1 1 1 PO10 output TIOCC0 input*1 TCLKA input* TEND0 output TPU channel 0 settings MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'101 B'101 PWM*3 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100. TCLKA input when phase counting mode is set for channels 1 and 5. 3. TIOCD0 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0. Rev. 1.00 Sep. 19, 2008 Page 525 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P11/DREQ1/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of the PPG, and bit P11DDR. TPU channel 0 settings P11DDR NDER9 Pin function (1) in table below TIOCB0 output 0 P11 input 0 P11 output TIOCB0 input* DREQ1 input Note: * TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx. (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) (2) in table below 1 1 PO9 output TPU channel 0 settings MD3 to MD0 IOB3 to IOB0 CCLR2 to CCLR0 Output function Other than B'010 PWM mode 2 output B'010 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 526 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P10/DREQ0/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of the PPG, and bit P10DDR. TPU channel 0 settings P10DDR NDER8 Pin function (1) in table below TIOCA0 output 0 P10 input 0 P10 output TIOCA0 input* DREQ0 input TPU channel 0 settings MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 Other than B'xx00 (2) 1 (2) in table below 1 1 PO8 output CCLR2 to CCLR0 Output function Other than B'001 B'001 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. 2. TIOCB0 output disabled. Rev. 1.00 Sep. 19, 2008 Page 527 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.2 Port 2 Port 2 is an 8-bit I/O port that also has other functions. Port 2 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. * * * * * Port 2 data direction register (P2DDR) Port 2 data register (P2DR) Port 2 register (PORT2) Port 2 open drain control register (P2ODR) Port function control register 3 (PFCR3) Port 2 Data Direction Register (P2DDR) 10.2.1 The individual bits of P2DDR specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. Rev. 1.00 Sep. 19, 2008 Page 528 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.2.3 Port 2 Register (PORT2) PORT2 shows the pin states of port 2. PORT2 cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P27 P26 P25 P24 P23 P22 P21 P20 * Initial Value * * * * * * * * R/W R R R R R R R R Description If this register is read while a P2DDR bit is set to 1, the corresponding P2DR value is read. If this register is read while a P2DDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins P27 to P20. Rev. 1.00 Sep. 19, 2008 Page 529 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.2.4 Port 2 Open Drain Control Register (P2ODR) P2ODR specifies the output type of each port 2 pin. Bit 7 6 5 4 3 2 1 0 Bit Name P27ODR P26ODR P25ODR P24ODR P23ODR P22ODR P21ODR P20ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting a P2ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P2ODR bit to 0 makes the corresponding pin a CMOS output pin. Rev. 1.00 Sep. 19, 2008 Page 530 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.2.5 Pin Functions Port 2 pins also function as the pins for PPG outputs, TPU I/Os, interrupt inputs (H8S/2426, H8S/2426R), 8-bit timer I/Os (H8S/2424), I2C I/Os, and bus control signal inputs. The correspondence between the register specification and the pin functions is shown below. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group * P27/PO7/TIOCB5/IRQ15-B/SCL2 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL of the PPG, bit ICE in ICCRA_2 of the I2C, bit P27DDR, and bit ITS15 in ITSR of the interrupt controller. ICE TPU channel 5 settings P27DDR NDER7 Pin function (1) in table below TIOCB5 output 0 P27 input 0 (2) in table below 1 0 P27 output 1 1 PO7 output 1 1 SCL2 I/O TIOCB5 input* IRQ15-B interrupt input*2 Notes: 1. TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1. 2. IRQ15-B input when the ITS15 bit in ITSR is 1. Rev. 1.00 Sep. 19, 2008 Page 531 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 5 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care * P26/PO6/TIOCA5/IRQ14-B/SDA2/ADTRG1 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL of the PPG, bits TRGS1, TRGS0, and EXTRGS in ADCR_1 of the ADC, bit ICE in ICCRA_2 of the I2C, bit P26DDR, and bit ITS14 in ITSR of the interrupt controller. ICE TPU channel 5 settings P26DDR NDER6 Pin function (1) in table below TIOCA5 output 0 P26 input 0 (2) in table below 1 0 P26 output TIOCA5 input* 1 1 1 1 PO6 output SDA2 I/O IRQ14-B interrupt input*2 ADTRG1 input* 4 Rev. 1.00 Sep. 19, 2008 Page 532 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 5 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (2) B'0010 Other than B'xx00 (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*3 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. IRQ14-B input when the ITS14 bit in ITSR is 1. 3. TIOCB5 output disabled. 4. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1. * P25/PO5-A/TIOCB4-A/IRQ13-B/WAIT-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER5 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit WAITS in PFCR4, bit P25DDR, and bit ITS13 in ITSR of the interrupt controller. * Modes 1, 2, 4, and 7 (EXPE = 1) WAITE TPU channel 4 settings P25DDR NDER5 Pin function (1) in table below TIOCB4-A output*4 0 P25 input 0 (2) in table below 1 0 P25 output TIOCB4-A input*1*4 IRQ13-B interrupt input* 2 1 1 1 PO5-A output*3 WAIT-B input*5 Rev. 1.00 Sep. 19, 2008 Page 533 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 (EXPE = 0) WAITE TPU channel 4 settings P25DDR NDER5 Pin function (1) in table below TIOCB4-A output* 4 (2) in table below 0 P25 input 0 P25 output TIOCB4-A input*1*4 IRQ13-B interrupt input* 2 1 0 PO5-A output*3 Notes: 1. 2. 3. 4. 5. TIOCB4-A input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx. IRQ13-B input when the ITS13 bit in ITSR is 1. PO5-A output when the PPGS bit in PFCR3 is 0. TIOCB4-A input/output when the TPUS bit in PFCR3 is 0. WAIT-B input when the WAITS bit in PFCR4 is 1. (2) (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) TPU channel 4 settings MD3 to MD0 IOB3 to IOB0 B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 534 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER4 in NDERL of the PPG, bit RE in SCR_4 of the SCI, bits PPGS and TPUS in PFCR3, bit RXD4S in PFCR4, bit P24DDR, and bit ITS12 in ITSR of the interrupt controller TPU channel 4 settings RE P24DDR NDER4 Pin function (1) in table below TIOCA4-A 5 output* 0 P24 input 0 P24 output (2) in table below 0 1 1 PO4-A output* 4 1 RxD4-A 6 input* TIOCA4-A input*1*5 IRQ12-B interrupt input* TPU channel 4 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 2 (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*3 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA4-A input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. 2. IRQ12-B input when the ITS12 bit in ITSR is 1. 3. TIOCB4 output disabled. 4. PO4-A output when the PPGS bit in PFCR3 is 0. 5. TIOCA4-A input/output when the TPUS bit in PFCR3 is 0. 6. RxD4-A input when the RXD4S bit in PFCR4 is 0. Rev. 1.00 Sep. 19, 2008 Page 535 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit TE in SCR_4 of the SCI, bits PPGS and TPUS in PFCR3, bit TXD4S in PFCR4, bit P23DDR, and bit ITS11 in ITSR of the interrupt controller. TPU channel 3 settings TE P23DDR NDER3 Pin function (1) in table below TIOCD3-A 4 output* 0 P23 input 0 P23 output (2) in table below 0 1 1 PO3-A output* 3 1 TxD4-A 5 output* TIOCD3-A input*1*4 IRQ11-B interrupt input* Notes: 1. 2. 3. 4. 5. 2 TIOCD3-A input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. IRQ11-B input when the ITS11 bit in ITSR is 1. PO3-A output when the PPGS bit in PFCR3 is 0. TIOCD3-A input/output when the TPUS bit in PFCR3 is 0. TxD4-A output when the TXD4S bit in PFCR4 is 0. (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) TPU channel 3 settings MD3 to MD0 IOD3 to IOD0 CCLR2 to CCLR0 Output function Other than B'110 PWM mode 2 output B'110 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 536 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P22/IRQ10-B /PO2-A/TIOCC3-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P22DDR, and bit ITS10 in ITSR of the interrupt controller. TPU channel 3 settings P22DDR NDER2 Pin function (1) in table below TIOCC3-A output* 5 (2) in table below 0 P22 input 0 P22 output TIOCC3-A input* * IRQ10-B interrupt input* 2 1 5 1 1 PO2-A output*4 TPU channel 3 settings MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'101 B'101 PWM*3 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCC3-A input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2. IRQ10-B input when the ITS10 bit in ITSR is 1. 3. TIOCD3 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_3. 4. PO2-A output when the PPGS bit in PFCR3 is 0. 5. TIOCC3-A input/output when the TPUS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 537 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P21/IRQ9-B/PO1-A/TIOCB3-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P21DDR, and bit ITS9 in ITSR of the interrupt controller. TPU channel 3 settings P21DDR NDER1 Pin function (1) in table below TIOCB3-A 4 output* 0 P21 input 0 P21 output TIOCB3-A input*1*4 IRQ9-B interrupt input* Notes: 1. 2. 3. 4. 2 (2) in table below 1 1 PO1-A output*3 TIOCB3-A input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx. IRQ9-B input when the ITS9 bit in ITSR is 1. PO1-A output when the PPGS bit in PFCR3 is 0. TIOCB3-A input/output when the TPUS bit in PFCR3 is 0. (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) TPU channel 3 settings MD3 to MD0 IOB3 to IOB0 CCLR2 to CCLR0 Output function Other than B'010 PWM mode 2 output B'010 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 538 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P20/PO0-A/TIOCA3-A/IRQ8-B*2 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P20DDR, and bit ITS8 in ITSR of the interrupt controller. TPU channel 3 settings P20DDR NDER0 Pin function (1) in table below TIOCA3-A 5 output* 0 P20 input 0 P20 output TIOCA3-A input*1*5 IRQ8-B interrupt input* 2 (2) in table below 1 1 PO0-A output*4 TPU channel 3 settings MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0001 to B'0011 B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'001 B'001 PWM*3 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. 2. IRQ8-B input when the ITS8 bit in ITSR is 1. 3. TIOCB3 output disabled. 4. PO0-A output when the PPGS bit in PFCR3 is 0. 5. TIOCA3-A input/output when the TPUS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 539 of 1270 REJ09B0466-0100 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group * P27/PO7/TIOCB5/SCL2 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL of the PPG, bit ICE in ICCRA_2 of the I2C, and bit P27DDR. ICE TPU channel 5 settings P27DDR NDER7 Pin function Note: * (1) in table below TIOCB5 output 0 P27 input 0 (2) in table below 1 0 P27 output 1 1 PO7 output 1 SCL2 I/O TIOCB5 input* TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1. (2) (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) TPU channel 5 settings MD3 to MD0 IOB3 to IOB0 B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 540 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P26/PO6/TIOCA5/SDA2/ADTRG1 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL of the PPG, bits TRGS1, TRGS0, and EXTRGS in ADCR_1 of the ADC, bit ICE in ICCRA_2 of the I2C, and bit P26DDR. ICE TPU channel 5 settings P26DDR NDER6 Pin function (1) in table below TIOCA5 output 0 P26 input 0 (2) in table below 1 0 P26 output TIOCA5 input*1 ADTRG1 input* TPU channel 5 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 3 1 1 1 PO6 output SDA2 I/O (2) B'0010 Other than B'xx00 (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. TIOCB5 output disabled. 3. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1. Rev. 1.00 Sep. 19, 2008 Page 541 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0*8 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit WAITS in PFCR4, and bit P25DDR. * Modes 1, 2, 4, and 7 (EXPE = 1) WAITE TPU channel 4 settings OS3 to OS0 P25DDR NDER5 Pin function 0 (1) in table below TIOCB4-A output*3 0 P25 input (2) in table below All 0 1 0 P25 output 1 1 PO5-A output*2 Not all 0 TMO1-A output*4 1 3 1 WAIT-B input*5 TIOCB4-A input* * * Mode 7 (EXPE = 0) WAITE TPU channel 4 settings OS3 to OS0 P25DDR NDER5 Pin function Notes: 1. 2. 3. 4. 5. (1) in table below TIOCB4-A output*3 0 P25 input (2) in table below All 0 0 P25 output 1 0 PO5-A output* 2 Not all 0 1 1 TIO1-A output*4 TIOCB4-A input*1*3 TIOCB4-A input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx. PO5-A output when the PPGS bit in PFCR3 is 0. TIOCB4-A input/output when the TPUS bit in PFCR3 is 0. TMO1-A output when the TMRS bit in PFCR3 is 0. WAIT-B input when the WAITS bit in PFCR4 is 1. Rev. 1.00 Sep. 19, 2008 Page 542 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 4 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care * P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A The pin function is switched as shown below according to the combination of bits OS3 to OS0 in TCSR_0 of the 8-bit timer, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER4 in NDERL of the PPG, bit RE in SCR_4 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit RXD4S in PFCR4, and bit P24DDR. TPU channel 4 settings OS3 to OS0 RE P24DDR NDER4 Pin function (1) in table below TIOCA4-A output*4 0 P24 input 0 1 0 P24 output 1 1 PO4-A output*3 (2) in table below All 0 1 RxD4-A input*6 Not all 0 TMO0-A output*5 TIOCA4-A input*1*4 Rev. 1.00 Sep. 19, 2008 Page 543 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 4 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA4-A input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. 2. TIOCB4 output disabled. 3. PO4-A output when the PPGS bit in PFCR3 is 0. 4. TIOCA4-A input/output when the TPUS bit in PFCR3 is 0. 5. TMO0-A output when the TMRS bit in PFCR3 is 0. 6. RxD4-A input when the RXD4S bit in PFCR4 is 0. Rev. 1.00 Sep. 19, 2008 Page 544 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit TE in SCR_4 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit TXD4S in PFCR4, and bit P23DDR. TPU channel 3 settings TE P23DDR NDER3 Pin function (1) in table below TIOCD3-A output*3 0 P23 input 0 P23 output (2) in table below 0 1 1 PO3-A output*2 1 3 1 TxD4-A output*5 TIOCD3-A input* * TMCI1-A input* Notes: 1. 2. 3. 4. 5. 4 TIOCD3-A input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. PO3-A output when the PPGS bit in PFCR3 is 0. TIOCD3-A input/output when the TPUS bit in PFCR3 is 0. TMCI1-A input when the TMRS bit in PFCR3 is 0. TxD4-A output when the TXD4S bit in PFCR4 is 0. (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) TPU channel 3 settings MD3 to MD0 IOD3 to IOD0 CCLR2 to CCLR0 Output function Other than B'110 PWM mode 2 output B'110 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 545 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P22/PO2-A/TIOCC3-A/TMCI0-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P22DDR. TPU channel 3 settings P22DDR NDER2 Pin function (1) in table below TIOCC3-A output* 4 (2) in table below 0 P22 input 0 P22 output TIOCC3-A input* * TMCI0-A input* 5 1 4 1 1 PO2-A output*3 TPU channel 3 settings MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'101 B'101 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCC3-A input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2. TIOCD3 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_3. 3. PO2-A output when the PPGS bit in PFCR3 is 0. 4. TIOCC3-A input/output when the TPUS bit in PFCR3 is 0. 5. TMCI0-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 546 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P21/PO1-A/TIOCB3-A/TMRI1-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P21DDR. TPU channel 3 settings P21DDR NDER1 Pin function (1) in table below TIOCB3-A 3 output* 0 P21 input 0 P21 output TIOCB3-A input*1*3 TMRI1-A input* Notes: 1. 2. 3. 4. 4 (2) in table below 1 1 PO1-A output*2 TIOCB3-A input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx. PO1-A output when the PPGS bit in PFCR3 is 0. TIOCB3-A input/output when the TPUS bit in PFCR3 is 0. TMRI1-A input when the TMRS bit in PFCR3 is 0. (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) TPU channel 3 settings MD3 to MD0 IOB3 to IOB0 CCLR2 to CCLR0 Output function Other than B'010 PWM mode 2 output B'010 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 547 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P20/PO0-A/TIOCA3-A/TMRI0-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P20DDR. TPU channel 3 settings P20DDR NDER0 Pin function (1) in table below TIOCA3-A 4 output* 0 P20 input 0 P20 output TIOCA3-A input*1*4 TMRI0-A input* 5 (2) in table below 1 1 PO0-A output*3 TPU channel 3 settings MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'001 B'001 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. 2. TIOCB3 output disabled. 3. PO0-A output when the PPGS bit in PFCR3 is 0. 4. TIOCA3-A input/output when the TPUS bit in PFCR3 is 0. 5. TMRI0-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 548 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.3 Port 3 Port 3 is a 6-bit I/O port that also has other functions. Port 3 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. * * * * * Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 register (PORT3) Port 3 open drain control register (P3ODR) Port function control register 2 (PFCR2) Port 3 Data Direction Register (P3DDR) 10.3.1 The individual bits of P3DDR specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be read. Bit 7, 6 5 4 3 2 1 0 Bit Name P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value All 0 0 0 0 0 0 0 R/W W W W W W W Description Reserved When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. Rev. 1.00 Sep. 19, 2008 Page 549 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit 7, 6 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P35DR P34DR P33DR P32DR P31DR P30DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.3.3 Port 3 Register (PORT3) PORT3 shows the pin states of port 3. PORT3 cannot be modified. Bit 7, 6 Bit Name Initial Value Undefined R/W Description Reserved If these bits are read, they will return an undefined value. 5 4 3 2 1 0 Note: P35 P34 P33 P32 P31 P30 * * * * * * * R R R R R R If this register is read while a P3DDR bit is set to 1, the corresponding P3DR value is read. If this register is read while a P3DDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins P35 to P30. Rev. 1.00 Sep. 19, 2008 Page 550 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.3.4 Port 3 Open Drain Control Register (P3ODR) P3ODR specifies the output type of each port 3 pin. Bit 7, 6 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0. Only the initial values should be written to these bits. 5 4 3 2 1 0 P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W When OE-B/CKE-B output is not selected, setting a P3ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P3ODR bit to 0 makes the corresponding pin a CMOS output pin. 10.3.5 Pin Functions Port 3 pins also function as the pins for SCI I/Os, I2C I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below. * P35/OE-B/CKE-B*4/SCK1/SCL0 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit ICE in ICCRA_0 of the I2C, bit C/A in SMR_1 and bits CKE0 and CKE1 in SCR_1 of the SCI, bits OEE and RMTS2 to RMTS0 in DRAMCR of the bus controller, bit OES in PFCR2, and bit P35DDR. Rev. 1.00 Sep. 19, 2008 Page 551 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Modes 1, 2, 4, and 7 (EXPE = 1) OEE OES RMTS2 to RMTS0 0 1 Areas 2 to 5 are DRAM space 1 0 Areas 2 to 5 are continuous SDRAM space ICE CKE1 C/A CKE0 P35DDR Pin function 0 P35 0 1 P35 0 1 SCK1 0 1 0 1 1 0 0 1 P35 0 1 SCK1 0 1 SCK1 0 1 1 OE-B CKE-B SCK1 SCK1 SCL0 P35 SCK1 SCL0 input output*1 output*1 output*1 input I/O*2 input output*1 output*1 output*1 input I/O*2 output*3 output*3*4 * Mode 7 (EXPE = 0) OEE OES RMTS2 to RMTS0 ICE CKE1 C/A CKE0 P35DDR Pin function Notes: 1. 2. 3. 4. 0 P35 input 0 1 P35 output*1 0 1 SCK1 output*1 0 1 SCK1 output*1 0 1 SCK1 input 0 1 SCL0 I/O*2 NMOS open-drain output when P35ODR = 1. NMOS open-drain output regardless of P35ODR. OE-B/CKE-B output when the OES bit in PFCR2 is 0. Not supported in the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 552 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P34/SCK0/SCK4-A/SDA0 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_0 of the I2C, bit C/A in SMR_0 and bits CKE0 and CKE1 in SCR_0 and SCR_4 of the SCI, and bit P34DDR. ICE CKE1 C/A CKE0 P34DDR Pin function Notes: 1. 2. 3. 4. 0 P34 input 0 1 0 1 0 1 0 1 1 SDA0 I/O*2 P34 SCK0/SCK4-A SCK0/SCK4-A SCK0/SCK4-A output*1 output*1*3*4 output*1*3*4 input*4 NMOS open-drain output when P34ODR = 1. NMOS open-drain output regardless of P34ODR. Simultaneous output of SCK0 and SCK4 cannot be set. SCK4-A input/output when the SCK4S bit in PFCR4 is 0. * P33/RxD1/SCL1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_1 of the I2C, bit RE in SCR_1 of the SCI, and bit P33DDR. ICE RE P33DDR Pin function 0 P33 input 0 1 P33 output* 1 0 1 RxD1 input 1 SCL1 I/O*2 Notes: 1. NMOS open-drain output when P33ODR = 1. 2. NMOS open-drain output regardless of P33ODR. Rev. 1.00 Sep. 19, 2008 Page 553 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P32/RxD0/IrRxD/SDA1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_1 of the I2C, bit RE in SCR_0 of the SCI, and bit P32DDR. ICE RE P32DDR Pin function 0 P32 input 0 1 P32 output* 1 0 1 RxD0/IrRxD input 1 SDA1 I/O*2 Notes: 1. NMOS open-drain output when P32ODR = 1. 2. NMOS open-drain output regardless of P32ODR. * P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR_1 of the SCI and bit P31DDR. TE P31DDR Pin function Note: * 0 P31 input NMOS open-drain output when P31ODR = 1. 0 1 P31 output* 1 TxD1 output* * P30/TxD0/IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR_0 of the SCI and bit P30DDR. TE P30DDR Pin function Note: * 0 P30 input NMOS open-drain output when P30ODR = 1. 0 1 P30 output* 1 TxD0/IrTxD output* Rev. 1.00 Sep. 19, 2008 Page 554 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.4 Port 4 Port 4 is an 8-bit input-only port that also has other functions, such as analog input pins. Port 4 has the following register. * Port 4 register (PORT4) 10.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows the pin states of port 4. PORT4 cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P47 P46 P45 P44 P43 P42 P41 P40 * Initial Value * * * * * * * * R/W R R R R R R R R Description The pin states are always read from this register. Determined by the states of pins P47 to P40. 10.4.2 Pin Functions Port 4 also functions as the pins for A/D converter analog inputs and interrupt inputs (the H8S/2424 Group). The correspondence between pins is as follows. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group * P40/AN0_0, P41/AN1_0, P42/AN2_0, P43/AN3_0, P44/AN4_0, P45/AN5_0, P46/AN6_0, P47/AN7_0 Pin function Legend: n = 7 to 0 ANn_0 input Rev. 1.00 Sep. 19, 2008 Page 555 of 1270 REJ09B0466-0100 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group * P47/IRQ7-B/AN7_0 Pin function AN7_0 input IRQ7-B interrupt input* * P46/IRQ6-B/AN6_0 Pin function AN6_0 input IRQ6-B interrupt input* * P45/IRQ5-B/AN5_0 Pin function AN5_0 input IRQ5-B interrupt input* * P44/IRQ4-B/AN4_0 Pin function AN4_0 input IRQ4-B interrupt input* * P43/IRQ3-B/AN3_0 Pin function AN3_0 input IRQ3-B interrupt input* * P42/IRQ2-B/AN2_0 Pin function AN2_0 input IRQ2-B interrupt input* * P41/IRQ1-B/AN1_0 Pin function AN1_0 input IRQ1-B interrupt input* * P40/IRQ0-B/AN0_0 Pin function Note: * AN0_0 input IRQ0-B interrupt input* IRQn input when the ITSn bit in ITSR is 1. (n = 7 to 0) Rev. 1.00 Sep. 19, 2008 Page 556 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.5 Port 5 Port 5 is a 4-bit I/O port. Port 5 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. * * * * * Port 5 data direction register (P5DDR) Port 5 data register (P5DR) Port 5 register (PORT5) Port 5 open drain control register (P5ODR) Port function control register 4 (PFCR4) Port 5 Data Direction Register (P5DDR) 10.5.1 The individual bits of P5DDR specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value All 0 0 0 0 0 R/W W W W W Description Reserved When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. 7 to 4 3 2 1 0 P53DDR P52DDR P51DDR P50DDR 10.5.2 Port 5 Data Register (P5DR) P5DR stores output data for the port 5 pins. Bit 7 to 4 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 3 2 1 0 P53DR P52DR P51DR P50DR 0 0 0 0 R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. Rev. 1.00 Sep. 19, 2008 Page 557 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.5.3 Port 5 Register (PORT5) PORT5 shows the pin states of port 5. PORT5 cannot be modified. Bit 7 to 4 Bit Name Initial Value Undefined R/W R Description Reserved If these bits are read, they will return an undefined value. 3 2 1 0 Note: P53 P52 P51 P50 * * * * * R R R R If the P53 to P50 bits are read while a P5DDR bit is set to 1, the corresponding P5DR value is read. If this register is read while a P5DDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins P53 to P50. 10.5.4 Port 5 Open Drain Control Register (P5ODR) P5ODR specifies the output type of each port 5 pin. Bit 7 to 4 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0. Only the initial values should be written to these bits. 3 2 1 0 P53ODR P52ODR P51ODR P50ODR 0 0 0 0 R/W R/W R/W R/W When BACK-B/BREQO-B output is not selected, setting a P5ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P5ODR bit to 0 makes the corresponding pin a CMOS output pin. Rev. 1.00 Sep. 19, 2008 Page 558 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.5.5 Pin Functions Port 5 pins also function as the pins for SCI I/Os, A/D converter inputs, interrupt inputs, I2C I/Os, bus control signal I/Os, JTAG inputs, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between the register specification and the pin functions is shown below. * P53/IRQ3-A/ADTRG0-A/TRST*3 The pin function is switched as shown below according to the combination of bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bit P53DDR, and bit ITS3 in ITSR of the interrupt controller. P53DDR Pin function 0 P53 input ADTRG0-A input* TRST input* 3 1 1 P53 output IRQ3-A interrupt input*2 Notes: 1. ADTRG0-A input when the EXTRGS bit in ADCR0 is 0, and TRGS1 = TRGS0 = 1. 2. IRQ3-A input when the ITS3 bit in ITSR is 0. 3. TRST input when BSCANE pin = 1 and EMLE = 0 in the 145-pin package. Rev. 1.00 Sep. 19, 2008 Page 559 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P52/SCK2/IRQ2-A/BACK-B/PO4-B/TIOCA4-B/TMO0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bits OS3 to OS0 in TCSR0 of 8-bit timer, bits MD3 to MD0 in TMDR_4 of TPU, bits IOA3 to IOA0 in TIOR_4, TPU channel 4 settings by bits CCLR1 and CCLR0 in TCR_4, bit NDER4 in NDERL of PPG, bit C/A in SMR_2 and bits CKE0 and CKE1 in SCR_2 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BACKS in PFCR4, bit P52DDR, bit NDER4 in NDERL of the PPG, and bit ITS2 in ITSR of the interrupt controller. * Modes 1, 2, 4, and 7 (EXPE = 1) BRLE BACKS TPU channel (1) in table 4 settings below OS3 to OS0 CKE1 C/A CKE0 P52DDR NDER4 Pin function TIOCA4-B 3 output* 0 P52 input 0 1 0 P52 output 1 1 PO4-B 2 output* 0 1 SCK2 output 0 1 SCK2 output 3 BRLE = 0 or BRLE = 1 and BACKS = 0 BRLE = 1 and BACKS = 1 Not all 0 1 SCK2 input TMO0-B 4 output* BACK-B output (2) in table below All 0 TIOCA4-B input* IRQ2-A interrupt input* 1 Rev. 1.00 Sep. 19, 2008 Page 560 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 (EXPE = 0) BRLE BACKS TPU channel (1) in table 4 settings below OS3 to OS0 CKE1 C/A CKE0 P52DDR NDER4 Pin function TIOCA4-B 3 output* 0 P52 input 0 1 0 P52 output 1 1 PO4-B 2 output* 0 1 SCK2 output 0 1 SCK2 output 3 (2) in table below All 0 1 SCK2 input Not all 0 TMO0-B 4 output* TIOCA4-B input* IRQ2-A interrupt input* 1 Notes: 1. 2. 3. 4. IRQ2-A input when the ITS2 bit in ITSR is 0. PO4-B output when the PPGS bit in PFCR3 is 1. TIOCA4-B input/output when the TPUS bit in PFCR3 is 1. TMO0-B output when the TMRS bit in PFCR3 is 1. (2) (1) (1) B'0010 Other than B'xx00 (2) B'001x B'xx00 (1) B'0011 Other than B'xx00 (2) TPU channel 4 settings MD3 to MD0 IOB3 to IOB0 B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function PWM mode 1 output Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 561 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P51/RxD2/IRQ1-A/SCL3/BREQ-B/PO2-B/TIOCC3-B/TMCI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I2C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOC3 to IOC0 in TIORL_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER2 in NDERL of PPG, bit RE in SCR_2 of the SCI, bit P51DDR, and bit ITS1 in ITSR of the interrupt controller. * Modes 1, 2, 4, and 7 (EXPE = 1) BRLE BREQS ICE TPU channel 3 settings RE P51DDR NDER2 Pin function (1) in table below TIOCC3-B 3 output* 0 P51 input BRLE = 0 or BRLE = 1 and BREQS = 0 BRLE = 1 and BREQS = 1 1 1 1 1 PO2-B 2 output* RxD2 input 3 0 (2) in table below 0 1 0 P51 output BREQ-B input SCL3 I/O TIOCC3-B input* IRQ1-A interrupt input* TMCI0-B input* 4 1 Rev. 1.00 Sep. 19, 2008 Page 562 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 (EXPE = 0) BRLE BREQS ICE TPU channel 3 settings RE P51DDR NDER2 Pin function (1) in table below TIOCC3-B output*3 0 P51 input 0 (2) in table below 0 1 0 P51 output 1 1 PO2-B output*2 1 RxD2 input 3 1 SCL3 I/O TIOCC3-B input* IRQ1-A interrupt input*1 TMCI0-B input* TPU channel 3 settings MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'001x B'xx00 4 (1) B'0010 Other than B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'101 B'101 PWM*3 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. IRQ1-A input when the ITS1 bit in ITSR is 0. 2. PO2-B output when the PPGS bit in PFCR3 is 1. 3. TIOCC3-B input/output when the TPUS bit in PFCR3 is 1. 4. TMCI0-B input when the TMRS bit in PFCR3 is 1. Rev. 1.00 Sep. 19, 2008 Page 563 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P50/TxD2/IRQ0-A/SDA3/BREQO-B*2/PO0-B/TIOCA3-B/TMRI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I2C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOA3 to IOA0 in TIORH_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER0 in NDERL of PPG, bit TE in SCR_2 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BREQOS in PFCR4, bit P50DDR, and bit ITS0 in ITSR of the interrupt controller. * Modes 1, 2, 4, and 7 (EXPE = 1) BRLE BREQOE BREQOS ICE TPU channel 3 settings TE P50DDR NDER0 Pin function (1) in table below 0 1 0 0 (2) in table below 0 1 BREQOE = 0 or BREQOE = 1 and BREQOS = 0 BREQOE = 1 and BREQOS = 1 1 (1) in table below 0 1 0 0 (2) in table below 1 0 1 1 1 0 1 1 1 BREQO-B output TIOCA3-B P50 P50 PO0-B TxD2 SDA3 TIOCA3-B P50 P50 PO0-B TxD2 SDA3 output*3 input output output*2 output I/O output*3 input output output*2 output I/O TIOCA3-B input*3 IRQ0-A interrupt input*1 TMRI0-B input*4 TIOCA3-B input*3 Rev. 1.00 Sep. 19, 2008 Page 564 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 (EXPE = 0) BRLE BREQOE BREQOS ICE TPU channel 3 settings TE P50DDR NDER0 Pin function (1) in table below TIOCA3-B output*3 0 P50 input 0 (2) in table below 0 1 0 P50 output 1 1 PO0-B output*2 3 1 1 TxD2 output SDA3 I/O TIOCA3-B input* IRQ0-A interrupt input*1 TMRI0-B input*4 TPU channel 3 settings MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'001 B'001 PWM*3 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. IRQ0-A input when the ITS0 bit in ITSR is 0. 2. PO0-B output when the PPGS bit in PFCR3 is 1. 3. TIOCA3-B input/output when the TPUS bit in PFCR3 is 1. 4. TMRI0-B input when the TMRS bit in PFCR3 is 1. Rev. 1.00 Sep. 19, 2008 Page 565 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.6 Port 6 Note: Port 6 is not supported in the H8S/2424 Group. Port 6 is a 6-bit I/O port that also has other functions. Port 6 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. * * * * * Port 6 data direction register (P6DDR) Port 6 data register (P6DR) Port 6 register (PORT6) Port 6 open drain control register (P6ODR) Port function control register 3 (PFCR3) Port 6 Data Direction Register (P6DDR) 10.6.1 The individual bits of P6DDR specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Bit 7, 6 5 4 3 2 1 0 Bit Name P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial Value All 0 0 0 0 0 0 0 R/W W W W W W W Description Reserved When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. Rev. 1.00 Sep. 19, 2008 Page 566 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.6.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit 7, 6 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P65DR P64DR P63DR P62DR P61DR P60DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.6.3 Port 6 Register (PORT6) PORT6 shows the pin states of port 6. PORT6 cannot be modified. Bit 7, 6 Bit Name Initial Value Undefined R/W Description Reserved If these bits are read, they will return an undefined value. 5 4 3 2 1 0 Note: P65 P64 P63 P62 P61 P60 * * * * * * * R R R R R R If this register is read while a P6DDR bit is set to 1, the corresponding P6DR value is read. If this register is read while a P6DDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins P65 to P60. Rev. 1.00 Sep. 19, 2008 Page 567 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.6.4 Port 6 Open Drain Control Register (P6ODR) P6ODR specifies the output type of each port 6 pin. Bit 7, 6 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0. Only the initial values should be written to these bits. 5 4 3 2 1 0 P65ODR P64ODR P63ODR P62ODR P61ODR P60ODR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Setting a P6ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P6ODR bit to 0 makes the corresponding pin a CMOS output pin. 10.6.5 Pin Functions Port 6 pins also function as 8-bit timer I/Os, interrupt inputs, and DMAC I/Os. The correspondence between the register specification and the pin functions is shown below. * P65/IRQ13-A/DACK1/TMO1-A The pin function is switched as shown below according to the combination of bit SAE1 in DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit TMRS in PFCR3, bit P65DDR, and bit ITS13 in ITSR of the interrupt controller. SAE1 OS3 to OS0 P65DDR Pin function 0 P65 input All 0 1 P65 output 0 Not all 0 TMO1-A output* 2 1 DACK1 output 1 IRQ13-A interrupt input* Notes: 1. IRQ13-A input when the ITS13 bit in ITSR is 0. 2. TMO1-A output when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 568 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P64/IRQ12-A/DACK0/TMO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit TMRS in PFCR3, bit P64DDR, and bit ITS12 in ITSR of the interrupt controller. SAE0 OS3 to OS0 P64DDR Pin function 0 P64 input All 0 1 P64 output 0 Not all 0 TMO0-A output* 2 1 DACK0 output 1 IRQ12-A interrupt input* Notes: 1. IRQ12-A input when the ITS12 bit in ITSR is 0. 2. TMO0-A output when the TMRS bit in PFCR3 is 0. * P63/IRQ11-A/TEND1/TMCI1-A The pin function is switched as shown below according to the combination of bit TEE1 in DMATCR of the DMAC, bit TMRS in PFCR3, bit P63DDR, and bit ITS11 in ITSR of the interrupt controller. TEE1 P63DDR Pin function 0 P63 input 0 1 P63 output IRQ11-A interrupt input*1 TMCI1-A input* * 2 3 1 TEND1 output Notes: 1. IRQ11-A input when the ITS11 bit in ITSR is 0. 2. When used as the external clock input pin for the TMR, its pin function should be specified to the external clock input by the CKS2 to CKS0 bits in TCR_1. 3. TMCI1-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 569 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P62/IRQ10-A/TEND0/TMCI0-A The pin function is switched as shown below according to the combination of bit TEE0 in DMATCR of the DMAC, bit TMRS in PFCR3, bit P62DDR, and bit ITS10 in ITSR of the interrupt controller. TEE0 P62DDR Pin function 0 P62 input 0 1 P62 output IRQ10-A interrupt input* TMCI0-A input* * 2 3 1 1 TEND0 output Notes: 1. IRQ10-A input when the ITS10 bit in ITSR is 0. 2. When used as the external clock input pin for the TMR, its pin function should be specified to the external clock input by the CKS2 to CKS0 bits in TCR_0. 3. TMCI0-A input when the TMRS bit in PFCR3 is 0. * P61/IRQ9-A/DREQ1/TMRI1-A The pin function is switched as shown below according to the combination of bit TMRS in PFCR3, bit P61DDR, and bit ITS9 in ITSR of the interrupt controller. P61DDR Pin function 0 P61 input TMRI1-A input* * DREQ1 input IRQ9-A interrupt input* 2 1 3 1 P61 output Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_1 should be set to 1. 2. IRQ9-A input when the ITS9 bit in ITSR is 0. 3. TMRI1-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 570 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P60/IRQ8-A/DREQ0/TMRI0-A The pin function is switched as shown below according to the combination of bit TMRS in PFCR3, bit P60DDR, and bit ITS8 in ITSR of the interrupt controller. P60DDR Pin function 0 P60 input TMRI0-A input*1*3. DREQ0 input IRQ8-A interrupt input* 2 1 P60 output Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_0 should be set to 1. 2. IRQ8-A input when the ITS8 bit in ITSR is 0. 3. TMRI0-A input when the TMRS bit in PFCR3 is 0. Rev. 1.00 Sep. 19, 2008 Page 571 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.7 Port 8 Port 8 is a 6-bit I/O port that also has other functions. Port 8 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. * * * * * Port 8 data direction register (P8DDR) Port 8 data register (P8DR) Port 8 register (PORT8) Port 8 open drain control register (P8ODR) Port function control register 3 (PFCR3) Port 8 Data Direction Register (P8DDR) 10.7.1 The individual bits of P8DDR specify input or output for the pins of port 8. P8DDR cannot be read; if it is, an undefined value will be read. Bit 7, 6 5 4 3 2 1 0 Bit Name P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial Value All 0 0 0 0 0 0 0 R/W W W W W W W Description Reserved When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. Bits 4, 2, and 0 are reserved in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 572 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.7.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit 7, 6 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P85DR P84DR P83DR P82DR P81DR P80DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. Bits 4, 2, and 0 are reserved in the H8S/2424 Group. 10.7.3 Port 8 Register (PORT8) PORT8 shows the pin states of port 8. PORT8 cannot be modified. Bit 7, 6 Bit Name Initial Value Undefined R/W Description Reserved If these bits are read, they will return an undefined value. 5 4 3 2 1 0 Note: P85 P84 P83 P82 P81 P80 * * * * * * * R R R R R R If this register is read while a P8DDR bit is set to 1, the corresponding P8DR value is read. If this register is read while a P8DDR bit is cleared to 0, the corresponding pin state is read. Bits 4, 2, and 0 are reserved in the H8S/2424 Group. Determined by the states of pins P85 to P80. Rev. 1.00 Sep. 19, 2008 Page 573 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.7.4 Port 8 Open Drain Control Register (P8ODR) P8ODR specifies the output type of each port 8 pin. Bit 7, 6 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0. Only the initial values should be written to these bits. 5 4 3 2 1 0 P85ODR P84ODR P83ODR P82ODR P81ODR P80ODR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Setting a P8ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P8ODR bit to 0 makes the corresponding pin a CMOS output pin. Bits 4, 2, and 0 are reserved in the H8S/2424 Group. 10.7.5 Pin Functions Port 8 pins also function as SCI I/Os, interrupt inputs, EXDMAC I/Os, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between the register specification and the pin functions is shown below. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group * P85/EDACK3/IRQ5-B/SCK3/PO5-B/TIOCB4-B/TMO1-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bit AMS in EDMDR_3 of the EXDMAC, bit C/A in SMR_3 and bits CKE0 and CKE1 in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit P85DDR, and bit ITS5 in ITSR of the interrupt controller. Rev. 1.00 Sep. 19, 2008 Page 574 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Modes 1, 2, 4, and 7 (EXPE = 1) TPU channel 4 settings OS3 to OS0 AMS CKE1 C/A CKE0 P85DDR NDER5 Pin function (1) in table below 0 0 1 0 P85 output 1 1 PO5-B 2 output* 0 1 SCK3 output 0 1 SCK3 output 3 (2) in table below All 0 0 1 SCK3 input 1 Not all 0 TIOCB4-B P85 input 3 output* EDACK3 TMO1-B 4 output output* TIOCB4-B input* IRQ5-B interrupt input* 1 * Mode 7 (EXPE = 0) TPU channel 4 settings OS3 to OS0 AMS CKE1 C/A CKE0 P85DDR NDER5 Pin function (1) in table below TIOCB4-B 3 output* 0 P85 input 0 1 0 P85 output 1 1 PO5-B 2 output* 0 1 SCK3 output 0 1 SCK3 output 3 (2) in table below All 0 1 SCK3 input Not all 0 TMO1-B 4 output* TIOCB4-B input* IRQ5-B interrupt input* 1 Notes: 1. 2. 3. 4. IRQ5-B input when the ITS5 bit in ITSR is 1. PO5-B output when the PPGS bit in PFCR3 is 1. TIOCB4-B input/output when the TPUS bit in PFCR3 is 1. TMO1-B output when the TMRS bit in PFCR3 is 1. Rev. 1.00 Sep. 19, 2008 Page 575 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 4 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care * P84/IRQ4-B/EDACK2 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR of the interrupt controller. Operating mode AMS P84DDR Pin function Note: * 0 P84 input 1, 2, 4, 7 (EXPE = 1) 0 1 P84 output 1 EDACK2 output IRQ4-B interrupt input* IRQ4-B input when the ITS4 bit in ITSR is 1. 0 P84 input 7 (EXPE = 0) 1 P84 output Rev. 1.00 Sep. 19, 2008 Page 576 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P83/ETEND3*5/IRQ3-B*5/RxD3/PO3-B/TIOCD3-B/TMCI1-B The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_3 of the EXDMAC, bit RE in SCR_3 of the SCI, TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit P83DDR, and bit ITS3 in ITSR of the interrupt controller. * Modes 1, 2, 4, and 7 (EXPE = 1) TPU channel 3 settings ETENDE RE P83DDR NDER3 Pin function (1) in table below TIOCD3-B output*3 0 P83 input 0 1 0 P83 output 1 1 PO3-B output*2 (2) in table below 0 1 RxD3 input 3 1 ETEND3 output TIOCD3-B input* IRQ3-B interrupt input*1 TMCI1-B input* 4 Rev. 1.00 Sep. 19, 2008 Page 577 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 (EXPE = 0) (1) in table below TIOCD3-B output*3 0 P83 input 0 P83 output 0 1 1 PO3-B output* 3 2 TPU channel 3 settings ETENDE RE P83DDR NDER3 Pin function (2) in table below 0 1 1 RxD3 input TIOCD3-B input* IRQ3-B interrupt input*1 TMCI1-B input* 4 Notes: 1. 2. 3. 4. IRQ3-B input when the ITS3 bit in ITSR is 1. PO3-B output when the PPGS bit in PFCR3 is 1. TIOCD3-B input/output when the TPUS bit in PFCR3 is 1. TMCI1-B input when the TMRS bit in PFCR3 is 1. (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) TPU channel 3 settings MD3 to MD0 IOD3 to IOD0 CCLR2 to CCLR0 Output function Other than B'110 PWM mode 2 output B'110 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 578 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P82/IRQ2-B/ETEND2 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR of the interrupt controller. Operating mode ETENDE P82DDR Pin function Note: * 0 P82 input 1, 2, 4, 7 (EXPE = 1) 0 1 P82 output 1 ETEND2 output IRQ2-B interrupt input* IRQ2-B input when the ITS2 bit in ITSR is 1. 0 P82 input 7 (EXPE = 0) 1 P82 output * P81/EDREQ3/IRQ1-B/TxD3/PO1-B/TIOCB3-B/TMRI1-B The pin function is switched as shown below according to the combination of bit TE in SCR_3 of the SCI, TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit P81DDR, and bit ITS1 in ITSR of the interrupt controller. TPU channel 3 settings TE P81DDR NDER1 Pin function (1) in table below TIOCB3-B output*3 0 P81 input 1 0 P81 output EDREQ3 input IRQ1-B interrupt input*1 TMRI1-B input*4 Notes: 1. 2. 3. 4. IRQ1-B input when the ITS1 bit in ITSR is 1. PO1-B output when the PPGS bit in PFCR3 is 1. TIOCB3-B input/output when the TPUS bit in PFCR3 is 1. TMRI1-B input when the TMRS bit in PFCR3 is 1. (2) in table below 0 1 1 PO1-B output* 3 2 1 TxD3 output TIOCB3-B input* Rev. 1.00 Sep. 19, 2008 Page 579 of 1270 REJ09B0466-0100 Section 10 I/O Ports TPU channel 3 settings MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'0010 (2) (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'010 PWM mode 2 output B'010 Legend: x: Don't care * P80/IRQ0-B/EDREQ2 The pin function is switched as shown below according to the combination of bit P80DDR and bit ITS0 in ITSR of the interrupt controller. P80DDR Pin function 0 P80 input EDREQ2 input IRQ0-B interrupt input* Note: * IRQ0-B input when the ITS0 bit in ITSR is 1. 1 P80 output Rev. 1.00 Sep. 19, 2008 Page 580 of 1270 REJ09B0466-0100 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group * P85/SCK3/PO5-B/TIOCB4-B/TMO1-B The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bit C/A in SMR_3 and bits CKE0 and CKE1 in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P85DDR. TPU channel 4 settings OS3 to OS0 CKE1 C/A CKE0 P85DDR NDER5 Pin function (1) in table below TIOCB4-B 3 output* 0 P85 input 0 1 0 P85 output 1 1 PO5-B 1 output* 0 1 SCK3 output 0 1 SCK3 output 2 (2) in table below All 0 1 SCK3 input Not all 0 TMO1-B 3 output* TIOCB4-B input* Notes: 1. PO5-B output when the PPGS bit in PFCR3 is 1. 2. TIOCB4-B input/output when the TPUS bit in PFCR3 is 1. 3. TMO1-B output when the TMRS bit in PFCR3 is 1. TPU channel 4 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 581 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit RE in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P83DDR. TPU channel 3 settings RE P83DDR NDER3 Pin function (1) in table below TIOCD3-B output*2 0 P83 input 0 P83 output 3 (2) in table below 0 1 1 PO3-B output*1 1 RxD3 input TIOCD3-B input*2 TMCI1-B input* Notes: 1. PO3-B output when the PPGS bit in PFCR3 is 1. 2. TIOCD3-B input/output when the TPUS bit in PFCR3 is 1. 3. TMCI1-B input when the TMRS bit in PFCR3 is 1. TPU channel 3 settings MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function Other than B'110 PWM mode 2 output B'110 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 582 of 1270 REJ09B0466-0100 Section 10 I/O Ports * P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bit TE in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P81DDR. TPU channel 3 settings TE P81DDR NDER1 Pin function TIOCB3-B output*2 0 P81 input 0 P81 output 3 (1) in table below 0 (2) in table below 1 1 1 PO1-B output*1 TxD3 output TIOCB3-B input*2 TMRI1-B input* Notes: 1. PO1-B output when the PPGS bit in PFCR3 is 1. 2. TIOCB3-B input/output when the TPUS bit in PFCR3 is 1. 3. TMRI1-B input when the TMRS bit in PFCR3 is 1. TPU channel 3 settings MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function Other than B'010 PWM mode 2 output B'010 Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 583 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.8 Port 9 Port 9 is an 8-bit input-only port that also has other functions. Port 9 has the following register. * Port 9 register (PORT9) 10.8.1 Port 9 Register (PORT9) PORT9 is an 8-bit read-only register that shows the pin states of port 9. PORT9 cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P97 P96 P95 P99 P93 P92 P91 P90 * Initial Value * * * * * * * * R/W R R R R R R R R Description The pin states are always read from this register. Bits 7, 6, and 3 to0 are reserved in the H8S/2424 Group. Determined by the states of pins P97 to P90. Rev. 1.00 Sep. 19, 2008 Page 584 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.8.2 Pin Functions Port 9 also functions as the pins for A/D converter analog inputs and D/A converter analog outputs. The correspondence between pins is as follows. (1) Pin Functions of H8S/2426 Group and H8S/2426R Group * P97/AN15_1 Pin function AN15_1 input * P96/AN14_1 Pin function AN14_1 input * P95/AN13_1/DA3 Pin function AN13_1 input DA3 output * P94/AN12_1/DA2 Pin function AN12_1 input DA2 output * P93/AN11_1 Pin function AN11_1 input * P92/AN10_1 Pin function AN10_1 input * P91/AN9_1 Pin function AN9_1 input * P90/AN8_1 Pin function AN8_1 input Rev. 1.00 Sep. 19, 2008 Page 585 of 1270 REJ09B0466-0100 Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group * P95/AN13_1/DA3 Pin function AN13_1 input DA3 output * P94/AN12_1/DA2 Pin function AN12_1 input DA2 output Rev. 1.00 Sep. 19, 2008 Page 586 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9 Port A Port A is an 8-bit I/O port that also has other functions. Port A has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. * * * * * * * * * Port A data direction register (PADDR) Port A data register (PADR) Port A register (PORTA) Port A pull-up MOS control register (PAPCR) Port A open-drain control register (PAODR) Port function control register 0 (PFCR0)(the H8S/2424 Group) Port function control register 1 (PFCR1) Port function control register 4 (PFCR4) Port function control register 5 (PFCR5) Rev. 1.00 Sep. 19, 2008 Page 587 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * Description * Modes 1 and 2 Pins PA4 to PA0 are address outputs. For pins PA7 to PA5, when the corresponding bit of A23E to A21E is set to 1, setting a PADDR bit to 1 makes the corresponding pin an address output, while clearing the bit to 0 makes the corresponding pin an input port. Clearing one of bits A23E to A21E to 0 makes the corresponding pin an I/O port, and its function can be switched with PADDR. Modes 7 (when EXPE = 1) and 4 When the corresponding bit of A23E to A16E is set to 1, setting a PADDR bit to 1 makes the corresponding pin an address output, while clearing the bit to 0 makes the corresponding pin an input port. Clearing one of bits A23E to A16E to 0 makes the corresponding pin an I/O port, and its function can be switched with PADDR. * Mode 7 (when EXPE = 0) Port A is an I/O port, and its pin functions can be switched with PADDR. Rev. 1.00 Sep. 19, 2008 Page 588 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit 7 6 5 4 3 2 1 0 Bit Name PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.9.3 Port A Register (PORTA) PORTA shows the pin states of port A. PORTA cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 * Initial Value * * * * * * * * R/W R R R R R R R R Description If this register is read while a PADDR bit is set to 1, the corresponding PADR value is read. If this register is read while a PADDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PA7 to PA0. Rev. 1.00 Sep. 19, 2008 Page 589 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.4 Port A Pull-Up MOS Control Register (PAPCR) PAPCR controls on/off of the input pull-up MOS for port A. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit 7 6 5 4 3 2 1 0 Bit Name PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When in an input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 10.9.5 Port A Open Drain Control Register (PAODR) PAODR specifies the output type of each port A pin. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR * Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When not specified for address output or CS7 output*, setting a PAODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PAODR bit to 0 makes the corresponding pin a CMOS output pin. Not supported by the H8S/2426 Group and the H8S/2426R Group Rev. 1.00 Sep. 19, 2008 Page 590 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.6 Pin Functions Port A pins also function as the pins for address outputs, interrupt inputs, SSU I/Os, SCI I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below. * PA7/A23/CS7*4/IRQ7-A/SSO0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, bit CS7E in PFCR0 (the H8S/2424 Group), bit A23E in PFCR1, bit PA7DDR, and bit ITS7 in ITSR of the interrupt controller. * Modes 1, 2, and 4 A23E CS7E* 4 0 0 Can be used as I/O port 0 PA7 input 1 PA7 output Input state 0 SSO0-B 2 input* Output state SSO0-B 3 output* 0 PA7 input 1 1 1 1 CS7 4 output* 0 PA7 input 1 A23 output SSU settings PA7DDR Pin function IRQ7-A interrupt input* * Mode 7 (EXPE = 1) A23E CS7E* 4 0 0 Can be used as I/O port 0 1 Input state 0 SSO0-B 2 input* Output state SSO0-B 3 output* 0 PA7 input 1 1 1 1 CS7 4 output* 0 1 SSU settings PA7DDR Pin function PA7 input PA7 output PA7 input A23 output IRQ7-A interrupt input* Rev. 1.00 Sep. 19, 2008 Page 591 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 (EXPE = 0) A23E CS7E* 4 0 Can be used as I/O port 0 PA7 input 1 PA7 output Input state 0 SSO0-B input* 2 SSU settings PA7DDR Pin function Output state SSO0-B output*3 IRQ7-A interrupt input*1 Notes: 1. IRQ7-A input when the ITS7 bit in ITSR is 0. 2. SSO0-B input when SSO0S1 and SSO0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000x1 or B'01x01. 3. SSO0-B output when SSO0S1 and SSO0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001xx, B'0101x, or B'10x1x. 4. Supported only by the H8S/2424 Group and not supported by the H8S/2426 and H8S/2426R Groups. SSO pin settings SSUMS BIDE MSS TE RE Pin state 0 1 Input 0 0 1 1 Input 0 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 Output Output Input Output Input Output Output Output Output Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 592 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PA6/A22/IRQ6-A/SSI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bit A22E in PFCR1, bits SSI0S1 and SSI0S0 in PFCR5, bit PA6DDR, and bit ITS6 in ITSR of the interrupt controller. * Modes 1, 2, and 4 A22E SSU settings PA6DDR Pin function Can be used as I/O port 0 PA6 input 1 PA6 output Input state 0 SSI0-B input*2 Output state SSI0-B output*3 1 0 PA6 input 1 A22 output IRQ6-A interrupt input* * Mode 7 EXPE A22E SSU settings Can be used as I/O port PA6DDR Pin function 0 PA6 input 1 0 Input state 0 Output state 0 1 1 1 0 Can be used as I/O port 0 PA6 input 1 Input state 0 Output state 1 PA6 SSI0-B SSI0-B PA6 A22 output input*2 output*3 input output PA6 SSI0-B SSI0-B output input*2 output*3 IRQ6-A interrupt input* Notes: 1. IRQ6-A input when the ITS6 bit in ITSR is 0. 2. SSI0-B input when SSI0S1 and SSI0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001x1 or B'10xx1. 3. SSI0-B output when SSI0S1 and SSI0S0 = B'01 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001x. Rev. 1.00 Sep. 19, 2008 Page 593 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSI pin settings SSUMS BIDE MSS TE RE Pin state 0 1 0 0 1 1 0 1 0 0 0 1 1 1 Input 0 1 0 1 0 0 1 0 1 1 1 0 0 1 Input 0 0 1 1 Input 0 1 Input 0 1 0 1 1 1 Input Output Output Input Legend: : Pin is not used by the SSU (can be used as I/O port) * PA5/A21/IRQ5-A/SSCK0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bit A21E in PFCR1, bits SSCK0S1 and SSCK0S0 in PFCR5, bit PA5DDR, and bit ITS5 in ITSR of the interrupt controller * Modes 1, 2, and 4 A21E SSU settings PA5DDR Pin function Can be used as I/O port 0 PA5 input 1 PA5 output 0 Input state 0 SSCK0-B input*2 Output state SSCK0-B output*3 2 1 0 PA5 input 1 A21 output IRQ5-A interrupt input*1 SSCK0-B input* Rev. 1.00 Sep. 19, 2008 Page 594 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 EXPE A21E SSU settings PA5DDR Pin function Can be used as I/O port 0 PA5 input 1 0 Input state 0 Output state 0 1 1 1 Can be used as I/O port 0 PA5 input 1 0 Input state 0 Output state 1 PA5 SSCK0-B SSCK0-B 2 3 output input* output* PA5 A21 input output PA5 SSCK0-B SSCK0-B 2 3 output input* output* IRQ5-A interrupt input* SSCK0-B input* 2 Notes: 1. IRQ5-A input when the ITS5 bit in ITSR is 0. 2. SSCK0-B input when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. 3. SSCK0-B output when SSCK0S1 and SSCK0S0 = B'00 in PFCR5, and SSUMS, MSS, and SCKS = B'x11. SSCK pin settings SSUMS MSS SCKS Pin state 0 0 1 Input 0 0 1 1 Output 0 0 1 Input 0 1 1 1 Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 595 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PA4/A20/IRQ4-A/SCS0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bit A20E in PFCR1, bit PA4DDR, and bit ITS4 in ITSR of the interrupt controller. Operating mode EXPE A20E SSU settings PA4DDR Pin function 1, 2 Can be used as I/O port 0 1 0 Input state 0 SCS0-B input*2 Output state SCS0-B output*3 1 4 1 0 1 A20 output PA4 input PA4 output PA4 input A20 output IRQ4-A interrupt input* Operating mode EXPE A20E SSU settings PA4DDR Pin function Can be used as I/O port 0 PA4 input 1 PA4 output 0 Input state 0 Output state 7 1 0 Can be used as I/O port 0 PA4 input 1 PA4 output Input state 0 Output state 0 PA4 input 1 1 A20 output SCS0-B SCS0-B 2 3 input* output* SCS0-B SCS0-B 2 3 input* output* 1 IRQ4-A interrupt input* Notes: 1. IRQ4-A input when the ITS4 bit in ITSR is 0. 2. SCSO-B input when SCS0S1 and SCS0S0 = B'01 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00xx, B'0101, or B'0110. 3. SCSO-B output when SCS0S1 and SCS0S0 = B'01 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011x. Rev. 1.00 Sep. 19, 2008 Page 596 of 1270 REJ09B0466-0100 Section 10 I/O Ports SCS pin settings SSUMS MSS CSS1 CSS0 Pin state 0 x x Input 0 0 1 Input 0 Automatic I/O 0 1 1 1 Output 1 x x x Legend: x: Don't care : Pin is not used by the SSU (can be used as I/O port) * PA3/A19/SCK4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit C/A in SMR_4 and bits CKE0 and CKE1 in SCR_4 of the SCI, bit A19E in PFCR1, bit SCK4S in PFCR4, and bit PA3DDR. Operating mode EXPE A19E CKE1 C/A CKE0 PA3DDR Pin function 1, 2 A19 output 0 PA3 input 0 1 PA3 output 0 1 SCK4-B output* 0 1 SCK4-B output* 0 1 SCK4-B input* 0 PA3 input 4 1 1 A19 output Rev. 1.00 Sep. 19, 2008 Page 597 of 1270 REJ09B0466-0100 Section 10 I/O Ports Operating mode EXPE A19E CKE1 C/A CKE0 PA3DDR Pin function 0 PA3 input 0 1 PA3 output 0 1 0 1 0 1 0 PA3 input 0 7 1 0 0 0 1 1 PA3 output SCK4-B output* 1 1 0 PA3 input 1 1 A19 output SCK4-B SCK4-B SCK4-B output* output* input* SCK4-B SCK4-B output* input* Note: * SCK4-B input/output when the SCK4S bit in PFCR4 is 1. * PA2/A18/RxD4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit RE in SCR_4 of the SCI, bit A18E in PFCR1, bit RXD4S in PFCR4, and bit PA2DDR. Operating mode EXPE A18E RE PA2DDR Pin function A18 output 0 PA2 input 0 1 PA2 output 0 1 RxD4-B input* 0 PA2 input 1 1 A18 output 0 PA2 input 0 1 PA2 output 0 1 0 0 1 PA2 0 1 0 1 1 1 A18 1, 2 4 7 RxD4-B PA2 input* RxD4-B PA2 input* input output input output Note: * RxD4-B input when the RXD4S bit in PFCR4 is 1. Rev. 1.00 Sep. 19, 2008 Page 598 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PA1/A17/TxD4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit TE in SCR_4 of the SCI, bit A17E in PFCR1, bit TXD4S in PFCR4, and bit PA1DDR. Operating mode EXPE A17E TE PA1DDR Pin function A17 output 0 PA1 input 0 1 PA1 0 1 TxD4-B 0 PA1 input 1 1 A17 output 0 PA1 input 0 1 PA1 0 1 0 0 1 PA1 0 1 0 1 1 1 A17 1, 2 4 7 TxD4-B PA1 TxD4-B PA1 output output* output output* input output output* input output Note: * TxD4-A output when the TXD4S bit in PFCR4 is 1. * PA0/A16 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit A16E in PFCR1, and bit PA0DDR. Operating mode EXPE A16E PA0DDR Pin function 1, 2 A16 output 0 PA0 input 0 1 PA0 output 0 PA0 input 4 1 1 A16 output 0 PA0 input 0 1 PA0 output 0 PA0 input 0 1 PA0 output 0 PA0 input 7 1 1 1 A16 output Rev. 1.00 Sep. 19, 2008 Page 599 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.9.7 Port A Input Pull-Up MOS States Port A has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used by pins PA7 to PA5 in modes 1 and 2, and by all pins in modes 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. Table 10.3 summarizes the input pull-up MOS states. Table 10.3 Input Pull-Up MOS States for Port A Mode 4 or 7 1 or 2 PA7 to PA0 PA7 to PA5 PA4 to PA0 Reset Off Hardware Standby Mode Off Software Standby Mode On/Off On/Off Off In Other Operations On/Off On/Off Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when in input port register state* and PAPCR = 1; otherwise off. Note: * Not available with SSU/SCI input Rev. 1.00 Sep. 19, 2008 Page 600 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10 Port B Port B is an 8-bit I/O port that also has other functions. Port B has the following registers. * * * * * Port B data direction register (PBDDR) Port B data register (PBDR) Port B register (PORTB) Port B pull-up MOS control register (PBPCR) Port B open drain control register (PBODR) 10.10.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * * Description * Modes 1 and 2 Port B pins are address outputs regardless of the PBDDR settings. Modes 7 (when EXPE = 1) and 4 Setting a PBDDR bit to 1 makes the corresponding pin an address output, while clearing a PBDDR bit to 0 makes the corresponding pin an input port. Mode 7 (when EXPE = 0) Port B is an I/O port, and its pin functions can be switched with PBDDR. Rev. 1.00 Sep. 19, 2008 Page 601 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10.2 Port B Data Register (PBDR) PBDR stores output data for the port B pins. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.10.3 Port B Register (PORTB) PORTB shows the pin states of port B. PORTB cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 * Initial Value * * * * * * * * R/W R R R R R R R R Description If this register is read while a PBDDR bit is set to 1, the corresponding PBDR value is read. If this register is read while a PBDDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PB7 to PB0. Rev. 1.00 Sep. 19, 2008 Page 602 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10.4 Port B Pull-Up MOS Control Register (PBPCR) PBPCR controls on/off of the input pull-up MOS for port B. PBPCR is valid in modes 4 and 7. Bit 7 6 5 4 3 2 1 0 Bit Name PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When in a input port register state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 10.10.5 Port B Open Drain Control Register (PBODR) PBODR specifies the output type of each port B pin. Bit 7 6 5 4 3 2 1 0 Bit Name PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When not specified for address output, setting a PBODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PBODR bit to 0 makes the corresponding pin a CMOS output pin. Rev. 1.00 Sep. 19, 2008 Page 603 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10.6 Pin Functions Port B pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below. * PB7/A15/TIOCB8/TCLKH The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOB3 to IOB0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), bits TPSC2 to TPSC0 in TCR_6 and TCR_11, and bit PB7DDR. Operating mode TPU channel 8 settings PB7DDR Pin function 1, 2 A15 output 0 PB7 input 4, 7 (EXPE = 1) 1 A15 output (1) in table below TIOCB8 output 7 (EXPE = 0) (2) in table below 0 PB7 input TCLKH input*2 1 PB7 output TIOCB8 input*1 TPU channel 8 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care Notes: 1. TIOCB8 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1. 2. TCLKH input when the setting for either TCR_6 or TCR_11 is TPSC2 to TPSC0 = B'111. TCLKH input when phase counting mode is set for channels 8 and 10. Rev. 1.00 Sep. 19, 2008 Page 604 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PB6/A14/TIOCA8 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOA3 to IOA0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), and bit PB6DDR. Operating mode TPU channel 8 settings PB6DDR Pin function 1, 2 A14 output 0 PB6 input 4, 7 (EXPE = 1) 1 A14 output (1) in table below TIOCA8 output 7 (EXPE = 0) (2) in table below 0 PB6 input 1 PB6 output 1 TIOCA8 input* TPU channel 8 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA8 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. TIOCB8 output disabled. Rev. 1.00 Sep. 19, 2008 Page 605 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PB5/A13/TIOCB7/TCLKG The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOB3 to IOB0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), bits TPSC2 to TPSC0 in TCR_6, TCR_8, TCR_10, and TCR_11, and bit PB5DDR. Operating mode TPU channel 7 settings PB5DDR Pin function 1, 2 A13 output 0 PB5 input 4, 7 (EXPE = 1) 1 A13 output (1) in table below TIOCB7 output 7 (EXPE = 0) (2) in table below 0 PB5 input 2 1 PB5 output TIOCB7 input*1 TCLKG input* TPU channel 7 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care Notes: 1. TIOCB7 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx. 2. TCLKG input when the setting for either TCR_6 or TCR_8 is TPSC2 to TPSC0 = B'111, or when the setting for either TCR_10 or TCR_11 is TPSC2 to TPSC0 = B'101. TCLKG input when phase counting mode is set for channels 8 and 10. Rev. 1.00 Sep. 19, 2008 Page 606 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PB4/A12/TIOCA7 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOA3 to IOA0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), and bit PB4DDR. Operating mode TPU channel 7 settings PB4DDR Pin function 1, 2 A12 output 0 PB4 input 4, 7 (EXPE = 1) 1 A12 output (1) in table below TIOCA7 output 7 (EXPE = 0) (2) in table below 0 PB4 input 1 PB4 output 1 TIOCA7 input* TPU channel 7 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA7 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. 2. TIOCB7 output disabled. Rev. 1.00 Sep. 19, 2008 Page 607 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PB3/A11/TIOCD6/TCLKF The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOD3 to IOD0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_8, and bit PB3DDR. Operating mode TPU channel 6 settings PB3DDR Pin function 1, 2 A11 output 0 PB3 input 4, 7 (EXPE = 1) 1 A11 output (1) in table below TIOCD6 output 7 (EXPE = 0) (2) in table below 0 PB3 input 2 1 PB3 output TIOCD6 input*1 TCLKF input* TPU channel 6 settings MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'0010 (2) (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'110 PWM mode 2 output B'110 Legend: x: Don't care Notes: 1. TIOCD6 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. 2. TCLKF input when the setting for any of TCR_6 to TCR_8 is TPSC2 to TPSC0 = B'101. TCLKF input when phase counting mode is set for channels 7 and 11. Rev. 1.00 Sep. 19, 2008 Page 608 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PB2/A10/TIOCC6/TCLKE The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOC3 to IOC0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_11, and bit PB2DDR. Operating mode TPU channel 6 settings PB2DDR Pin function 1, 2 A10 output 0 PB2 input 4, 7 (EXPE = 1) 1 A10 output (1) in table below TIOCC6 output 7 (EXPE = 0) (2) in table below 0 PB2 input 2 1 PB2 output TIOCC6 input*1 TCLKE input* TPU channel 6 settings MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR2 to CCLR0 Output function Other than B'101 B'101 PWM*3 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCC6 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2. TCLKE input when the setting for any of TCR_6 to TCR_11 is TPSC2 to TPSC0 = B'100. TCLKE input when phase counting mode is set for channels 7 and 11. 3. TIOCD6 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_6. Rev. 1.00 Sep. 19, 2008 Page 609 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PB1/A9/TIOCB6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOB3 to IOB0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB1DDR. Operating mode TPU channel 6 settings PB1DDR Pin function 1, 2 A9 output 0 PB1 input 4, 7 (EXPE = 1) 1 A9 output (1) in table below TIOCB6 output 7 (EXPE = 0) (2) in table below 0 PB1 input 1 PB1 output TIOCB6 input* TPU channel 6 settings MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'0010 (2) (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'010 PWM mode 2 output B'010 Legend: x: Don't care Note: * TIOCB6 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx. Rev. 1.00 Sep. 19, 2008 Page 610 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PB0/A8/TIOCA6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOA3 to IOA0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB0DDR. Operating mode TPU channel 6 settings PB0DDR Pin function 1, 2 A8 output 0 PB0 input 4, 7 (EXPE = 1) 1 A8 output (1) in table below TIOCA6 output 7 (EXPE = 0) (2) in table below 0 PB0 input 1 PB0 output 1 TIOCA6 input* TPU channel 6 settings MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR2 to CCLR0 Output function Other than B'001 B'001 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA6 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. 2. TIOCB6 output disabled. Rev. 1.00 Sep. 19, 2008 Page 611 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.10.7 Port B Input Pull-Up MOS States Port B has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.4 summarizes the input pull-up MOS states. Table 10.4 Input Pull-Up MOS States for Port B Mode 1 or 2 4 or 7 Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when in an input port state 0 and PBPCR = 1; otherwise off. Rev. 1.00 Sep. 19, 2008 Page 612 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11 Port C Port C is an 8-bit I/O port that also has other functions. Port C has the following registers. * * * * * Port C data direction register (PCDDR) Port C data register (PCDR) Port C register (PORTC) Port C pull-up MOS control register (PCPCR) Port C open drain control register (PCODR) 10.11.1 Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * * Description * Modes 1 and 2 Port C pins are address outputs regardless of the PCDDR settings. Modes 7 (when EXPE = 1) and 4 Setting a PCDDR bit to 1 makes the corresponding pin an address output, while clearing a PCDDR to 0 makes the corresponding pin an input port. Mode 7 (when EXPE = 0) Port C is an I/O port, and its pin functions can be switched with PCDDR. Rev. 1.00 Sep. 19, 2008 Page 613 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit 7 6 5 4 3 2 1 0 Bit Name PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.11.3 Port C Register (PORTC) PORTC shows the pin states of port C. PORTC cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 * Initial Value * * * * * * * * R/W R R R R R R R R Description If this register is read while a PCDDR bit is set to 1, the corresponding PCDR value is read. If this register is read while a PCDDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PC7 to PC0. Rev. 1.00 Sep. 19, 2008 Page 614 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11.4 Port C Pull-Up MOS Control Register (PCPCR) PCPCR controls on/off of the input pull-up MOS for port C. PCPCR is valid in modes 4 and 7. Bit 7 6 5 4 3 2 1 0 Bit Name PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When in a input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 10.11.5 Port C Open Drain Control Register (PCODR) PCODR specifies the output type of each port C pin. Bit 7 6 5 4 3 2 1 0 Bit Name PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When not specified for address output, setting a PCODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PCODR bit to 0 makes the corresponding pin a CMOS output pin. Rev. 1.00 Sep. 19, 2008 Page 615 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11.6 Pin Functions Port C pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below. * PC7/A7/TIOCB11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOB3 to IOB0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC7DDR. Operating mode TPU channel 11 settings PC7DDR Pin function 1, 2 A7 output 0 PC7 input 4, 7 (EXPE = 1) 1 A7 output (1) in table below TIOCB11 output 7 (EXPE = 0) (2) in table below 0 PC7 input 1 PC7 output TIOCB11 input* TPU channel 11 settings MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'0010 (2) (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care Note: * TIOCB11 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1. Rev. 1.00 Sep. 19, 2008 Page 616 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PC6/A6/TIOCA11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOA3 to IOA0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC6DDR. Operating mode TPU channel 11 settings PC6DDR Pin function 1, 2 A6 output 0 PC6 input 4, 7 (EXPE = 1) 1 A6 output (1) in table below TIOCA11 output 7 (EXPE = 0) (2) in table below 0 PC6 input 1 PC6 output 1 TIOCA11 input* TPU channel 11 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (2) B'0010 (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA11 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. TIOCB11 output disabled. Rev. 1.00 Sep. 19, 2008 Page 617 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PC5/A5/TIOCB10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOB3 to IOB0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC5DDR. Operating mode TPU channel 10 settings PC5DDR Pin function 1, 2 A5 output 0 PC5 input 4, 7 (EXPE = 1) 1 A5 output (1) in table below TIOCB10 output 7 (EXPE = 0) (2) in table below 0 PC5 input 1 PC5 output TIOCB10 input* TPU channel 10 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 Legend: x: Don't care Note: * TIOCB10 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx. Rev. 1.00 Sep. 19, 2008 Page 618 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PC4/A4/TIOCA10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOA3 to IOA0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC4DDR. Operating mode TPU channel 10 settings PC4DDR Pin function 1, 2 A4 output 0 PC4 input 4, 7 (EXPE = 1) 1 A4 output (1) in table below TIOCA10 output 7 (EXPE = 0) (2) in table below 0 PC4 input 1 PC4 output 1 TIOCA10 input* TPU channel 10 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR1, CCLR0 Output function Other than B'01 B'01 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA10 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. 2. TIOCB10 output disabled. Rev. 1.00 Sep. 19, 2008 Page 619 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PC3/A3/TIOCD9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOD3 to IOD0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC3DDR. Operating mode TPU channel 9 settings PC3DDR Pin function 1, 2 A3 output 0 PC3 input 4, 7 (EXPE = 1) 1 A3 output (1) in table below TIOCD9 output 7 (EXPE = 0) (2) in table below 0 PC3 input 1 PC3 output TIOCD9 input* TPU channel 9 settings MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'0010 (2) (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'110 PWM mode 2 output B'110 Legend: x: Don't care Note: * TIOCD9 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. Rev. 1.00 Sep. 19, 2008 Page 620 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PC2/A2/TIOCC9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOC3 to IOC0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC2DDR. Operating mode TPU channel 9 settings PC2DDR Pin function 1, 2 A2 output 0 PC2 input 4, 7 (EXPE = 1) 1 A2 output (1) in table below TIOCC9 output 7 (EXPE = 0) (2) in table below 0 PC2 input 1 PC2 output 1 TIOCC9 input* TPU channel 9 settings MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR2 to CCLR0 Output function Other than B'101 B'101 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCC9 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2. TIOCD9 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_9. Rev. 1.00 Sep. 19, 2008 Page 621 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PC1/A1/TIOCB9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOB3 to IOB0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC1DDR. Operating mode TPU channel 9 settings PC1DDR Pin function 1, 2 A1 output 0 PC1 input 4, 7 (EXPE = 1) 1 A1 output (1) in table below TIOCB9 output 7 (EXPE = 0) (2) in table below 0 PC1 input 1 PC1 output TIOCB9 input* TPU channel 9 settings MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'0010 (2) (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'010 PWM mode 2 output B'010 Legend: x: Don't care Note: * TIOCB9 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx. Rev. 1.00 Sep. 19, 2008 Page 622 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PC0/A0/TIOCA9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOA3 to IOA0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC0DDR. Operating mode TPU channel 9 settings PC0DDR Pin function 1, 2 A0 output 0 PC0 input 4, 7 (EXPE = 1) 1 A0 output (1) in table below TIOCA9 output 7 (EXPE = 0) (2) in table below 0 PC0 input 1 PC0 output 1 TIOCA9 input* TPU channel 9 settings MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000, B'0100, B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0001 to B'0011, B'0101 to B'0111 Output compare output CCLR2 to CCLR0 Output function Other than B'001 B'001 PWM*2 mode PWM mode 1 output 2 output Legend: x: Don't care Notes: 1. TIOCA9 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. 2. TIOCB9 output disabled. Rev. 1.00 Sep. 19, 2008 Page 623 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.11.7 Port C Input Pull-Up MOS States Port C has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.5 summarizes the input pull-up MOS states. Table 10.5 Input Pull-Up MOS States for Port C Mode 1 or 2 4 or 7 Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when in an input port state and PCPCR = 1; otherwise off. Rev. 1.00 Sep. 19, 2008 Page 624 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.12 Port D Port D is an 8-bit I/O port that also has other functions. Port D has the following registers. * * * * * Port D data direction register (PDDDR) Port D data register (PDDR) Port D register (PORTD) Port D pull-up MOS control register (PDPCR) Port D open drain control register (PDODR) 10.12.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * Description * Modes 7 (when EXPE = 1), 1, 2, and 4 Port D is automatically designated for data input/output. Mode 7 (when EXPE = 0) Port D is an I/O port, and its pin functions can be switched with PDDDR. Rev. 1.00 Sep. 19, 2008 Page 625 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.12.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit 7 6 5 4 3 2 1 0 Bit Name PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.12.3 Port D Register (PORTD) PORTD shows the pin states of port D. PORTD cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 * Initial Value * * * * * * * * R/W R R R R R R R R Description If this register is read while a PDDDR bit is set to 1, the corresponding PDDR value is read. If this register is read while a PDDDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PD7 to PD0. Rev. 1.00 Sep. 19, 2008 Page 626 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.12.4 Port D Pull-Up MOS Control Register (PDPCR) PDPCR controls on/off of the input pull-up MOS for port D. PDPCR is valid in mode 7. Bit 7 6 5 4 3 2 1 0 Bit Name PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When PDDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 10.12.5 Port D Open Drain Control Register (PDODR) PDODR specifies the output type of each port D pin. Bit 7 6 5 4 3 2 1 0 Bit Name PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When not specified for data output, setting a PDODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PDODR bit to 0 makes the corresponding pin a CMOS output pin. Rev. 1.00 Sep. 19, 2008 Page 627 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.12.6 Pin Functions Port D pins also function as the pins for data I/Os. The correspondence between the register specification and the pin functions is shown below. * PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, and bit PDnDDR. Operating mode EXPE PDnDDR Pin function Legend: n = 7 to 0 1, 2, 4 Data I/O 0 PDn input 0 1 PDn output 7 1 Data I/O 10.12.7 Port D Input Pull-Up MOS States Port D has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in mode 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In mode 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.6 summarizes the input pull-up MOS states. Table 10.6 Input Pull-Up MOS States for Port D Mode 1, 2, or 4 7 Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when PDDDR = 0 and PDPCR = 1; otherwise off. Rev. 1.00 Sep. 19, 2008 Page 628 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.13 Port E Port E is an 8-bit I/O port that also has other functions. Port E has the following registers. * * * * * Port E data direction register (PEDDR) Port E data register (PEDR) Port E register (PORTE) Port E pull-up MOS control register (PEPCR) Port E open drain control register (PEODR) 10.13.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W * Description * Modes 1, 2, and 4 When 8-bit bus mode is selected, port E is an I/O port, and its pin functions can be switched with PEDDR. When 16-bit bus mode is selected, port E is designated for data input/output. For details on 8-bit and 16-bit bus modes, see section 6, Bus Controller (BSC). Mode 7 (when EXPE = 1) When 8-bit bus mode is selected, port E is an I/O port. Setting a PEDDR bit to 1 makes the corresponding pin an output port, while clearing a PEDDR bit to 0 makes the corresponding pin an input port. When 16-bit bus mode is selected, port E is designated for data input/output. * Mode 7 (when EXPE = 0) Port E is an I/O port, and its pin functions can be switched with PEDDR. Rev. 1.00 Sep. 19, 2008 Page 629 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.13.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit 7 6 5 4 3 2 1 0 Bit Name PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.13.3 Port E Register (PORTE) PORTE shows the pin states of port E. PORTE cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 * Initial Value * * * * * * * * R/W R R R R R R R R Description If this register is read while a PEDDR bit is set to 1, the corresponding PEDR value is read. If this register is read while a PEDDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PE7 to PE0. Rev. 1.00 Sep. 19, 2008 Page 630 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.13.4 Port E Pull-Up MOS Control Register (PEPCR) PEPCR controls on/off of the input pull-up MOS for port E. PEPCR is valid in 8-bit bus mode. Bit 7 6 5 4 3 2 1 0 Bit Name PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When PEDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 10.13.5 Port E Open Drain Control Register (PEODR) PEODR specifies the output type of each port E pin. Bit 7 6 5 4 3 2 1 0 Bit Name PE7ODR PE6ODR PE5ODR PE4ODR PE3ODR PE2ODR PE1ODR PE0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When not specified for data output, setting a PEODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PEODR bit to 0 makes the corresponding pin a CMOS output pin. Rev. 1.00 Sep. 19, 2008 Page 631 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.13.6 Pin Functions Port E pins also function as the pins for data I/Os. The correspondence between the register specification and the pin functions is shown below. * PE7/D7, PE6/D6, PE5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0 The pin function is switched as shown below according to the combination of the operating mode, bus mode, bit EXPE, and bit PEnDDR. Operating mode Bus mode 1, 2, 4 All areas are 8-bit space 0 PEn input 1 PEn output At least one area is 16-bit space Data I/O 0 PEn input 7 All areas are 8-bit space 1 1 PEn output 0 PEn input 1 PEn output At least one area is 16-bit space 1 Data I/O EXPE PEnDDR Pin function Legend: n = 7 to 0 0 10.13.7 Port E Input Pull-Up MOS States Port E has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in 8-bit bus mode. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.7 summarizes the input pull-up MOS states. Table 10.7 Input Pull-Up MOS States for Port E Mode 1, 2, or 4 8-bit bus 16-bit bus Reset Off Hardware Standby Mode Off Software Standby Mode On/Off Off In Other Operations On/Off Off Legend: Off: Input pull-up MOS is always off. On/Off: Input pull-up MOS is on when PEDDR = 0 and PEPCR = 1; otherwise off. Rev. 1.00 Sep. 19, 2008 Page 632 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.14 Port F Port F is an 8-bit I/O port that also has other functions. Port F has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. * * * * * * * * Port F data direction register (PFDDR) Port F data register (PFDR) Port F register (PORTF) Port function control register 0 (PFCR0) Port function control register 2 (PFCR2) Port function control register 4 (PFCR4) Port function control register 5 (PFCR5) Port F open drain control register (PFODR) Rev. 1.00 Sep. 19, 2008 Page 633 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.14.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Initial Value 1/0* 0 0 0 0 0 0 0 R/W W W W W W W W W Description * Modes 7 (when EXPE = 1), 1, 2, and 4 Pin PF7 functions as the output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pin PF6 functions as the AS output pin when the ASOE bit is set to 1. When the ASOE bit is cleared to 0, pin PF6 is an I/O port and its function can be switched with PF6DDR. Pins PF5 and PF4 are automatically designated as bus control outputs (RD and HWR). Pin PF3 functions as the LWR output pin when the LWROE bit is set to 1. When the LWROE bit is cleared to 0, pin PF3 is an I/O port and its function can be switched with PF3DDR. Pins PF2 to PF0 function as bus control input/output pins (LCAS, UCAS, and WAIT) when the appropriate bus controller settings are made. Otherwise, these pins are output ports when the corresponding PFDDR bits are set to 1 and are input ports when the bits are cleared to 0. * Mode 7 (when EXPE = 0) Pin PF7 functions as the output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pins PF6 to PF0 are I/O ports, and their functions can be switched with PFDDR. Rev. 1.00 Sep. 19, 2008 Page 634 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.14.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit 7 6 5 4 3 2 1 0 Bit Name PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.14.3 Port F Register (PORTF) PORTF shows the pin states of port F. PORTF cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 * Initial Value * * * * * * * * R/W R R R R R R R R Description If this register is read while a PFDDR bit is set to 1, the corresponding PFDR value is read. If this register is read while a PFDDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PF7 to PF0. Rev. 1.00 Sep. 19, 2008 Page 635 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.14.4 Port F Open Drain Control Register (PFODR) PFODR specifies the output type of each port F pin. Bit 7 6 5 4 3 2 1 0 Bit Name PF7ODR PF6ODR PF5ODR PF4ODR PF3ODR PF2ODR PF1ODR PF0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When not specified for , AS, AH, RD, HWR, LWR, LCAS, UCAS, DQML, DQMU, CS5, CS6, or OE-A output, setting a PFODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PFODR bit to 0 makes the corresponding pin a CMOS output pin. 10.14.5 Pin Functions Port F pins also function as the pins for SSU I/Os, A/D converter inputs, interrupt inputs, bus control signal I/Os, and system clock outputs. The correspondence between the register specification and the pin functions is shown below. * PF7/ The pin function is switched as shown below according to bit PF7DDR. Operating mode PF7DDR Pin function 0 PF7 input 1, 2, 4, 7 1 output Rev. 1.00 Sep. 19, 2008 Page 636 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PF6/AS/AH The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit MPXE in MPXCR of the bus controller, bit ASOE in PFCR2, and bit PF6DDR. Operating mode EXPE ASOE PF6DDR Pin function Note: * 1 AS/AH* output 0 PF6 input 1, 2, 4 0 1 PF6 output 0 PF6 input 0 1 PF6 output 1 AS/AH* output 0 PF6 input 7 1 0 1 PF6 output AH output when MPXE = 1, and AS output when MPXE = 0. * PF5/RD The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, and bit PF5DDR. Operating mode EXPE PF5DDR Pin function 1, 2, 4 RD output 0 PF5 input 0 1 PF5 output 7 1 RD output * PF4/HWR The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, and bit PF4DDR. Operating mode EXPE PF4DDR Pin function 1, 2, 4 HWR output 0 PF4 input 0 1 PF4 output 7 1 HWR output Rev. 1.00 Sep. 19, 2008 Page 637 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PF3/LWR/SSO0-C The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bit LWROE in PFCR2, bits SSOS1 and SSOS0 in PFCR5, and bit PF3DDR. Operating mode LWROE SSU settings PF3DDR Pin function 1 LWR output Can be used as I/O port 0 PF3 input 1 PF3 output 1, 2, 4, 7 (EXPE = 1) 0 Input state 0 Output state Can be used as I/O port 0 PF3 input 1 7 (EXPE = 0) 0 Input state 0 Output state SSO0-C SSO0-C input*1 output*2 PF3 SSO0-C SSO0-C output input*1 output*2 Notes: 1. SSO0-C input when SSO0S1 and SSO0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'000x1 or B'01x01. 2. SSO0-C output when SSO0S1 and SSO0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0011x, B'01x10, or B'10x1x. SSO pin settings SSUMS BIDE MSS TE RE Pin state 0 1 Input 0 0 1 1 Input 0 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 Output Output Input Output Input Output Output Output Output Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 638 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PF2/LCAS/DQML/IRQ15-A/SSI0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits SSI0S1 and SSI0S0 in PFCR5, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR. * Modes 1, 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any DRAM/ synchronous DRAM space area is 16-bit bus space LCAS output 3 DQML* output All DRAM/synchronous DRAM space areas are 8-bit bus space, or areas 2 to 5 are all normal space SSU settings PF2DDR Pin function Can be used as I/O port 0 PF2 input 1 Input state 0 2 Output state SSI0-C output*3 PF2 output SSI0-C input* 1 IRQ15-A interrupt input* * Mode 7 (EXPE = 0) Areas 2 to 5 SSU settings PF2DDR Pin function Can be used as I/O port 0 PF2 input 1 PF2 output Input state 0 SSI0-C input* 1 2 Output state SSI0-C output*3 IRQ15-A interrupt input* Notes: 1. IRQ15 input when the ITS15 bit in ITSR is 0. 2. SSI0-C input when SSI0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001x1 or B'10xx1. 3. SSI0-C output when SSI0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001x. Rev. 1.00 Sep. 19, 2008 Page 639 of 1270 REJ09B0466-0100 Section 10 I/O Ports SSI pin settings SSUMS BIDE MSS TE RE Pin state 0 1 0 0 1 1 0 1 0 0 0 1 1 1 Input 0 1 0 1 0 0 1 0 1 1 1 0 0 1 Input 0 0 1 1 Input 0 1 Input 0 1 0 1 1 1 Input Output Output Input Legend: : Pin is not used by the SSU (can be used as I/O port) * PF2/CS6/LCAS/SSI0-C (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS6E in PFCR0, bits SSI0S1 and SSI0S0 in PFCR5, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR. * Modes 1, 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any DRAM/ synchronous DRAM space area is 16-bit bus space LCAS output Can be used as I/O port 0 PF2 input 1 PF2 output All DRAM/synchronous DRAM space areas are 8-bit bus space, or areas 2 to 5 are all normal space CS6E SSU settings PF2DDR Pin function 0 Input state 0 SSI0-C input*1 Output state SSI0-C output*2 0 PF2 input 1 1 CS6 output Rev. 1.00 Sep. 19, 2008 Page 640 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 (EXPE = 0) Areas 2 to 5 CS6E SSU settings PF2DDR Pin function Can be used as I/O port 0 PF2 input 1 PF2 output Input state 0 SSI0-C input* 1 Output state SSI0-C output*2 Notes: 1. SSI0-C input when SSI0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'001x1 or B'10xx1. 2. SSI0-C output when SSI0S1 and SSI0S0 = B'10 in PFCR5, and SSUMS, BIDE, MSS, TE, and RE = B'0001x. SSI pin settings SSUMS BIDE MSS TE RE Pin state 0 1 0 0 1 1 0 0 1 0 1 0 1 1 Input 0 1 0 1 0 0 1 1 0 1 1 0 0 1 Input 0 0 1 1 Input 1 0 1 0 1 Input 0 1 1 Input Output Output Input Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 641 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PF1/UCAS/DQMU/IRQ14-A/SSCK0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit PF1DDR. * Modes 1, 2, 4, and 7 (EXPE = 1) Areas 2 to 5 Any of areas 2 to 5 is DRAM/synchronous DRAM space UCAS output DQMU*3 output Areas 2 to 5 are all normal space SSU settings PF1DDR Pin function Can be used as I/O port 0 PF1 input 1 PF1 output Input state 0 SSCK0-C input*2 1 Output state SSCK0-C output*3 IRQ14-A interrupt input* * Mode 7 (EXPE = 0) Areas 2 to 5 SSU settings PF1DDR Pin function Can be used as I/O port 0 PF1 input 1 PF1 output Input state 0 SSCK0-C input* 2 Output state SSCK0-C output*3 IRQ14-A interrupt input*1 Notes: 1. IRQ14 input when the ITS14 bit in ITSR is 0. 2. SSCK0-C input when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. 3. SSCK0-C output when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'x11. SSCK pin settings SSUMS MSS SCKS Pin state 0 0 1 Input 0 0 1 1 Output 0 0 1 Input 0 1 1 1 Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 642 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PF1/CS5/UCAS/SSCK0-C (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS5E in PFCR0, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit PF1DDR. * Modes 2, 4, and 7 (EXPE = 1) Areas 2 to 5 CS5E SSU settings PF1DDR Pin function Any of areas 2 to 5 is DRAM space UCAS output Can be used as I/O port 0 PF1 input 1 PF1 output Areas 2 to 5 are all normal space 0 Input state 0 SSCK0-C 1 input* Output state SSCK0-C output*2 0 PF1 input 1 1 CS5 output * Mode 7 (EXPE = 0) Areas 2 to 5 CS5E SSU settings PF1DDR Pin function Can be used as I/O port 0 PF1 input 1 PF1 output Input state 0 SSCK0-C input* 1 Output state SSCK0-C output*2 Notes: 1. SSCK0-C input when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'001 or B'101. 2. SSCK0-C output when SSCK0S1 and SSCK0S0 = B'10 in PFCR5, and SSUMS, MSS, and SCKS = B'x11. SSCK pin settings SSUMS MSS SCKS Pin state 0 0 1 Input 0 0 1 1 Output 0 0 1 Input 0 1 1 1 Output Legend: : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 643 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PF0/WAIT-A/ADTRG0-B/SCS0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR. * Modes 1, 2, 4, and 7 (EXPE = 1) WAITE SSU settings PF0DDR Pin function Can be used as I/O port 0 PF0 input 1 PF0 output 0 Input state 0 SCS0-C input* 3 1 Output state SCS0-C output* 1 4 WAIT-A input*2 ADTRG0-B input* * Mode 7 (EXPE = 0) WAITE SSU settings PF0DDR Pin function Can be used as I/O port 0 PF0 input 1 PF0 output ADTRG0-B input*1 Notes: 1. ADTRG0-B input when the ADTRG0S bit in PFCR4 is 1, TRGS1 = TRGS0 = 0, and EXTRGS = 1 2. WAIT-A input when the WAITS bit in PFCR4 is 0. 3. SCSO-C input when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00xx, B'0101, or B'0110. 4. SCSO-C output when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011x. Input state 0 SCS0-C input* 3 Output state SCS0-C output*4 Rev. 1.00 Sep. 19, 2008 Page 644 of 1270 REJ09B0466-0100 Section 10 I/O Ports SCS pin settings SSUMS MSS CSS1 CSS0 Pin state 0 x x Input 0 0 1 Input 0 Automatic I/O 0 1 1 1 Output 1 x x x Legend: x: Don't care : Pin is not used by the SSU (can be used as I/O port) * PF0/WAIT-A/ADTRG0-B/SCS0-C/OE-A (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, bit OEE in DRAMCR, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bit OES in PFCR2, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR. * Modes 1, 2, 4, and 7 (EXPE = 1) OEE RMTS2 to RMTS0 0 1 Areas 2 to 5 are DRAM space WAITE SSU settings Can be used as I/O port PF0DDR Pin function 0 PF0 input 1 PF0 output 0 Input state 0 Output state 0 PF0 input 1 Can be used as I/O port 1 PF0 output 1 0 Input state 0 Output state 1 OE-A output SCS0-C SCS0-C WAIT-A input*2 output*4 input*3 SCS0-C SCS0-C WAIT-A input*2 output*4 input*3 ADTRG0-B input* Rev. 1.00 Sep. 19, 2008 Page 645 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 (EXPE = 0) OEE Area 2 WAITE SSU settings PF0DDR Pin function 0 PF0 input 1 PF0 output ADTRG0-B input*1 Notes: 1. ADTRG0-B input when the ADTRG0S bit in PFCR4 is 1, TRGS1 = TRGS0 = 0, and EXTRGS = 1 2. WAIT-A input when the WAITS bit in PFCR4 is 0. 3. SCSO-C input when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'00xx, B'0101, or B'0110. 4. SCSO-C output when SCS0S1 and SCS0S0 = B'10 in PFCR5, and SSUMS, MSS, CSS1, and CSS0 = B'011x. SCS pin settings SSUMS MSS CSS1 CSS0 Pin state 0 x x Input 0 0 1 Input 0 Automatic I/O 0 1 1 1 Output 1 x x x Input state 0 SCS0-C input* 2 Output state SCS0-C output*4 Legend: x: Don't care : Pin is not used by the SSU (can be used as I/O port) Rev. 1.00 Sep. 19, 2008 Page 646 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.15 Port G Port G is a 7-bit I/O port that also has other functions. Port G has the following registers. * * * * * * Port G data direction register (PGDDR) Port G data register (PGDR) Port G register (PORTG) Port function control register 0 (PFCR0) Port function control register 4 (PFCR4) Port G open drain control register (PGODR) 10.15.1 Port G Data Direction Register (PGDDR) The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Initial Value 0 0 0 0 0 0 0 1/0* R/W W W W W W W W Description Reserved * Modes 7 (when EXPE = 1), 1, 2, and 4 Pins PG6 to PG4 function as bus control input/output pins (BREQO, BACK, and BREQ) when the appropriate bus controller settings are made. Otherwise, these pins are I/O ports, and their functions can be switched with PGDDR. When the CS output enable bits (CS3E to CS0E) are set to 1, pins PG3 to PG0 function as CS output pins when the corresponding PGDDR bit is set to 1, and as input ports when the bit is cleared to 0. When the CS output enable bits (CS3E to CS0E) are cleared to 0, pins PG3 to PG0 are I/O ports, and their functions can be switched with PGDDR. * Mode 7 (when EXPE = 0) Pins PG6 to PG0 are I/O ports, and their functions can be switched with PGDDR. Note: * PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7. Rev. 1.00 Sep. 19, 2008 Page 647 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.15.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit 7 Bit Name Initial Value 0 R/W Description Reserved This bit is always read as 0, and cannot be modified. 6 5 4 3 2 1 0 PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.15.3 Port G Register (PORTG) PORTG shows the pin states of port G. PORTG cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PG6 PG5 PG4 PG3 PG2 PG1 PG0 * Initial Value Undefined * * * * * * * R/W R R R R R R R Description Reserved If this bit is read, it will return an undefined value. If this register is read while a PGDDR bit is set to 1, the corresponding PGDR value is read. If this register is read while a PGDDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PG6 to PG0. Rev. 1.00 Sep. 19, 2008 Page 648 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.15.4 Port G Open Drain Control Register (PGODR) PGODR specifies the output type of each port G pin. Bit 7 Bit Name Initial Value 0 R/W Description Reserved This bit is always read as 0. Only the initial value should be written to this bit. 6 5 4 3 2 1 0 PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W When not specified for BACK-A, BREQO-A, CS0, CS1, CS2, CS3, CS4, RAS2, RAS3, RAS, or CAS output, setting a PGODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PGODR bit to 0 makes the corresponding pin a CMOS output pin. Rev. 1.00 Sep. 19, 2008 Page 649 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.15.5 Pin Functions Port G pins also function as the pins for JTAG inputs and bus control signal I/Os. The correspondence between the register specification and the pin functions is shown below. * PG6/BREQ-A/TDI*1 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQS in PFCR4, and bit PG6DDR. Operating mode EXPE BRLE BREQS PG6DDR Pin function 1, 2, 4 BRLE = 0 or BRLE = 1 and BREQS = 1 0 PG6 input 1 PG6 output BRLE = 1 and BREQS = 0 BREQ-A input 0 PG6 input 0 7 1 BRLE = 0 or BRLE = 1 and BREQS = 1 1 PG6 output 0 PG6 input 1 PG6 output BRLE = 1 and BREQS = 0 BREQ-A input TDI input*2 Notes: 1. Supported only in the 145-pin package. 2. TDI input when BSCANE pin = 1 in the 145-pin package. Rev. 1.00 Sep. 19, 2008 Page 650 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PG5/BACK-A/TMS*1 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BACKS in PFCR4, and bit PG5DDR. Operating mode EXPE BRLE BACKS PG5DDR Pin function 1, 2, 4 BRLE = 0 or BRLE = 1 and BACKS = 1 0 PG5 input 1 PG5 output BRLE = 1 and BACKS = 0 BACK-A output 0 PG5 input 0 7 1 BRLE = 0 or BRLE = 1 and BACKS = 1 1 PG5 output 2 BRLE = 1 and BACKS = 0 BACK-A output 0 PG5 input 1 PG5 output TMS input* Notes: 1. Supported only in the 145-pin package. 2. TMS input when BSCANE pin = 1 in the 145-pin package. * PG4/BREQO-A/CS4*1/TCK*2 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQOE, bit BREQOS in PFCR4, and bit PG4DDR. * Modes 1, 2, 4, and 7 (EXPE = 1) BRLE BREQOE BREQOS CS4E PG4DDR Pin function 0 PG4 input 0 1 PG4 output 0 1 CS4 output*1 0 PG4 input 1 BREQOE = 0 or BREQOE = 1 and BREQOS = 1 0 1 PG4 output 3 BREQO = 1 and BREQOS = 0 BREQO-A output 1 CS4 output*1 TCK input* Rev. 1.00 Sep. 19, 2008 Page 651 of 1270 REJ09B0466-0100 Section 10 I/O Ports * Mode 7 (EXPE = 0) BRLE BREQOE BREQOS CS4E PG4DDR Pin function 0 PG4 input 0 1 PG4 output TCK input*3 Notes: 1. Not supported in the H8S/2426 Group and H8S/2426R Group. 2. Supported only in the 145-pin package. 3. TCK input when BSCANE pin = 1 in the 145-pin package. 1 CS4 output*1 * PG3/CS3/RAS3/CAS* The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS3E in PFCR0, and bit PG3DDR. Operating mode EXPE CS3E RMTS2 to RMTS0 0 Area 3 is in normal space 1 Area 3 Areas 2 to 5 is in space are in DRAM* space PG3DDR Pin function 0 PG3 1 PG3 0 PG3 1 CS3 RAS3 output CAS* output 0 PG3 1 PG3 0 PG3 1 PG3 0 PG3 1 CS3 RAS3 DRAM synchronous 0 0 1 1 Area 3 is in Area 3 Areas 2 to 5 normal space is in space are in DRAM* space CAS* output DRAM synchronous 1, 2, 4 7 input output input output input output input output input output output Note: * Not supported in the H8S/2426 Group and H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 652 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PG2/CS2/RAS2/RAS* The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS2E in PFCR0, and bit PG2DDR. Operating mode EXPE CS2E RMTS2 to RMTS0 0 Area 2 is in normal space 1 Area 2 Areas 2 to 5 is in space are in DRAM* space PG2DDR Pin function 0 PG2 1 PG2 0 PG2 1 CS2 RAS2 RAS* output 0 PG2 1 PG2 0 PG2 1 PG2 0 PG2 1 CS2 RAS2 DRAM synchronous 0 0 1 1 Area 2 is in Area 2 Areas 2 to 5 normal space is in space are in DRAM* space RAS* output DRAM synchronous 1, 2, 4 7 input output input output output input output input output input output output Note: * Not supported in the H8S/2426 Group and H8S/2424 Group. * PG1/CS1, PG0/CS0 The pin function is switched as shown below according to the combination of the operating mode, bit CSnE in PFCR0, and bit PGnDDR. Operating mode EXPE CSnE PGnDDR Pin function Legend: n = 1 or 0 0 PGn input 0 1 PGn output 0 PGn input 1, 2, 4 1 1 CSn output 0 PGn input 0 1 PGn output 0 PGn input 0 1 PGn output 0 PGn input 7 1 1 1 CSn output Rev. 1.00 Sep. 19, 2008 Page 653 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.16 Port H Note: Port H is not supported in the H8S/2424 Group. Port H is a 4-bit I/O port that also has other functions. Port H has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. * * * * * * Port H data direction register (PHDDR) Port H data register (PHDR) Port H register (PORTH) Port function control register 0 (PFCR0) Port function control register 2 (PFCR2) Port H open drain control register (PHODR) 10.16.1 Port H Data Direction Register (PHDDR) The individual bits of PHDDR specify input or output for the pins of port H. PHDDR cannot be read; if it is, an undefined value will be read. Bit 7 to 4 3 2 1 0 Bit Name PH3DDR PH2DDR PH1DDR PH0DDR Initial Value All 0 0 0 0 0 R/W W W W W Description Reserved * Modes 7 (when EXPE = 1), 1, 2, and 4 When the OE output enable bit (OEE) and OE output select bit (OES) are set to 1, pin PH3 functions as the OE output pin. Otherwise, when bit CS7E is set to 1, pin PH3 functions as the CS7 output pin when bit PH3DDR is set to 1, and as an input port when the bit is cleared to 0. When bit CS7E is cleared to 0, pin PH3 is an I/O port, and its function can be switched with bit PH3DDR. When areas 2 to 5 are specified as continuous SDRAM space*, OE output is CKE output. When bit CS6E is set to 1, setting bit PH2DDR to 1 makes pin PH2 function as the CS6 output pin, and clearing the bit to 0 makes the pin function as an I/O port. When bit CS6E is cleared to 0, pin PH2 is an I/O port, and its function can be switched with bit PH2DDR. Rev. 1.00 Sep. 19, 2008 Page 654 of 1270 REJ09B0466-0100 Section 10 I/O Ports Bit 0 Bit Name PH0DDR Initial Value 0 R/W W Description Pin PH1 functions as the SDRAM* output pin when the SDPSTP bit is 0 in a product supporting the SDRAM interface. In a product not supporting the SDRAM interface or when the SDPSTP bit is 1, if bit CS5E is set to 1 while area 5 is specified as normal space, pin PH1 functions as the CS5 output pin when bit PH1DDR is set to 1, and functions as an I/O port when the bit is cleared to 0. When bit CS5E is cleared to 0, pin PH1 is an I/O port, and its function can be switched with bit PH1DDR. When area 5 is specified as DRAM space and bit CS5E is set to 1, pin PH1 functions as the RAS5 output pin and as an I/O port when the bit is cleared to 0. Pin PH0 functions as the CS4 output pin when area 4 is specified as normal space and bit PH0DDR is set to 1. If bit PH0DDR is cleared to 0, pin PH0 functions as an I/O port. When bit CS4E is cleared to 0, pin PH0 is an I/O port, and its function can be switched with bit PH0DDR. When area 4 is specified as DRAM space and bit CS4E is set to 1, pin PH0 functions as the RAS4 output pin and as an I/O port when the bit is cleared to 0. When areas 2 to 5 are specified as continuous SDRAM space*, pin PH0 functions as the WE output pin when bit CS4E is set to 1, and as an I/O port when the bit is cleared to 0. * Mode 7 (when EXPE = 0) Pins PH3 to PH0 are I/O ports, and their functions can be switched with PHDDR. Pin PH1 functions as the SDRAM output pin when the SDPSTP bit is 0 in a product supporting the SDRAM interface. In a product not supporting the SDRAM interface or when the SDPSTP bit is 1, pin PH1 is an I/O port and its function can be switched with PHDDR. Note: * Not supported in the H8S/2426 Group. Rev. 1.00 Sep. 19, 2008 Page 655 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.16.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit 7 to 4 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 3 2 1 0 PH3DR PH2DR PH1DR PH0DR 0 0 0 0 R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.16.3 Port H Register (PORTH) PORTH shows the pin states of port H. PORTH cannot be modified. Bit 7 to 4 Bit Name Initial Value Undefined R/W Description Reserved If these bits are read, they will return an undefined value. 3 2 1 0 Note: PH3 PH2 PH1 PH0 * * * * * R R R R If this register is read while a PHDDR bit is set to 1, the corresponding PHDR value is read. If this register is read while a PHDDR bit is cleared to 0, the corresponding pin state is read. Determined by the states of pins PH3 to PH0. Rev. 1.00 Sep. 19, 2008 Page 656 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.16.4 Port H Open Drain Control Register (PHODR) PHODR specifies the output type of each port H pin. Bit Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0. Only the initial values should be written to these bits. 3 2 1 0 Note: PH3ODR PH2ODR PH1ODR PH0ODR * 0 0 0 0 R/W R/W R/W R/W When not specified for CS4, CS5, CS6, CS7, OEA, CKE-A, RAS4, RAS5, WE, or SDRAM* output, setting a PHODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PHODR bit to 0 makes the corresponding pin a CMOS output pin. 7 to 4 Not supported in the H8S/2426 Group. Rev. 1.00 Sep. 19, 2008 Page 657 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.16.5 Pin Functions Port H pins also function as bus control signal I/Os and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. * PH3/CS7/OE-A/CKE-A/IRQ7-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit OEE in DRAMCR of the bus controller, bit OES in PFCR2, bit CS7E in PFCR0, and bit PH3DDR. * Modes 1, 2, 4, and 7 (EXPE = 1) OEE OES RMTS2 to RMTS0 0 0 0 1 1 Areas 2 to Areas 2 to 5 are 5 are synDRAM chronous space DRAM 3 space* 1 1 PH3 output 0 PH3 input 1 CS7 output OE-A output*2 CKE-A*3 output*2 CS7E PH3DDR Pin function 0 PH3 input 0 1 PH3 output 0 PH3 input 1 1 CS7 output 0 PH3 input 0 IRQ7-B input*1 * Mode 7 (EXPE = 0) OEE OES RMTS2 to RMTS0 CS7E PH3DDR Pin function 0 PH3 input IRQ7-B input* Notes: 1. IRQ7-B input when the ITS7 bit in ITSR is 1. 2. OE-A/CKE-A output when the OES bit in PFCR2 is 1. 3. Not supported in the H8S/2426 Group. 1 1 PH3 output Rev. 1.00 Sep. 19, 2008 Page 658 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PH2/CS6/IRQ6-B The pin function is switched as shown below according to the combination of the operating mode, bit CS6E in PFCR0, and bit PH2DDR. Operating mode EXPE CS6E PH2DDR Pin function Note: * 0 PH2 input 0 1 PH2 output 0 PH2 input 1, 2, 4 1 1 CS6 output 0 PH2 input 0 1 PH2 output 0 PH2 input 0 1 PH2 output 0 PH2 input 7 1 1 1 CS6 output IRQ6-B interrupt input* IRQ6-B input when the ITS6 bit in ITSR is 1. * PH1/CS5/RAS5/SDRAM* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit SDPSTP in SCKCR of the clock pulse generator, bit CS5E in PFCR0 and bit PH1DDR. SDPSTP Operating mode EXPE OEE OES RMTS2 to RMTS0 CS5E PH1DDR Pin function 0 PH1 1 1, 2, 4 7 0 0 Area 5 is normal space 1 0 Area 5 is DRAM space 0 1 PH1 0 0 1 1 0 Area 5 is DRAM space Area 5 is normal space 1 0 PH1 0 1 CS5 1 1 PH1 0 PH1 0 1 0 PH1 1 1 PH1 0 1 CS5 1 1 PH1 0 PH1 RAS5 output 0 PH1 0 PH1 PH1 RAS5 SDRAM output* input output input output input output input output input output input output input output output Note: * Not supported in the H8S/2426 Group. Rev. 1.00 Sep. 19, 2008 Page 659 of 1270 REJ09B0466-0100 Section 10 I/O Ports * PH0/CS4/RAS4/WE* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS4E in PFCR0, and bit PH0DDR. Operating mode EXPE CS4E RMTS2 to RMTS0 0 Area 4 is normal space 1 Area 4 is DRAM space Areas 2 to 5 are synchronous DRAM* space PH0DDR Pin function 0 PH0 1 PH0 0 PH0 1 CS4 RAS4 output WE* output 0 PH0 1 PH0 0 PH0 1 PH0 0 PH0 1 CS4 RAS4 0 0 Area 4 is normal space 1 1 Area 4 is DRAM Areas 2 to 5 are synDRAM* space WE* output 1, 2, 4 7 space chronous input output input output input output input output input output output Note: * Not supported in the H8S/2426 Group. Rev. 1.00 Sep. 19, 2008 Page 660 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.17 Port J Note: Port J is not supported in the H8S/2424 Group and in the 145-pin package. Port J is a 3-bit I/O port. Port J has the following registers. * * * * Port J data direction register (PJDDR) Port J data register (PJDR) Port J register (PORT3) Port J open drain control register (PJODR) 10.17.1 Port J Data Direction Register (PJDDR) The individual bits of PJDDR specify input or output for the pins of port J. PJDDR cannot be read; if it is, an undefined value will be read. Bit 7 to 2 1 0 Bit Name PJ1DDR PJ0DDR Initial Value All 0 0 0 R/W W W Description Reserved When a pin function is specified as a general purpose I/O, setting this bit to 1 makes the corresponding pin an output port, while clearing this bit to 0 makes the corresponding pin an input port. 10.17.2 Port J Data Register (PJDR) PJDR stores output data for the port J pins. Bit 7 to 2 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 1 0 PJ1DR PJ0DR 0 0 R/W R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. Rev. 1.00 Sep. 19, 2008 Page 661 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.17.3 Port J Register (PORTJ) PORTJ shows the pin states of port J. PORTJ cannot be modified. Bit 7 to 3 Bit Name Initial Value Undefined R/W Description Reserved If these bits are read, they will return an undefined value. 2 1 0 PJ2 PJ1 PJ0 * * * R R R The pin state is always read from this register. Bit 2 is reserved for the 145-pin version. If this register is read, the PJDR values are read for the bits with the corresponding PJDDR bits set to 1. For the bits with the corresponding PJDDR bits cleared to 0, the pin states are read. Note: * Determined by the state of pins PJ0 to PJ2. 10.17.4 Port J Open Drain Control Register (PJODR) PJODR specifies the output type of each port J pin. Bit Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0. Only the initial values should be written to these bits. 1 0 PJ1ODR PJ0ODR 0 0 R/W R/W Setting a PJODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a PJODR bit to 0 makes the corresponding pin a CMOS output pin. 7 to 2 Rev. 1.00 Sep. 19, 2008 Page 662 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.17.5 Pin Functions Port J pins function only as I/O ports. The correspondence between the register specification and the pin functions is shown below. * PJ2* The PJ2 pin is an input-only pin. Pin function Note: * Not supported in the 145-pin package. PJ2 input * PJ1, PJ0 The pin function is switched as shown below according to bit PJnDDR. PJnDDR Pin function Legend: n = 1 or 0 0 PJn input 1 PJn output Rev. 1.00 Sep. 19, 2008 Page 663 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.18 Port Function Control Registers The port function controller performs I/O port control. The setting of input or output for each pin should be enabled only after the input or output destination has been selected. The port function controller has the following registers. * * * * * * Port function control register 0 (PFCR0) Port function control register 1 (PFCR1) Port function control register 2 (PFCR2) Port function control register 3 (PFCR3) Port function control register 4 (PFCR4) Port function control register 5 (PFCR5) 10.18.1 Port Function Control Register 0 (PFCR0) PFCR0 switches the functions of the chip select output pins. Bit 7 6 5 4 3 2 1 0 Bit Name CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description CS7 to CS0 Enable These bits enable or disable the corresponding CSn output. 0: Pin is designated as I/O port 1: Pin is designated as CSn output pin (n = 7 to 0) Rev. 1.00 Sep. 19, 2008 Page 664 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.18.2 Port Function Control Register 1 (PFCR1) PFCR1 enables or disables address output (A23 to A16). Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit 7 Bit Name A23E Initial Value 1 R/W R/W Description Address 23 Enable Enables or disables output for address output 23 (A23). 0: DR output when PA7DDR = 1 1: A23 output when PA7DDR = 1 6 A22E 1 R/W Address 22 Enable Enables or disables output for address output 22 (A22). 0: DR output when PA6DDR = 1 1: A22 output when PA6DDR = 1 5 A21E 1 R/W Address 21 Enable Enables or disables output for address output 21 (A21). 0: DR output when PA5DDR = 1 1: A21 output when PA5DDR = 1 4 A20E 1 R/W Address 20 Enable Enables or disables output for address output 20 (A20). 0: DR output when PA4DDR = 1 1: A20 output when PA4DDR = 1 3 A19E 1 R/W Address 19 Enable Enables or disables output for address output 19 (A19). 0: DR output when PA3DDR = 1 1: A19 output when PA3DDR = 1 2 A18E 1 R/W Address 18 Enable Enables or disables output for address output 18 (A18). 0: DR output when PA2DDR = 1 1: A18 output when PA2DDR = 1 Rev. 1.00 Sep. 19, 2008 Page 665 of 1270 REJ09B0466-0100 Section 10 I/O Ports Bit 1 Bit Name A17E Initial Value 1 R/W R/W Description Address 17 Enable Enables or disables output for address output 17 (A17). 0: DR output when PA1DDR = 1 1: A17 output when PA1DDR = 1 0 A16E 1 R/W Address 16 Enable Enables or disables output for address output 16 (A16). 0: DR output when PA0DDR = 1 1: A16 output when PA0DDR = 1 Rev. 1.00 Sep. 19, 2008 Page 666 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.18.3 Port Function Control Register 2 (PFCR2) PFCR2 enables or disables AS output, LWR output, and OE output. Bit 7 to 4 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 3 ASOE 1 R/W AS Output Enable Enables or disables the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as AS output pin 2 LWROE 1 R/W LWR Output Enable Enables or disables the LWR output pin. 0: PF3 is designated as I/O port 1: PF3 is designated as LWR output pin 1 OES 1 R/W OE Output Select 1 Selects the OE/CKE* output pin port when the OEE bit in DRAMCR is set to 1 (enabling OE/CKE*1 output). 1 0: P35 is designated as OE-B/CKE-B* output pin. 2 1 1: PH3* is designated as OE-A/CKE-A* output pin. 0 0 Reserved This bit is always read as 0. Only the initial value should be written to this bit. Notes: 1. Not supported in the H8S/2424 Group. 2. PH3 becomes PF0 in the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 667 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.18.4 Port Function Control Register 3 (PFCR3) PFCR3 switches the functions of the PPG output pin, TPU input/output pin, and TMR input/output pin. Bit 7 Bit Name Initial Value 1 R/W Description Reserved This bit is always read as 1. Only the initial value should be written to this bit. 6 PPGS 0 R/W PPG Pin Select Selects the output pins of PO5 to PO0. 0: P25/PO5-A, P24/PO4-A, P23/PO3-A, P22/PO2A, P21/PO1-A, and P20/PO0-A are selected 1: P85/PO5-B, P52/PO4-B, P83/PO3-B, P51/PO2B, P81/PO1-B, and P50/PO0-B are selected 5 TPUS 0 R/W TPU Pin Select Selects the output pins of TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, and TIOCB4. 0: P25/TIOCB4-A, P24/TIOCA4-A, P23/TIOCD3-A, P22/TIOCC3-A, P21/TIOCB3-A, and P20/TIOCA3-A are selected 1: P85/TIOCB4-B, P52/TIOCA4-B, P83/TIOCD3-B, P51/TIOCC3-B, P81/TIOCB3-B, and P50/TIOCA3-B are selected Rev. 1.00 Sep. 19, 2008 Page 668 of 1270 REJ09B0466-0100 Section 10 I/O Ports Bit 4 Bit Name TMRS Initial Value 0 R/W R/W Description TMR Pin Select Selects the output pins of TMO1 and TMO0 and input pins of TMCI1, TMCI0, TMRI1, and TMRI0. 0: [For H8S/2424] P25/TMO1-A, P24/TMO0-A, P23/TMCI1-A, P22/TMCI0-A, P21/TMRI1-A, and P20/TMRI0-A are selected [For H8S/2426, H8S/2426R] P65/TMO1-A, P64/TMO0-A, P63/TMCI1-A, P62/TMCI0-A, P61/TMRI1-A, and P60/TMRI0-A are selected 1: P85/TMO1-B , P52/TMO0-B, P83/TMCI1-B, P51/TMCI0-B, P81/TMRI1-B, and P50/TMRI0-B are selected 3 to 1 All 0 Reserved These bits are always read as 0. Only the initial values should be written to these bits. 0 1 Reserved This bit is always read as 1. Only the initial value should be written to this bit. 10.18.5 Port Function Control Register 4 (PFCR4) PFCR4 switches the functions of the WAIT input pin, BREQ input pin, BACK output pin, BREQO output pin, TxD4 output pin, RxD4 input pin, and SCK4 input/output pin. Bit 7 Bit Name WAITS Initial Value 0 R/W R/W Description WAIT Pin Select Selects the WAIT input pin. 0: PF0/WAIT-A is selected 1: P25/WAIT-B is selected 6 BREQS 0 R/W BREQ Pin Select Selects the BREQ input pin. 0: PG6/BREQ-A is selected 1: P51/BREQ-B is selected Rev. 1.00 Sep. 19, 2008 Page 669 of 1270 REJ09B0466-0100 Section 10 I/O Ports Bit 5 Bit Name BACKS Initial Value 0 R/W R/W Description BACK Pin Select Selects the BACK output pin. 0: PG5/BACK-A is selected 1: P52/BACK-B is selected 4 BREQOS 0 R/W BREQO Pin Select Selects the BREQO output pin. 0: PG4/BREQO-A is selected 1: P50/BREQO-B is selected 3 0 Reserved This bit is always read as 0. Only the initial value should be written to this bit. 2 TXD4S 0 R/W TxD4 Pin Select Selects the TxD4 output pin. 0: P23/TxD4-A is selected 1: PA1/TxD4-B is selected 1 RXD4S 0 R/W RxD4 Pin Select Selects the RxD4 input pin. 0: P24/RxD4-A is selected 1: PA2/RxD4-B is selected 0 SCK4S 0 R/W SCK4 Pin Select Selects the SCK4 input/output pin. 0: P34/SCK4-A is selected 1: PA3/SCK4-B is selected Rev. 1.00 Sep. 19, 2008 Page 670 of 1270 REJ09B0466-0100 Section 10 I/O Ports 10.18.6 Port Function Control Register 5 (PFCR5) PFCR5 switches the functions of the SSU input/output pins. Bit 7 6 Bit Name SSO0S1 SSO0S0 Initial Value 0 0 R/W R/W R/W Description SSO0 Pin Select Selects the SSO0 input/output pin. 00: P14/SSO0-A is selected 01: PA7/SSO0-B is selected 10: PF3/SSO0-C is selected 11: Setting prohibited 5 4 SSI0S1 SSI0S0 0 0 R/W R/W SSI0 Pin Select Selects the SSI0 input/output pin. 00: P15/SSI0-A is selected 01: PA6/SSI0-B is selected 10: PF2/SSI0-C is selected 11: Setting prohibited 3 2 SSCK0S1 SSCK0S0 0 0 R/W R/W SSCK0 Pin Select Selects the SSCK0 input/output pin. 00: P16/SSCK0-A is selected 01: PA5/SSCK0-B is selected 10: PF1/SSCK0-C is selected 11: Setting prohibited 1 0 SCS0S1 SCS0S0 0 0 R/W R/W SCS0 Pin Select Selects the SCS0 input/output pin. 00: P17/SCS0-A is selected 01: PA4/SCS0-B is selected 10: PF0/SCS0-C is selected 11: Setting prohibited Rev. 1.00 Sep. 19, 2008 Page 671 of 1270 REJ09B0466-0100 Section 10 I/O Ports Rev. 1.00 Sep. 19, 2008 Page 672 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU: unit 0 and unit 1) which each comprises six 16-bit timer channels, resulting in a total of 12 channels. The functions of unit 0 are listed in table 11.1, and the functions of unit 1 are listed in table 11.2. The block diagram of unit 0 is shown in figure 11.1 and the block diagram of unit 1 is shown in figure 11.2. The descriptions in this section refer to unit 0. 11.1 Features * Maximum 16-pulse input/output * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operations: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 * Cascaded operation * Fast access via internal 16-bit bus * 26 interrupt sources * Automatic transfer of register data * Programmable pulse generator (PPG) output trigger can be generated * A/D converter conversion start trigger can be generated * Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 673 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.1 TPU (Unit 0) Functions Item Count clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture /1 /4 /16 /64 /256 TCLKA TCLKB TGRA_1 TGRB_1 TIOCA1 TIOCB1 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOCA2 TIOCB2 /1 /4 /16 /64 /256 /1024 /4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture /1 /4 /16 /64 /1024 TCLKA TCLKC TGRA_4 TGRB_4 TIOCA4 TIOCB4 /1 /4 /16 /64 /256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 TIOCA5 TIOCB5 General registers (TGR) General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation Rev. 1.00 Sep. 19, 2008 Page 674 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 TGR compare match or input capture TGRA_1 compare match or input capture TGRA_1 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture 4 sources * Channel 2 TGR compare match or input capture TGRA_2 compare match or input capture TGRA_2 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture 4 sources Channel 3 TGR compare match or input capture TGRA_3 compare match or input capture TGRA_3 compare match or input capture Channel 4 TGR compare match or input capture TGRA_4 compare match or input capture TGRA_4 compare match or input capture Channel 5 TGR compare match or input capture TGRA_5 compare match or input capture TGRA_5 compare match or input capture DTC TGR activation compare match or input capture DMAC TGRA_0 activation compare match or input capture A/D TGRA_0 converter compare trigger match or input capture PPG trigger TGRA_0/ TGRB_0 compare match or input capture 5 sources * Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow TGRA_3/ TGRB_3 compare match or input capture 5 sources Compare match or input capture 3A Compare match or input capture 3B Compare match or input capture 3C Compare match or input capture 3D Overflow 4 sources * Compare match or input capture 4A Compare match or input capture 4B Overflow Underflow Interrupt sources 4 sources * Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow * * * * * Compare * match or input capture 1A Compare * match or input capture 1B Overflow * Underflow * Compare * match or input capture 2A Compare * match or input capture 2B Overflow * Underflow * * * * * * * * * * [Legend] : Possible *: Not possible Rev. 1.00 Sep. 19, 2008 Page 675 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.2 TPU (Unit 1) Functions Item Count clock Channel Channel 6 Channel 7 Channel 8 Channel 9 10 /1 /4 /16 /64 TCLKE TCLKF TCLKG TCLKH TGRA_6 TGRB_6 TGRC_6 TGRD_6 TIOCA6 TIOCB6 TIOCC6 TIOCD6 TGR compare match or input capture /1 /4 /16 /64 /256 TCLKE TCLKF TGRA_7 TGRB_7 TIOCA7 TIOCB7 /1 /4 /16 /64 /1024 TCLKE TCLKF TCLKG TGRA_8 TGRB_8 TIOCA8 TIOCB8 /1 /4 /16 /64 /256 /1024 /4096 TCLKE TGRA_9 TGRB_9 TGRC_9 TGRD_9 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TGR compare match or input capture /1 /4 /16 /64 /1024 TCLKE TCLKG TGRA_10 TGRB_10 TIOCA10 TIOCB10 Channel 11 /1 /4 /16 /64 /256 TCLKE TCLKG TCLKH TGRA_11 TGRB_11 TIOCA11 TIOCB11 General registers (TGR) General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation Rev. 1.00 Sep. 19, 2008 Page 676 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 6 Channel 7 TGR compare match or input capture TGRA_7 compare match or input capture TGRA_7/ TGRB_7 compare match or input capture 4 sources Channel 8 TGR compare match or input capture TGRA_8 compare match or input capture TGRA_8/ TGRB_8 compare match or input capture 4 sources Channel 9 TGR compare match or input capture TGRA_9 compare match or input capture Channel 10 TGR compare match or input capture TGRA_10 compare match or input capture Channel 11 TGR compare match or input capture TGRA_11 compare match or input capture DTC TGR activation compare match or input capture DMAC activation A/D TGRA_6 converter compare trigger match or input capture PPG trigger TGRA_6/ TGRB_6 compare match or input capture 5 sources * TGRA_9/ TGRB_9 compare match or input capture 5 sources 4 sources Compare * match or input capture 9A Compare * match or input capture 9B Compare * match or * input capture 9C Compare match or input capture 9D Overflow Interrupt sources 4 sources Compare match or input capture 11A Compare match or input capture 11B Overflow Underflow Compare * match or input capture 6A Compare * match or input capture 6B Compare * match or * input capture 6C Compare match or input capture 6D Overflow Compare * match or input capture 7A Compare * match or input capture 7B Overflow * Underflow * Compare * match or input capture 8A Compare * match or input capture 8B Overflow Underflow * Compare * match or input capture 10A Compare * match or input capture 10B Overflow * Underflow * * * * * * * [Legend] : Possible : Not possible Rev. 1.00 Sep. 19, 2008 Page 677 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) TIORH TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 3 to 5 Input/output pins TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5 Channel 5 TIOR TMDR Channel 2 TSR Clock input Internal clock: /1 /4 /16 /64 /256 /1024 /4096 External clock: TCLKA TCLKB TCLKC TCLKD TIER TCR Module data bus TSTR TSYR TGRA Bus interface TGRB TCNT Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U TMDR Channel 4 TSR TIER TCR TIOR TMDR TSR TIER TCR TGRA TGRB TCNT Common Control logic Internal data bus A/D conversion start request signal PPG output trigger signal TIOR TIER TCR TGRA TGRB TCNT Control logic for channels 0 to 2 TIORH TIORL TMDR Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TIOR Channel 0 TSR TIER TCR TGRB TGRC TGRD TGRB TCNT TCNT Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TIER: TSR: TGR (A, B, C, D): TCNT: TIER TCR Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 11.1 Block Diagram of TPU (Unit 0) Rev. 1.00 Sep. 19, 2008 Page 678 of 1270 REJ09B0466-0100 TGRA Section 11 16-Bit Timer Pulse Unit (TPU) TIORH TIORL TMDR Channel 9 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 9 to 11 Input/output pins TIOCA9 Channel 9: TIOCB9 TIOCC9 TIOCD9 Channel 10: TIOCA10 TIOCB10 Channel 11: TIOCA11 TIOCB11 Channel 11 TIOR TMDR Channel 6 TSR Clock input Internal clock: /1 /4 /16 /64 /256 /1024 /4096 External clock: TCLKE TCLKF TCLKG TCLKH TIER TCR Module data bus TSTR TSYR TGRA Bus interface TGRB TCNT Interrupt request signals Channel 9: TGI9A TGI9B TGI9C TGI9D TCI9V Channel 10: TGI10A TGI10B TCI10V TCI10U Channel 11: TGI11A TGI11B TCI11V TCI11U TMDR Channel 10 TSR TIER TCR TIOR TMDR TSR TIER TCR TGRA TGRB TCNT Common Control logic Internal data bus A/D conversion start request signal PPG output trigger signal TIOR TIER TCR TGRA TGRB TCNT Control logic for channels 6 to 8 TIORH TIORL TMDR Input/output pins TIOCA6 Channel 6: TIOCB6 TIOCC6 TIOCD6 TIOCA7 Channel 7: TIOCB7 TIOCA8 Channel 8: TIOCB8 Interrupt request signals Channel 6: TGI6A TGI6B TGI6C TGI6D TCI6V Channel 7: TGI7A TGI7B TCI7V TCI7U Channel 8: TGI8A TGI8B TCI8V TCI8U TMDR Channel 7 TSR TGRA TIOR Channel 8 TSR TIER TCR TGRB TGRC TGRD TGRB TCNT TCNT Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TIER: TSR: TGR (A, B, C, D): TCNT: TIER TCR Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 11.2 Block Diagram of TPU (Unit 1) Rev. 1.00 Sep. 19, 2008 Page 679 of 1270 REJ09B0466-0100 TGRA Section 11 16-Bit Timer Pulse Unit (TPU) 11.2 Input/Output Pins Table 11.3 Pin Configuration Unit 0 Channel All Symbol TCLKA TCLKB TCLKC TCLKD 0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 and 5 phase counting mode A phase input) External clock B input pin (Channel 1 and 5 phase counting mode B phase input) External clock C input pin (Channel 2 and 4 phase counting mode A phase input) External clock D input pin (Channel 2 and 4 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin Rev. 1.00 Sep. 19, 2008 Page 680 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Unit 0 Channel 4 Symbol TIOCA4 TIOCB4 I/O I/O I/O I/O I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O Function TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRA_5 input capture input/output compare output/PWM output pin TGRB_5 input capture input/output compare output/PWM output pin External clock E input pin (Channel 7 and 11 phase counting mode A phase input) External clock F input pin (Channel 7 and 11 phase counting mode B phase input) External clock G input pin (Channel 8 and 10 phase counting mode A phase input) External clock H input pin (Channel 8 and 10 phase counting mode B phase input) TGRA_6 input capture input/output compare output/PWM output pin TGRB_6 input capture input/output compare output/PWM output pin TGRC_6 input capture input/output compare output/PWM output pin TGRD_6 input capture input/output compare output/PWM output pin TGRA_7 input capture input/output compare output/PWM output pin TGRB_7 input capture input/output compare output/PWM output pin TGRA_8 input capture input/output compare output/PWM output pin TGRB_8 input capture input/output compare output/PWM output pin 5 TIOCA5 TIOCB5 1 All TCLKE TCLKF TCLKG TCLKH 6 TIOCA6 TIOCB6 TIOCC6 TIOCD6 7 TIOCA7 TIOCB7 8 TIOCA8 TIOCB8 Rev. 1.00 Sep. 19, 2008 Page 681 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Unit 1 Channel 9 Symbol TIOCA9 TIOCB9 TIOCC9 TIOCD9 I/O I/O I/O I/O I/O I/O I/O I/O I/O Function TGRA_9 input capture input/output compare output/PWM output pin TGRB_9 input capture input/output compare output/PWM output pin TGRC_9 input capture input/output compare output/PWM output pin TGRD_9 input capture input/output compare output/PWM output pin TGRA_10 input capture input/output compare output/PWM output pin TGRB_10 input capture input/output compare output/PWM output pin TGRA_11 input capture input/output compare output/PWM output pin TGRB_11 input capture input/output compare output/PWM output pin 10 TIOCA10 TIOCB10 11 TIOCA11 TIOCB11 Rev. 1.00 Sep. 19, 2008 Page 682 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3 Register Descriptions The TPU has the following registers in each channel. The descriptions in this section refer to the registers of unit 0. Unit 0: Channel 0 * Timer control register_0 (TCR_0) * Timer mode register_0 (TMDR_0) * Timer I/O control register H_0 (TIORH_0) * Timer I/O control register L_0 (TIORL_0) * Timer interrupt enable register_0 (TIER_0) * Timer status register_0 (TSR_0) * Timer counter_0 (TCNT_0) * Timer general register A_0 (TGRA_0) * Timer general register B_0 (TGRB_0) * Timer general register C_0 (TGRC_0) * Timer general register D_0 (TGRD_0) Channel 1 * Timer control register_1 (TCR_1) * Timer mode register_1 (TMDR_1) * Timer I/O control register_1 (TIOR_1) * Timer interrupt enable register_1 (TIER_1) * Timer status register_1 (TSR_1) * Timer counter_1 (TCNT_1) * Timer general register A_1 (TGRA_1) * Timer general register B_1 (TGRB_1) Rev. 1.00 Sep. 19, 2008 Page 683 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 2 * Timer control register_2 (TCR_2) * Timer mode register_2 (TMDR_2) * Timer I/O control register_2 (TIOR_2) * Timer interrupt enable register_2 (TIER_2) * Timer status register_2 (TSR_2) * Timer counter_2 (TCNT_2) * Timer general register A_2 (TGRA_2) * Timer general register B_2 (TGRB_2) Channel 3 * Timer control register_3 (TCR_3) * Timer mode register_3 (TMDR_3) * Timer I/O control register H_3 (TIORH_3) * Timer I/O control register L_3 (TIORL_3) * Timer interrupt enable register_3 (TIER_3) * Timer status register_3 (TSR_3) * Timer counter_3 (TCNT_3) * Timer general register A_3 (TGRA_3) * Timer general register B_3 (TGRB_3) * Timer general register C_3 (TGRC_3) * Timer general register D_3 (TGRD_3) Channel 4 * Timer control register_4 (TCR_4) * Timer mode register_4 (TMDR_4) * Timer I/O control register_4 (TIOR_4) * Timer interrupt enable register_4 (TIER_4) * Timer status register_4 (TSR_4) * Timer counter_4 (TCNT_4) * Timer general register A_4 (TGRA_4) * Timer general register B_4 (TGRB_4) Rev. 1.00 Sep. 19, 2008 Page 684 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 5 * Timer control register_5 (TCR_5) * Timer mode register_5 (TMDR_5) * Timer I/O control register_5 (TIOR_5) * Timer interrupt enable register_5 (TIER_5) * Timer status register_5 (TSR_5) * Timer counter_5 (TCNT_5) * Timer general register A_5 (TGRA_5) * Timer general register B_5 (TGRB_5) Common Registers of Unit 0 * Timer start register (TSTR) * Timer synchronous register (TSYR) Unit 1: Channel 6 * Timer control register_6 (TCR_6) * Timer mode register_6 (TMDR_6) * Timer I/O control register H_6 (TIORH_6) * Timer I/O control register L_6 (TIORL_6) * Timer interrupt enable register_6 (TIER_6) * Timer status register_6 (TSR_6) * Timer counter_6 (TCNT_6) * Timer general register A_6 (TGRA_6) * Timer general register B_6 (TGRB_6) * Timer general register C_6 (TGRC_6) * Timer general register D_6 (TGRD_6) Rev. 1.00 Sep. 19, 2008 Page 685 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 7 * Timer control register_7 (TCR_7) * Timer mode register_7 (TMDR_7) * Timer I/O control register_7 (TIOR_7) * Timer interrupt enable register_7 (TIER_7) * Timer status register_7 (TSR_7) * Timer counter_7 (TCNT_7) * Timer general register A_7 (TGRA_7) * Timer general register B_7 (TGRB_7) Channel 8 * Timer control register_8 (TCR_8) * Timer mode register_8 (TMDR_8) * Timer I/O control register_8 (TIOR_8) * Timer interrupt enable register_8 (TIER_8) * Timer status register_8 (TSR_8) * Timer counter_8 (TCNT_8) * Timer general register A_8 (TGRA_8) * Timer general register B_8 (TGRB_8) Channel 9 * Timer control register_9 (TCR_9) * Timer mode register_9 (TMDR_9) * Timer I/O control register H_9 (TIORH_9) * Timer I/O control register L_9 (TIORL_9) * Timer interrupt enable register_9 (TIER_9) * Timer status register_9 (TSR_9) * Timer counter_9 (TCNT_9) * Timer general register A_9 (TGRA_9) * Timer general register B_9 (TGRB_9) * Timer general register C_9 (TGRC_9) * Timer general register D_9 (TGRD_9) Rev. 1.00 Sep. 19, 2008 Page 686 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 10 * Timer control register_10 (TCR_10) * Timer mode register_10 (TMDR_10) * Timer I/O control register_10 (TIOR_10) * Timer interrupt enable register_10 (TIER_10) * Timer status register_10 (TSR_10) * Timer counter_10 (TCNT_10) * Timer general register A_10 (TGRA_10) * Timer general register B_10 (TGRB_10) Channel 11 * Timer control register_11 (TCR_11) * Timer mode register_11 (TMDR_11) * Timer I/O control register_11 (TIOR_11) * Timer interrupt enable register_11 (TIER_11) * Timer status register_11 (TSR_11) * Timer counter_11 (TCNT_11) * Timer general register A_11 (TGRA_11) * Timer general register B_11 (TGRB_11) Common Registers of Unit 1 * Timer start register B (TSTRB) * Timer synchronous register B (TSYRB) Rev. 1.00 Sep. 19, 2008 Page 687 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 11.4 and 11.5 for details. Clock Edge 1 and 0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 11.6 to 11.11 for details. [Legend] x: Don't care Rev. 1.00 Sep. 19, 2008 Page 688 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.4 CCLR2 to CCLR0 (Channels 0 and 3) Channel 0, 3 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 1 0 0 1 1 0 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 11.5 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Channel 1, 2, 4, 5 Bit 7 Reserved*2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 689 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.6 TPSC2 to TPSC0 (Channel 0) Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 11.7 TPSC2 to TPSC0 (Channel 1) Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 1.00 Sep. 19, 2008 Page 690 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.8 TPSC2 to TPSC0 (Channel 2) Channel 2 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 11.9 TPSC2 to TPSC0 (Channel 3) Channel 3 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input Internal clock: counts on /1024 Internal clock: counts on /256 Internal clock: counts on /4096 Rev. 1.00 Sep. 19, 2008 Page 691 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.10 TPSC2 to TPSC0 (Channel 4) Channel 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 11.11 TPSC2 to TPSC0 (Channel 5) Channel 5 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Rev. 1.00 Sep. 19, 2008 Page 692 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.2 Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit 7 6 5 Bit Name -- -- BFB Initial Value 1 1 0 R/W -- -- R/W Description Reserved These bits are always read as 1 and cannot be modified. Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 These bits are used to set the timer operating mode. MD3 is a reserved bit. The write value should always be 0. See table 11.12 for details. Rev. 1.00 Sep. 19, 2008 Page 693 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.12 MD3 to MD0 Bit 3 1 MD3* 0 Bit 2 MD2*2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 x x 0 1 1 x Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 [Legend] x: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. 11.3.3 Timer I/O Control Register (TIOR) TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 1.00 Sep. 19, 2008 Page 694 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control B3 to B0 Specify the function of TGRB. For details, see tables 11.13, 11.15, 11.16, 11.17, 11.19, and 11.20. I/O Control A3 to A0 Specify the function of TGRA. For details, see tables 11.21, 11.23, 11.24, 11.25, 11.27, and 11.28. TIORL_0, TIORL_3 Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. For details, see tables 11.22 and 11.26. Description I/O Control D3 to D0 Specify the function of TGRD. For details, see tables 11.14 and 11.18. Rev. 1.00 Sep. 19, 2008 Page 695 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.13 TIORH_0 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge Capture input source is TIOCB0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count- up/count-down* [Legend] x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. Rev. 1.00 Sep. 19, 2008 Page 696 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.14 TIORL_0 Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register*2 TGRD_0 Function Output compare 2 register* TIOCD0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge Capture input source is TIOCD0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* 1 [Legend] x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Sep. 19, 2008 Page 697 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.15 TIOR_1 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] x: Don't care Rev. 1.00 Sep. 19, 2008 Page 698 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.16 TIOR_2 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x Input capture register TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges Rev. 1.00 Sep. 19, 2008 Page 699 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.17 TIORH_3 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_3 Function Output compare register TIOCB3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB3 pin Input capture at rising edge Capture input source is TIOCB3 pin Input capture at falling edge Capture input source is TIOCB3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. Rev. 1.00 Sep. 19, 2008 Page 700 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.18 TIORL_3 Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register*2 TGRD_3 Function Output compare 2 register* TIOCD3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD3 pin Input capture at rising edge Capture input source is TIOCD3 pin Input capture at falling edge Capture input source is TIOCD3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* 1 [Legend] x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Sep. 19, 2008 Page 701 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.19 TIOR_4 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_4 Function Output compare register TIOCB4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB4 pin Input capture at rising edge Capture input source is TIOCB4 pin Input capture at falling edge Capture input source is TIOCB4 pin Input capture at both edges Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture [Legend] x: Don't care Rev. 1.00 Sep. 19, 2008 Page 702 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.20 TIOR_5 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x Input capture register TGRB_5 Function Output compare register TIOCB5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB5 pin Input capture at rising edge Capture input source is TIOCB5 pin Input capture at falling edge Capture input source is TIOCB5 pin Input capture at both edges Rev. 1.00 Sep. 19, 2008 Page 703 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.21 TIORH_0 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Rev. 1.00 Sep. 19, 2008 Page 704 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.22 TIORL_0 Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRC_0 Function Output compare register* TIOCC0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC0 pin Input capture at rising edge Capture input source is TIOCC0 pin Input capture at falling edge Capture input source is TIOCC0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Sep. 19, 2008 Page 705 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.23 TIOR_1 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge Capture input source is TIOCA1 pin Input capture at both edges Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] x: Don't care Rev. 1.00 Sep. 19, 2008 Page 706 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.24 TIOR_2 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x Input capture register TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges Rev. 1.00 Sep. 19, 2008 Page 707 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.25 TIORH_3 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_3 Function Output compare register TIOCA3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA3 pin Input capture at rising edge Capture input source is TIOCA3 pin Input capture at falling edge Capture input source is TIOCA3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] x: Don't care Rev. 1.00 Sep. 19, 2008 Page 708 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.26 TIORL_3 Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRC_3 Function Output compare register* TIOCC3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC3 pin Input capture at rising edge Capture input source is TIOCC3 pin Input capture at falling edge Capture input source is TIOCC3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] x: Don't care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Sep. 19, 2008 Page 709 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.27 TIOR_4 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_4 Function Output compare register TIOCA4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA4 pin Input capture at rising edge Capture input source is TIOCA4 pin Input capture at falling edge Capture input source is TIOCA4 pin Input capture at both edges Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture [Legend] x: Don't care Rev. 1.00 Sep. 19, 2008 Page 710 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.28 TIOR_5 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x Input capture register TGRA_5 Function Output compare register TIOCA5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Input capture source is TIOCA5 pin Input capture at rising edge Input capture source is TIOCA5 pin Input capture at falling edge Input capture source is TIOCA5 pin Input capture at both edges Rev. 1.00 Sep. 19, 2008 Page 711 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5 -- TCIEU 1 0 -- R/W Reserved This bit is always read as 1 and cannot be modified. Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev. 1.00 Sep. 19, 2008 Page 712 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit Name TGIEC Initial value 0 R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev. 1.00 Sep. 19, 2008 Page 713 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 -- 1 -- Reserved This bit is always read as 1 and cannot be modified. 5 TCFU 0 R/(W)* Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 4 TCFV 0 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 Rev. 1.00 Sep. 19, 2008 Page 714 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGFD Initial value 0 R/W R/(W)* Description Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFD after reading TGFD =1 [Clearing conditions] * * 2 TGFC 0 R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFC after reading TGFC =1 [Clearing conditions] * * Rev. 1.00 Sep. 19, 2008 Page 715 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 1 Bit Name TGFB Initial value 0 R/W R/(W)* Description Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB =1 [Clearing conditions] * * 0 TGFA 0 R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing conditions] * * * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When DMAC is activated by TGIA interrupt while DTE bit of DMABCR in DTC is 0 When 0 is written to TGFA after reading TGFA =1 Note: * Only 0 can be written, for flag clearing. Rev. 1.00 Sep. 19, 2008 Page 716 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 11.3.7 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA-TGRC and TGRB-TGRD. 11.3.8 Timer Start Register (TSTR) TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit 7 6 5 4 3 2 1 0 Bit Name -- -- CST5 CST4 CST3 CST2 CST1 CST0 Initial value 0 0 0 0 0 0 0 0 R/W -- -- R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. Counter Start 5 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation Rev. 1.00 Sep. 19, 2008 Page 717 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit 7 6 5 4 3 2 1 0 Bit Name -- -- SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value 0 0 0 0 0 0 0 0 R/W -- -- R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 performs synchronous operation (TCNT synchronous presetting/ synchronous clearing is possible) Rev. 1.00 Sep. 19, 2008 Page 718 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.10 Timer Start Register B (TSTRB) TSTRB selects operation/stoppage for channels 6 to 11. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit 7 6 5 4 3 2 1 0 Bit Name -- -- CST11 CST10 CST9 CST8 CST7 CST6 Initial value 0 0 0 0 0 0 0 0 R/W -- -- R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. Counter Start 11 to 6 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_11 to TCNT_6 count operation is stopped 1: TCNT_11 to TCNT_6 performs count operation Rev. 1.00 Sep. 19, 2008 Page 719 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.11 Timer Synchronous Register B (TSYRB) TSYRB selects independent operation or synchronous operation for the TCNT counters of channels 6 to 11. A channel performs synchronous operation when the corresponding bit in TSYRB is set to 1. Bit 7 6 5 4 3 2 1 0 Bit Name -- -- SYNC11 SYNC10 SYNC9 SYNC8 SYNC7 SYNC6 Initial value 0 0 0 0 0 0 0 0 R/W -- -- R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. Timer Synchronization 11 to 6 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_11 to TCNT_6 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_11 to TCNT_6 performs synchronous operation (TCNT synchronous presetting/ synchronous clearing is possible) Rev. 1.00 Sep. 19, 2008 Page 720 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4 11.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure Figure 11.3 shows an example of the count operation setting procedure. Rev. 1.00 Sep. 19, 2008 Page 721 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Operation selection Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count Periodic counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count [5] Figure 11.3 Example of Counter Operation Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 722 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 11.4 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 11.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Rev. 1.00 Sep. 19, 2008 Page 723 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.5 illustrates periodic counter operation. TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 11.5 Periodic Counter Operation Rev. 1.00 Sep. 19, 2008 Page 724 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 11.6 shows an example of the setting procedure for waveform output by a compare match. Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count [3] Figure 11.6 Example of Setting Procedure for Waveform Output by Compare Match Rev. 1.00 Sep. 19, 2008 Page 725 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 11.7 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time Figure 11.7 Example of 0 Output/1 Output Operation Figure 11.8 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output TIOCB TIOCA Figure 11.8 Example of Toggle Output Operation Rev. 1.00 Sep. 19, 2008 Page 726 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, 4, 6, 7, 9, and 10 it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0, 3, 6, and 9, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. (a) Example of setting procedure for input capture operation Figure 11.9 shows an example of the setting procedure for input capture operation. Input selection [1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). [1] Select input capture input [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 11.9 Example of Setting Procedure for Input Capture Operation Rev. 1.00 Sep. 19, 2008 Page 727 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 11.10 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 11.10 Example of Input Capture Operation 11.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple of TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 and 6 to 11 can all be designated for synchronous operation. Rev. 1.00 Sep. 19, 2008 Page 728 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (1) Example of Synchronous Operation Setting Procedure Figure 11.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source No [3] Set synchronous counter clearing [4] Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 11.11 Example of Synchronous Operation Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 729 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 11.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 11.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA_0 TIOCA_1 TIOCA_2 Figure 11.12 Example of Synchronous Operation Rev. 1.00 Sep. 19, 2008 Page 730 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, 6, and 9, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 11.29 shows the register combinations used in buffer operation. Table 11.29 Register Combinations in Buffer Operation Unit 0 Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 1 6 TGRA_6 TGRB_6 9 TGRA_9 TGRB_9 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 TGRC_6 TGRD_6 TGRC_9 TGRD_9 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 11.13. Compare match signal Buffer register Timer general register Comparator TCNT Figure 11.13 Compare Match Buffer Operation Rev. 1.00 Sep. 19, 2008 Page 731 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 11.14. Input capture signal Timer general register Buffer register TCNT Figure 11.14 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 11.15 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] Select TGR function [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set buffer operation [2] Start count [3] Figure 11.15 Example of Buffer Operation Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 732 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) (a) Examples of Buffer Operation When TGR is an output compare register Figure 11.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details on PWM modes, see section 11.4.5, PWM Modes. TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 11.16 Example of Buffer Operation (1) Rev. 1.00 Sep. 19, 2008 Page 733 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (b) When TGR is an input capture register Figure 11.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 11.17 Example of Buffer Operation (2) Rev. 1.00 Sep. 19, 2008 Page 734 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4, channel 7, or channel 10) counter clock at overflow/underflow of TCNT_2 (TCNT_5, TCNT_8, or TCNT_11) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 11.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 11.30 Cascaded Combinations Combination Channels 1 and 2 Channels 4 and 5 Channels 7 and 8 Channels 10 and 11 Upper 16 Bits TCNT_1 TCNT_4 TCNT_7 TCNT_10 Lower 16 Bits TCNT_2 TCNT_5 TCNT_8 TCNT_11 (1) Example of Cascaded Operation Setting Procedure Figure 11.18 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading [1] [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Start count [2] Figure 11.18 Cascaded Operation Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 735 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) Examples of Cascaded Operation Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2. TCNT_1 clock TCNT_1 TCNT_2 clock TCNT_2 TIOCA1, TIOCA2 TGRA_1 H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2 TGRA_2 H'0000 Figure 11.19 Example of Cascaded Operation (1) Figure 11.20 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 11.20 Example of Cascaded Operation (2) Rev. 1.00 Sep. 19, 2008 Page 736 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0-% to 100-% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 11.31. Rev. 1.00 Sep. 19, 2008 Page 737 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.31 PWM Output Registers and Output Pins Output Pins Unit 0 Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TGRA_4 TGRB_4 TGRA_5 TGRB_5 TGRA_6 TGRB_6 TGRC_6 TGRD_6 TGRA_7 TGRB_7 TGRA_8 TGRB_8 TGRA_9 TGRB_9 TGRC_9 TGRD_9 TGRA_10 TGRB_10 TGRA_11 TGRB_11 PWM Mode 1 TIOCA0 TIOCC0 TIOCA1 TIOCA2 TIOCA3 TIOCC3 TIOCA4 TIOCA5 TIOCA6 TIOCC6 TIOCA7 TIOCA8 TIOCA9 TIOCC9 TIOCA10 TIOCA11 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 1 2 3 4 5 1 6 7 8 9 10 11 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set. Rev. 1.00 Sep. 19, 2008 Page 738 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (1) Example of PWM Mode Setting Procedure Figure 11.21 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. Select counter clearing source [2] Select waveform output level [3] [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGRs. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. Set TGR [4] Set PWM mode [5] [6] Set the CST bit in TSTR to 1 to start the count operation. Start count [6] Figure 11.21 Example of PWM Mode Setting Procedure Rev. 1.00 Sep. 19, 2008 Page 739 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) Examples of PWM Mode Operation Figure 11.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as the duty cycle. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 11.22 Example of PWM Mode Operation (1) Rev. 1.00 Sep. 19, 2008 Page 740 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty cycle. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 11.23 Example of PWM Mode Operation (2) Rev. 1.00 Sep. 19, 2008 Page 741 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 11.24 Example of PWM Mode Operation (3) Rev. 1.00 Sep. 19, 2008 Page 742 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, 5, 7, 8, 10, and 11. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 11.32 shows the correspondence between external clock pins and channels. Table 11.32 Clock Input Pins in Phase Counting Mode External Clock Pins Unit 0 Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode 1 When channel 7 or 11 is set to phase counting mode When channel 8 or 10 is set to phase counting mode A-Phase TCLKA TCLKC TCLKE TCLKG B-Phase TCLKB TCLKD TCLKF TCLKH Rev. 1.00 Sep. 19, 2008 Page 743 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (1) Example of Phase Counting Mode Setting Procedure Figure 11.25 shows an example of the phase counting mode setting procedure. Phase counting mode [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. [1] Select phase counting mode Start count [2] Figure 11.25 Example of Phase Counting Mode Setting Procedure (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. a. Phase counting mode 1 Figure 11.26 shows an example of phase counting mode 1 operation, and table 11.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.26 Example of Phase Counting Mode 1 Operation Rev. 1.00 Sep. 19, 2008 Page 744 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKE (Channels 7 and 11) TCLKG (Channels 8 and 10) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCLKF (Channels 7 and 11) TCLKH (Channels 8 and 10) Operation Up-count Rev. 1.00 Sep. 19, 2008 Page 745 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) b. Phase counting mode 2 Figure 11.27 shows an example of phase counting mode 2 operation, and table 11.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.27 Example of Phase Counting Mode 2 Operation Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKE (Channels 7 and 11) TCLKG (Channels 8 and 10) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCLKF (Channels 7 and 11) TCLKH (Channels 8 and 10) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count Rev. 1.00 Sep. 19, 2008 Page 746 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) c. Phase counting mode 3 Figure 11.28 shows an example of phase counting mode 3 operation, and table 11.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.28 Example of Phase Counting Mode 3 Operation Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKE (Channels 7 and 11) TCLKG (Channels 8 and 10) High level Low level Low level High level High level Low level High level Low level [Legend] : : Rising edge Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCLKF (Channels 7 and 11) TCLKH (Channels 8 and 10) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care Rev. 1.00 Sep. 19, 2008 Page 747 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) d. Phase counting mode 4 Figure 11.29 shows an example of phase counting mode 4 operation, and table 11.36 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.29 Example of Phase Counting Mode 4 Operation Table 11.36 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKE (Channels 7 and 11) TCLKG (Channels 8 and 10) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCLKF (Channels 7 and 11) TCLKH (Channels 8 and 10) Operation Up-count Rev. 1.00 Sep. 19, 2008 Page 748 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (3) Phase Counting Mode Application Example Figure 11.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function, and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved. Rev. 1.00 Sep. 19, 2008 Page 749 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 + + - TGRA_0 (speed control cycle) TGRC_0 (position control cycle) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 11.30 Phase Counting Mode Application Example 11.5 Interrupt Sources There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 11.37 lists the TPU interrupt sources. Rev. 1.00 Sep. 19, 2008 Page 750 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.37 TPU Interrupts Unit Channel 0 0 Name TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TCNT_4 overflow TCNT_4 underflow TGRA_5 input capture/compare match TGRB_5 input capture/compare match TCNT_5 overflow TCNT_5 underflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TCFV_4 TCFU_4 TGFA_5 TGFB_5 TCFV_5 TCFU_5 DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible DMAC Activation Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Rev. 1.00 Sep. 19, 2008 Page 751 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Unit Channel 1 6 Name TGI6A TGI6B TGI6C TGI6D TCI6V Interrupt Source TGRA_6 input capture/compare match TGRB_6 input capture/compare match TGRC_6 input capture/compare match TGRD_6 input capture/compare match TCNT_6 overflow TGRA_7 input capture/compare match TGRB_7 input capture/compare match TCNT_7 overflow TCNT_7 underflow TGRA_8 input capture/compare match TGRB_8 input capture/compare match TCNT_8 overflow TCNT_8 underflow TGRA_9 input capture/compare match TGRB_9 input capture/compare match TGRC_9 input capture/compare match TGRD_9 input capture/compare match TCNT_9 overflow TGRA_10 input capture/compare match TGRB_10 input capture/compare match TCNT_10 overflow TCNT_10 underflow TGRA_11 input capture/compare match TGRB_11 input capture/compare match TCNT_11 overflow TCNT_11 underflow Interrupt Flag TGFA_6 TGFB_6 TGFC_6 TGFD_6 TCFV_6 TGFA_7 TGFB_7 TCFV_7 TCFU_7 TGFA_8 TGFB_8 TCFV_8 TCFU_8 TGFA_9 TGFB_9 TGFC_9 TGFD_9 TCFV_9 DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Possible Possible Not possible DMAC Activation Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible 7 TGI7A TGI7B TCI7V TCI7U 8 TGI8A TGI8B TCI8V TCI8U 9 TGI9A TGI9B TGI9C TGI9D TCI9V 10 TGI10A TGI10B TCI10V TCI10U TGFA_10 Possible TGFB_10 Possible TCFV_10 Not possible TCFU_10 Not possible TGFA_11 Possible TGFB_11 Possible TCFV_11 Not possible 11 TGI11A TGI11B TCI11V TCI11U TCFU_11 Not possible Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev. 1.00 Sep. 19, 2008 Page 752 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 32 input capture/compare match interrupts, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has 12 overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has eight underflow interrupts, one each for channels 1, 2, 4, 5, 7, 8, 10, and 11. 11.6 DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 9, Data Transfer Controller (DTC). A total of 32 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. 11.7 DMAC Activation In unit 0 of the TPU, the DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). (The DMAC cannot be activated by unit 1.) In unit 0 of the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC activation sources, one for each channel. Rev. 1.00 Sep. 19, 2008 Page 753 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.8 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of 12 TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 11.9 11.9.1 (1) Operation Timing Input/Output Timing TCNT Count Timing Figure 11.31 shows TCNT count timing in internal clock operation, and figure 11.32 shows TCNT count timing in external clock operation. Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 11.31 Count Timing in Internal Clock Operation Rev. 1.00 Sep. 19, 2008 Page 754 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 11.32 Count Timing in External Clock Operation (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the (TIOC pin) TCNT input clock is generated. Figure 11.33 shows output compare output timing. TCNT input clock N N+1 TCNT TGR N Compare match signal TIOC pin Figure 11.33 Output Compare Output Timing Rev. 1.00 Sep. 19, 2008 Page 755 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Signal Timing Figure 11.34 shows input capture signal timing. Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 11.34 Input Capture Input Signal Timing (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 11.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 11.36 shows the timing when counter clearing by input capture occurrence is specified. Compare match signal Counter clear signal TCNT N H'0000 TGR N Figure 11.35 Counter Clear Timing (Compare Match) Rev. 1.00 Sep. 19, 2008 Page 756 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 11.36 Counter Clear Timing (Input Capture) (5) Buffer Operation Timing Figures 11.37 and 11.38 show the timings in buffer operation. TCNT n n+1 Compare match signal TGRA, TGRB TGRC, TGRD n N N Figure 11.37 Buffer Operation Timing (Compare Match) Rev. 1.00 Sep. 19, 2008 Page 757 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Input capture signal TCNT N N+1 TGRA, TGRB TGRC, TGRD n N N+1 n N Figure 11.38 Buffer Operation Timing (Input Capture) 11.9.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 11.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. TCNT input clock TCNT N N+1 TGR N Compare match signal TGF flag TGI interrupt Figure 11.39 TGI Interrupt Timing (Compare Match) Rev. 1.00 Sep. 19, 2008 Page 758 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (2) TGF Flag Setting Timing in Case of Input Capture Figure 11.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 11.40 TGI Interrupt Timing (Input Capture) Rev. 1.00 Sep. 19, 2008 Page 759 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (3) TCFV Flag/TCFU Flag Setting Timing Figure 11.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 11.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000 TCFV flag TCIV interrupt Figure 11.41 TCIV Interrupt Setting Timing TCNT input clock TCNT (underflow) Underflow signal H'0000 H'FFFF TCFU flag TCIU interrupt Figure 11.42 TCIU Interrupt Setting Timing Rev. 1.00 Sep. 19, 2008 Page 760 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.43 shows the timing for status flag clearing by the CPU, and figure 11.44 shows the timing for status flag clearing by the DTC or DMAC. TSR write cycle T2 T1 Address TSR address Write signal Status flag Interrupt request signal Figure 11.43 Timing for Status Flag Clearing by CPU DTC/DMAC read cycle T1 T2 DTC/DMAC write cycle T1 T2 Address Source address Destination address Status flag Interrupt request signal Figure 11.44 Timing for Status Flag Clearing by DTC/DMAC Activation Rev. 1.00 Sep. 19, 2008 Page 761 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10 Usage Notes 11.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 11.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.45 shows the input clock conditions in phase counting mode. Phase Phase diffedifference Overlap rence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 11.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 1.00 Sep. 19, 2008 Page 762 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= (N + 1) Where f: Counter frequency : Operating frequency N: TGR set value 11.10.4 Contention between TCNT Write and Clear Operations If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 11.46 shows the timing in this case. TCNT write cycle T1 T2 Address TCNT address Write signal Counter clearing signal TCNT N H'0000 Figure 11.46 Contention between TCNT Write and Clear Operations Rev. 1.00 Sep. 19, 2008 Page 763 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.47 shows the timing in this case. TCNT write cycle T2 T1 Address TCNT address Write signal TCNT input clock N TCNT write data M TCNT Figure 11.47 Contention between TCNT Write and Increment Operations Rev. 1.00 Sep. 19, 2008 Page 764 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 11.48 shows the timing in this case. TGR write cycle T2 T1 Address TGR address Write signal Compare match signal TCNT N N+1 Disabled TGR N TGR write data M Figure 11.48 Contention between TGR Write and Compare Match Rev. 1.00 Sep. 19, 2008 Page 765 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11.49 shows the timing in this case. TGR write cycle T2 T1 Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 11.49 Contention between Buffer Register Write and Compare Match Rev. 1.00 Sep. 19, 2008 Page 766 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.50 shows the timing in this case. TGR read cycle T1 T2 Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 11.50 Contention between TGR Read and Input Capture Rev. 1.00 Sep. 19, 2008 Page 767 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.51 shows the timing in this case. TGR write cycle T1 T2 Address TGR address Write signal Input capture signal TCNT M TGR M Figure 11.51 Contention between TGR Write and Input Capture Rev. 1.00 Sep. 19, 2008 Page 768 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.10 Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.52 shows the timing in this case. Buffer register write cycle T1 T2 Buffer register address Address Write signal Input capture signal TCNT N TGR Buffer register M N M Figure 11.52 Contention between Buffer Register Write and Input Capture Rev. 1.00 Sep. 19, 2008 Page 769 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. TCNT input clock TCNT Counter clearing signal TGF Disabled TCFV H'FFFF H'0000 Figure 11.53 Contention between Overflow and Counter Clearing Rev. 1.00 Sep. 19, 2008 Page 770 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.54 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 Address TCNT address Write signal TCNT write data H'FFFF M TCNT TCFV flag Figure 11.54 Contention between TCNT Write and Overflow 11.10.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 11.10.14 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 1.00 Sep. 19, 2008 Page 771 of 1270 REJ09B0466-0100 Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Sep. 19, 2008 Page 772 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. The block diagram of PPG is shown in figure 12.1. 12.1 * * * * * * * Features 16-bit output data Four output groups Selectable output trigger signals Non-overlap mode Can operate together with the data transfer controller (DTC) and the DMA controller (DMAC) Settable inverted output Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 773 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Compare match signals NDERH Control logic PMR NDERL PCR PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Pulse output pins, group 3 PODRH Pulse output pins, group 2 Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL (NDRLH, NDRLL) NDRH (NDRHH, NDRHL) Internal data bus Legend: PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL : PPG output mode register : PPG output control register : Next data enable register H : Next data enable register L : Next data register H : Next data register L : Output data register H : Output data register L Figure 12.1 Block Diagram of PPG Rev. 1.00 Sep. 19, 2008 Page 774 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.2 Input/Output Pins Table 12.1 shows the PPG pin configuration. Table 12.1 Pin Configuration Pin Name PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 0 pulse output Group 1 pulse output Group 2 pulse output Function Group 3 pulse output 12.3 Register Descriptions The PPG has the following registers. * * * * * * * * Next data enable register H (NDERH) Next data enable register L (NDERL) Output data register H (PODRH) Output data register L (PODRL) Next data register H (NDRH) Next data register L (NDRL) PPG output control register (PCR) PPG output mode register (PMR) Rev. 1.00 Sep. 19, 2008 Page 775 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1. * NDERH Bit 7 6 5 4 3 2 1 0 Bit Name NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 15 to 8 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits. * NDERL Bit 7 6 5 4 3 2 1 0 Bit Name NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 7 to 0 When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits. Rev. 1.00 Sep. 19, 2008 Page 776 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. * PODRH Bit 7 6 5 4 3 2 1 0 Bit Name POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 15 to 8 For bits which have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set. * PODRL Bit 7 6 5 4 3 2 1 0 Bit Name POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set. Rev. 1.00 Sep. 19, 2008 Page 777 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. * NDRH (NDRHH, NDRHL)* If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Note: * When pulse output groups 2 and 3 have the same output trigger by PCR settings, the NDRH address is HFF4C. When they have different output triggers, the NDRH addresses corresponding to the groups 2 and 3 are NDRHH (HFF4E) and NDRHL (HFF4C), respectively. Also, when pulse output groups 0 and 1 have the same output trigger by PCR settings, the NDRL address is NDRLH (HFF4D). When they have different output triggers, the NDRL addresses corresponding to the groups 0 and 1 are NDRLL (HFF4F) and HFF4D, respectively. Bit 7 6 5 4 3 2 1 0 Bit Name NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 15 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. If pulse output groups 2 and 3 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. Bit 7 6 5 4 3 to 0 Bit Name NDR15 NDR14 NDR13 NDR12 -- Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W -- Description Next Data Register 15 to 12 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. Reserved 1 is always read and write is disabled. Rev. 1.00 Sep. 19, 2008 Page 778 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Bit 7 to 4 Bit Name -- Initial Value All 1 R/W -- Description Reserved 1 is always read and write is disabled. 3 2 1 0 NDR11 NDR10 NDR9 NDR8 0 0 0 0 R/W R/W R/W R/W Next Data Register 11 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. * NDRL (NDRLH, NDRLL)* If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Note: * When pulse output groups 2 and 3 have the same output trigger by PCR settings, the NDRH address is HFF4C. When they have different output triggers, the NDRH addresses corresponding to the groups 2 and 3 are NDRHH (HFF4E) and NDRHL (HFF4C), respectively. Also, when pulse output groups 0 and 1 have the same output trigger by PCR settings, the NDRL address is NDRLH (HFF4D). When they have different output triggers, the NDRL addresses corresponding to the groups 0 and 1 are NDRLL (HFF4F) and HFF4D, respectively. Bit 7 6 5 4 3 2 1 0 Bit Name NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Rev. 1.00 Sep. 19, 2008 Page 779 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. Bit 7 6 5 4 3 to 0 Bit Name NDR7 NDR6 NDR5 NDR4 -- Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W -- Description Next Data Register 7 to 4 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Reserved 1 is always read and write is disabled. Bit 7 to 4 Bit Name -- Initial Value All 1 R/W -- Description Reserved 1 is always read and write is disabled. 3 2 1 0 NDR3 NDR2 NDR1 NDR0 0 0 0 0 R/W R/W R/W R/W Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Rev. 1.00 Sep. 19, 2008 Page 780 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 12.3.5, PPG Output Mode Register (PMR). Bit 7 6 Bit Name G3CMS1 G3CMS0 Initial Value 1 1 R/W R/W R/W Description Group 3 Compare Match Select 1 and 0 Select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 5 4 G2CMS1 G2CMS0 1 1 R/W R/W Group 2 Compare Match Select 1 and 0 Select output trigger of pulse output group 2. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 3 2 G1CMS1 G1CMS0 1 1 R/W R/W Group 1 Compare Match Select 1 and 0 Select output trigger of pulse output group 1. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 1 0 G0CMS1 G0CMS0 1 1 R/W R/W Group 0 Compare Match Select 1 and 0 Select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 Rev. 1.00 Sep. 19, 2008 Page 781 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 12.4.4, Non-Overlapping Pulse Output. Bit 7 Bit Name G3INV Initial Value 1 R/W R/W Description Group 3 Inversion Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output 6 G2INV 1 R/W Group 2 Inversion Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output 5 G1INV 1 R/W Group 1 Inversion Selects direct output or inverted output for pulse output group 1. 0: Inverted output 1: Direct output 4 G0INV 1 R/W Group 0 Inversion Selects direct output or inverted output for pulse output group 0. 0: Inverted output 1: Direct output Rev. 1.00 Sep. 19, 2008 Page 782 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Bit 3 Bit Name G3NOV Initial Value 0 R/W R/W Description Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 2 G2NOV 0 R/W Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 1 G1NOV 0 R/W Group 1 Non-Overlap Selects normal or non-overlapping operation for pulse output group 1. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 0 G0NOV 0 R/W Group 0 Non-Overlap Selects normal or non-overlapping operation for pulse output group 0. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) Rev. 1.00 Sep. 19, 2008 Page 783 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4 Operation Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. DDR NDER Q Output trigger signal C Q PODR D Pulse output pin Normal output/inverted output Q NDR D Internal data bus Figure 12.2 Overview Diagram of PPG Rev. 1.00 Sep. 19, 2008 Page 784 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N+1 TGRA N Compare match A signal NDRH n PODRH m n PO8 to PO15 m n Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) Rev. 1.00 Sep. 19, 2008 Page 785 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.2 Sample Setup Procedure for Normal Pulse Output Figure 12.4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output compare register (with output disabled). [2] Set the PPG output trigger period. Set TGRA value TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Port and PPG setup Select output trigger Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [10] [3] [4] [5] [6] [7] [2] Normal PPG output Select TGR functions [1] [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR2 to CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. [8] [9] No Figure 12.4 Setup Procedure for Normal Pulse Output (Example) Rev. 1.00 Sep. 19, 2008 Page 786 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value TGRA Compare match TCNT H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PODRH 00 80 C0 40 60 20 30 10 18 08 88 80 C0 PO15 PO14 PO13 PO12 PO11 Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so that the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. Five-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 1.00 Sep. 19, 2008 Page 787 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: * NDR bits are always transferred to PODR bits at compare match A. * At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.6 illustrates the non-overlapping pulse output operation. DDR NDER Q Compare match A Compare match B Pulse output pin C Q PODR D Q NDR D Internal data bus Normal output/inverted output Figure 12.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs. Rev. 1.00 Sep. 19, 2008 Page 788 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Figure 12.7 shows the timing of this operation. Compare match A Compare match B Write to NDR NDR Write to NDR PODR 0 output 0/1 output 0 output 0/1 output Write to NDR here Write to NDR Do not write here to NDR here Do not write to NDR here Figure 12.7 Non-Overlapping Operation and NDR Write Timing Rev. 1.00 Sep. 19, 2008 Page 789 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping pulse output Select TGR functions Set TGR values TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU setup Start counter Compare match A? Yes Set next pulse output data [11] [3] [4] [5] [6] [7] [8] [1] [2] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled). [2] Set the pulse output trigger period in TGRB and the non-overlap period in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR2 to CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. PPG setup [9] [10] No Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example) Rev. 1.00 Sep. 19, 2008 Page 790 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRH 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) Rev. 1.00 Sep. 19, 2008 Page 791 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. 4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 1.00 Sep. 19, 2008 Page 792 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9. TCNT value TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 Time TCNT PODRL 00 95 05 65 41 59 50 56 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.10 Inverted Pulse Output (Example) Rev. 1.00 Sep. 19, 2008 Page 793 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.11 shows the timing of this output. TIOC pin Input capture signal NDR N PODR M N PO M N Figure 12.11 Pulse Output Triggered by Input Capture (Example) Rev. 1.00 Sep. 19, 2008 Page 794 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) 12.5 12.5.1 Usage Notes Module Stop Mode Setting PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 12.5.2 Operation of Pulse Output Pins Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Rev. 1.00 Sep. 19, 2008 Page 795 of 1270 REJ09B0466-0100 Section 12 Programmable Pulse Generator (PPG) Rev. 1.00 Sep. 19, 2008 Page 796 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Section 13 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.1 Features * Selection of seven clock sources The counters can be driven by one of six internal clock signals (/8, /64, /8192, /2, /32, or /1024) or an external clock input * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal * Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output * Provision for cascading of two channels (TMR_0 and TMR_1) Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the lower 8 bits (16-bit count mode) TMR_1 can be used to count TMR_0 compare matches (compare match count mode) * Three independent interrupts Compare match A and B and overflow interrupts can be requested independently * A/D converter conversion start trigger can be generated Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1). Rev. 1.00 Sep. 19, 2008 Page 797 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Internal clock sources /8 /64 /8192 /2 /32 /1024 Counter clock 1 Counter clock 0 Clock select TCORA_0 Compare match A1 Compare match A0 TMCI0 TMCI1 TCORA_1 Comparator A_0 Comparator A_1 TMO0 TMRI0 Overflow 1 Overflow 0 Counter clear 0 Counter clear 1 Control logic Compare match B1 Compare match B0 TCNT_0 TCNT_1 Internal bus Comparator B_0 Comparator B_1 TMO1 TMRI1 TCORB_0 A/D conversion start request signal TCORB_1 TCSR_0 TCSR_1 TCR_0 TCR_1 TCCR_0 Channel 0 (TMR_0) TCCR_1 Channel 1 (TMR_1) CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals Legend: TCORA_0 TCNT_0 TCORB_0 TCSR_0 TCR_0 TCCR_0 : Time constant register A_0 : Timer counter_0 : Time constant register B_0 : Timer control/status register_0 : Timer control register_0 : Timer counter control register_0 TCORA_1 TCNT_1 TCORB_1 TCSR_1 TCR_1 TCCR_1 : Time constant register A_1 : Timer counter_1 : Time constant register B_1 : Timer control/status register_1 : Timer control register_1 : Timer counter control register_1 Figure 13.1 Block Diagram of 8-Bit Timer Module Rev. 1.00 Sep. 19, 2008 Page 798 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the 8-bit timer module. Table 13.1 Pin Configuration Channel 0 Name Timer output pin Timer clock input pin Timer reset input pin 1 Timer output pin Timer clock input pin Timer reset input pin Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Outputs at compare match Inputs external clock for counter Inputs external reset to counter Outputs at compare match Inputs external clock for counter Inputs external reset to counter 13.3 Register Descriptions The 8-bit timer module has the following registers. For details on the module stop control register, refer to section 24.1.2, Module Stop Control Registers H and L (MSTPCRH, MSTPCRL). * * * * * * * * * * * * Timer counter_0 (TCNT_0) Time constant register A_0 (TCORA_0) Time constant register B_0 (TCORB_0) Timer control register_0 (TCR_0) Timer control/status register_0 (TCSR_0) Timer counter control register_0 (TCCR_0) Timer counter_1 (TCNT_1) Time constant register A_1 (TCORA_1) Time constant register B_1 (TCORB_1) Timer control register_1 (TCR_1) Timer control/status register_1 (TCSR_1) Timer counter control register_1 (TCCR_1) Rev. 1.00 Sep. 19, 2008 Page 799 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.3.1 Timer Counter (TCNT) TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a clock. TCNT can be cleared by an external reset input or by a compare match signal A or B. Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00. 13.3.2 Time Constant Register A (TCORA) TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. 13.3.3 Time Constant Register B (TCORB) TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCOBR write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. Rev. 1.00 Sep. 19, 2008 Page 800 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts. Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled 6 CMIEA 0 R/W Compare Match Interrupt Enable A Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt requests (CMIA) are disabled 1: CMFA interrupt requests (CMIA) are enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt requests (OVI) are disabled 1: OVF interrupt requests (OVI) are enabled 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1 and 0 These bits select the method by which TCNT is cleared, in combination with the TMRIS bit in TCCR. See table 13.2. Clock Select 2 to 0 These bits select the clock input to TCNT and the count condition, in combination with the ICKS1 and ICKS0 bits in TCCR. See table 13.3. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Rev. 1.00 Sep. 19, 2008 Page 801 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.3.5 Timer Counter Control Register (TCCR) TCCR selects the TCNT internal clock source and controls the external reset input. Bit 7 to 4 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. 3 TMRIS 0 R/W Timer Reset Input Select Selects the external reset input, in combination with the CCLR1 and CCLR0 bits in TCR. See table 13.2. 2 -- 0 R Reserved This bit is always read as 0 and cannot be modified. 1 0 ICKS1 ICKS0 0 0 R/W R/W Internal Clock Select 1, 0 These bits select the internal clock source, in combination with the CKS2 to CKS0 bits in TCR. See table 13.3. Table 13.2 Reset Input to TCNT and Clearing Condition TCR Bit 1 CCLR1 0 0 1 1 0 0 1 1 Bit 0 CCLR0 0 1 0 1 0 1 0 1 TCCR Bit 3 TMRIS 0 0 0 0 1 1 1 1 Description Clearing is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input Clear by both rising and falling edges of external reset input Clear by falling edge of external reset input Clear by low level of external reset input Clear by high level of external reset input Rev. 1.00 Sep. 19, 2008 Page 802 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Table 13.3 Clock Input to TCNT and Count Condition TCR Channel TMR_0 Bit 2 CKS2 0 0 Bit 1 CKS1 0 0 Bit 0 CKS0 0 1 TCCR Bit 1 ICKS1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 TMR_1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 Bit 0 ICKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Clock input disabled Internal clock, counted at rising edge of /8 Internal clock, counted at rising edge of /2 Internal clock, counted at falling edge of /8 Internal clock, counted at falling edge of /2 Internal clock, counted at rising edge of /64 Internal clock, counted at rising edge of /32 Internal clock, counted at falling edge of /64 Internal clock, counted at falling edge of /32 Internal clock, counted at rising edge of /8192 Internal clock, counted at rising edge of /1024 Internal clock, counted at falling edge of /8192 Internal clock, counted at falling edge of /1024 Counted at TCNT_1 overflow signal* Clock input disabled Internal clock, counted at rising edge of /8 Internal clock, counted at rising edge of /2 Internal clock, counted at falling edge of /8 Internal clock, counted at falling edge of /2 Internal clock, counted at rising edge of /64 Internal clock, counted at rising edge of /32 Internal clock, counted at falling edge of /64 Internal clock, counted at falling edge of /32 Internal clock, counted at rising edge of /8192 Internal clock, counted at rising edge of /1024 Internal clock, counted at falling edge of /8192 Internal clock, counted at falling edge of /1024 Counted at TCNT_0 compare match A* Rev. 1.00 Sep. 19, 2008 Page 803 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) TCR Channel All Bit 2 CKS2 1 Bit 1 CKS1 0 1 1 Bit 0 CKS0 1 0 1 TCCR Bit 1 ICKS1 Bit 0 ICKS0 Description External clock, counted at rising edge External clock, counted at falling edge External clock, counted at both rising and falling edges Note: * If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting. 13.3.6 Timer Control/Status Register (TCSR) TCSR displays status flags, and controls compare match output. * TCSR_0 Bit 7 Bit Name CMFB Initial Value 0 R/W R/(W)* Description Compare Match Flag B [Setting condition] * * * 6 CMFA 0 R/(W)* Set when TCNT matches TCORB Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 [Clearing conditions] Compare Match Flag A [Setting condition] * * * Set when TCNT matches TCORA Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 [Clearing conditions] Rev. 1.00 Sep. 19, 2008 Page 804 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Bit 5 Bit Name OVF Initial Value 0 R/W R/(W)* Description Timer Overflow Flag [Setting condition] Set when TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF 4 ADTE 0 R/W A/D Trigger Enable Selects enabling or disabling of A/D converter start requests by compare match A. 0: A/D converter start requests by compare match A are disabled 1: A/D converter start requests by compare match A are enabled 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Note: Only 0 can be written to, to clear these flags. Rev. 1.00 Sep. 19, 2008 Page 805 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) * TCSR_1 Bit 7 Bit Name CMFB Initial Value 0 R/W R/(W)* Description Compare Match Flag B [Setting condition] * * * 6 CMFA 0 R/(W)* Set when TCNT matches TCORB Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 [Clearing conditions] Compare Match Flag A [Setting condition] * * * Set when TCNT matches TCORA Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 [Clearing conditions] 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] * * Set when TCNT overflows from H'FF to H'00 Cleared by reading OVF when OVF = 1, then writing 0 to OVF [Clearing condition] 4 -- 1 R Reserved This bit is always read as 1 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 806 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Bit 3 2 Bit Name OS3 OS2 Initial Value 0 0 R/W R/W R/W Description Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Note: * Only 0 can be written to, to clear these flags. Rev. 1.00 Sep. 19, 2008 Page 807 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.4 13.4.1 Operation Pulse Output Figure 13.2 shows an example in which the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: [1] In TCR, the CCLR1 bit is cleared to 0 and the CCLR0 bit is set to 1 so that TCNT is cleared at a TCORA compare match. [2] In TCSR, the OS3 to OS0 bits are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 13.2 Example of Pulse Output Rev. 1.00 Sep. 19, 2008 Page 808 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.4.2 Reset Input Figure 13.3 shows an example in which the 8-bit timer is used to generate a pulse output with a selected delay in response to the TMRI input. The control bits are set as follows: [1] The CCLR0 bit in TCR is set to 1 and the TMRIS bit in TCCR is set to 1 so that TCNT is cleared at the high level of the TMRI input. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses whose delay from the TMRI input is determined by TCORA and the pulse width determined by (TCORB - TCORA). TCORB TCORA TCNT H'00 TMRI TMO Figure 13.3 Example of Reset Input Rev. 1.00 Sep. 19, 2008 Page 809 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.5 13.5.1 Operation Timing TCNT Incrementation Timing Figure 13.4 shows the count timing for internal clock input. Figure 13.5 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Internal clock Clock input to TCNT TCNT N-1 N N+1 Figure 13.4 Count Timing for Internal Clock Input External clock input pin Clock input to TCNT TCNT N-1 N N+1 Figure 13.5 Count Timing for External Clock Input Rev. 1.00 Sep. 19, 2008 Page 810 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 13.6 shows this timing. TCNT N N+1 TCOR Compare match signal N CMF Figure 13.6 Timing of CMF Setting Rev. 1.00 Sep. 19, 2008 Page 811 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.5.3 Timing of Timer Output when Compare-Match Occurs When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Figure 13.7 shows the timing when the output is set to toggle at compare match A. Compare match A signal Timer output pin Figure 13.7 Timing of Timer Output 13.5.4 Timing of Compare Match Clear TCNT is cleared when compare match A or B occurs, depending on the settings of the CCLR1 and CCLR0 bits in TCR and the TMRIS bit in TCCR. Figure 13.8 shows the timing of this operation. Compare match signal TCNT N H'00 Figure 13.8 Timing of Compare Match Clear Rev. 1.00 Sep. 19, 2008 Page 812 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.5.5 Timing of TCNT External Reset TCNT is cleared at the rising edge, falling edge, low level, or high level of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR and the TMRIS bit in TCCR. The clear pulse width must be at least 1.5 states for a single edge and at least 2.5 states for both edges. Figure 13.9 shows the timing of this operation. External reset input pin Clear signal TCNT N-1 N H'00 Figure 13.9 Timing of Clearance by External Reset 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of this operation. TCNT H'FF H'00 Overflow signal OVF Figure 13.10 Timing of OVF Setting Rev. 1.00 Sep. 19, 2008 Page 813 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). In this case, the timer operates as below. 13.6.1 16-Bit Counter Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. [1] Setting of compare match flags * The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs. * The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs. [2] Counter clear specification * If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the 16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter clear by the TMRI0 pin has also been set. * The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. [3] Pin output * Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare match conditions. * Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare match conditions. 13.6.2 Compare Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A's for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel. Rev. 1.00 Sep. 19, 2008 Page 814 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.7 13.7.1 Interrupt Sources Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 13.4. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 13.4 8-Bit Timer Interrupt Sources Name CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt Source TCORA_0 compare match TCORB_0 compare match TCNT_0 overflow TCORA_1 compare match TCORB_1 compare match TCNT_1 overflow Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Low Low High Priority High 13.7.2 A/D Converter Activation The A/D converter can be activated only by TMR_0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of TMR_0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Rev. 1.00 Sep. 19, 2008 Page 815 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.8 13.8.1 Usage Notes Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 13.11 shows this operation. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 13.11 Contention between TCNT Write and Clear Rev. 1.00 Sep. 19, 2008 Page 816 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.8.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 13.12 shows this operation. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.12 Contention between TCNT Write and Increment Rev. 1.00 Sep. 19, 2008 Page 817 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.8.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 13.13. TCOR write cycle by CPU T1 T2 Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Inhibited Figure 13.13 Contention between TCOR Write and Compare Match Rev. 1.00 Sep. 19, 2008 Page 818 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) 13.8.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.5. Table 13.5 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High 13.8.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 13.6 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1, CKS0, ICKS1, and ICKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the rising edge or falling edge of the internal clock pulse is detected. Therefore, when the falling edge is selected, if clock switching causes a change from high to low level, as shown in case 3 in table 13.6, a TCNT clock pulse is generated and the TCNT incremented on the assumption that the switchover is a falling edge. This is the same as when the rising edge is selected. The erroneous incrementation can also happen when switching between the rising edge and falling edge of an internal clock or switching between internal and external clocks. Rev. 1.00 Sep. 19, 2008 Page 819 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Table 13.6 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of Modifying CKS1, CKS0, ICKS1, and ICKS0 Bits Switching from low to low*1 No. 1 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N CKS bit write N+1 2 Switching from low to high*2 Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write 3 Switching from high to low*3 Clock before swichover Clock after swichover *4 TCNT clock TCNT N N+1 CKS bit write N+2 Rev. 1.00 Sep. 19, 2008 Page 820 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) No. 4 Timing of Switchover by Means of Modifying CKS1, CKS0, ICKS1, and ICKS0 Bits Switching from high to high TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 13.8.6 Mode Setting with Cascaded Connection If 16-bit counter mode and compare match count mode are specified at the same time, input clocks for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter and compare match count modes simultaneously. 13.8.7 Module Stop Mode Setting Operation of the TMR can be disabled or enabled using the module stop control register. The initial setting is for operation of the TMR to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 13.8.8 Interrupts in Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC and DMAC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 1.00 Sep. 19, 2008 Page 821 of 1270 REJ09B0466-0100 Section 13 8-Bit Timers (TMR) Rev. 1.00 Sep. 19, 2008 Page 822 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT is shown in figure 14.1. 14.1 Features * Selectable from eight counter input clocks * Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode * If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire chip is reset at the same time. Interval Timer Mode * If the counter overflows, the WDT generates an interval timer interrupt (WOVI). Rev. 1.00 Sep. 19, 2008 Page 823 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) Overflow WOVI (interrupt request signal) WDTOVF Internal reset signal* Interrupt control Clock Clock select Reset control /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources RSTCSR TCNT TSCR Bus interface Module bus WDT Legend: : Timer control/status register TCSR : Timer counter TCNT RSTCSR : Reset control/status register Note: * An internal reset signal can be generated by the register setting. Figure 14.1 Block Diagram of WDT 14.2 Input/Output Pin Table 14.1 shows the WDT pin configuration. Table 14.1 Pin Configuration Name Watchdog timer overflow Symbol WDTOVF I/O Output Function Outputs counter overflow signal in watchdog timer mode Rev. 1.00 Sep. 19, 2008 Page 824 of 1270 REJ09B0466-0100 Internal bus Section 14 Watchdog Timer (WDT) 14.3 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 14.6.1, Notes on Register Access. * Timer counter (TCNT) * Timer control/status register (TCSR) * Reset control/status register (RSTCSR) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Bit 7 Bit Name OVF Initial Value 0 R/W R/(W)* Description Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows in interval timer mode (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF Rev. 1.00 Sep. 19, 2008 Page 825 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) Bit 6 Bit Name WT/IT Initial Value 0 R/W R/W Description Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output. 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow frequency for = 20 MHz is enclosed in parentheses. 000: Clock /2 (frequency: 25.6 s) 001: Clock /64 (frequency: 819.2 s) 010: Clock /128 (frequency: 1.6 ms) 011: Clock /512 (frequency: 6.6 ms) 100: Clock /2048 (frequency: 26.2 ms) 101: Clock /8192 (frequency: 104.9 ms) 110: Clock /32768 (frequency: 419.4 ms) 111: Clock /131072 (frequency: 1.68 s) Note: * Only a write of 0 is permitted, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 826 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) 14.3.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Bit 7 Bit Name WOVF Initial Value 0 R/W R/(W)* Description Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, and then writing 0 to WOVF 6 RSTE 0 R/W Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 -- 0 R/W Reserved Can be read and written, but does not affect operation. 4 to 0 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. Note: * Only a write of 0 is permitted, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 827 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) 14.4 14.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs. This WDTOVF signal can be used to reset the chip internally in watchdog timer mode. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets this LSI internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. The internal reset signal is output for 518 states. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, an internal reset signal is generated to the entire chip. Rev. 1.00 Sep. 19, 2008 Page 828 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) TCNT count Overflow H'FF H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT Time WDTOVF signal 132 states*2 Internal reset signal*1 518 states Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Figure 14.2 Operation in Watchdog Timer Mode 14.4.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1. Rev. 1.00 Sep. 19, 2008 Page 829 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT=0 TME=1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request generation Figure 14.3 Operation in Interval Timer Mode Rev. 1.00 Sep. 19, 2008 Page 830 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) 14.5 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 14.2 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Impossible 14.6 14.6.1 Usage Notes Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 14.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer instruction cannot perform writing to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0 to the WOVF bit, satisfy the lower condition shown in figure 14.4. If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, satisfy the above condition shown in figure 14.4. If satisfied, the transfer instruction writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the WOVF bit. Rev. 1.00 Sep. 19, 2008 Page 831 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) TCNT write or Writing to RSTE bit in RSTCSR 15 Address: H'FFBC (TCNT) H'FFBE (RSTCSR) TCSR write Address: H'FFBC (TCSR) 15 H'A5 8 7 Write data 0 8 H'5A 7 Write data 0 Writing 0 to WOVF bit in RSTCSR Address: H'FFBE (RSTCSR) 15 H'A5 8 7 H'00 0 Writing to RSTE bit in RSTCSR Address: H'FFBE (RSTCSR) 15 H'5A 8 7 Write data 0 Figure 14.4 Writing to TCNT, TCSR, and RSTCSR (2) Reading TCNT, TCSR, and RSTCSR These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR. Rev. 1.00 Sep. 19, 2008 Page 832 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) 14.6.2 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this operation. TCNT write cycle T1 T2 Next cycle Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.5 Contention between TCNT Write and Increment 14.6.3 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev. 1.00 Sep. 19, 2008 Page 833 of 1270 REJ09B0466-0100 Section 14 Watchdog Timer (WDT) 14.6.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 14.6.6 System Reset by WDTOVF Signal If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 14.6. This LSI Reset input RES Reset signal to entire system WDTOVF Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example) Rev. 1.00 Sep. 19, 2008 Page 834 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Section 15 Serial Communication Interface (SCI, IrDA) This LSI has five independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function) in asynchronous mode. The SCI also supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an asynchronous serial communication interface extension function. One of the five SCI channels (SCI_0) can generate an IrDA communication waveform conforming to IrDA specification version 1.0. Figure 15.1 shows a block diagram of the SCI. 15.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source (except for in Smart Card interface mode). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources transmit-end, transmit-data-empty, receive-data-full, and receive error that can issue requests. The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (DTC) or DMA controller (DMAC). * Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 835 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Asynchronous Mode Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error * Average transfer rate generator (SCI_2 only): 115.152 or 460.606 kbps at 10.667-MHz operation 115.196, 460.784, or 720 kbps at 16-MHz operation 720 kbps at 32-MHz operation Clocked Synchronous Mode * Data length: 8 bits * Receive error detection: Overrun errors detected Smart Card Interface * Automatic transmission of error signal (parity error) in receive mode * Error signal detection and automatic data retransmission in transmit mode * Direct convention and inverse convention both supported * * * * * Rev. 1.00 Sep. 19, 2008 Page 836 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR SEMR Transmission/ reception control BRR Baud rate generator /4 /16 /64 Clock TxD Parity check SCK Parity generation External clock TEI TXI RXI ERI : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register : Serial control register : Serial status register : Smart card mode register : Bit rate register : Serial extension mode register (only in SCI_2) Legend: RSR RDR TSR TDR SMR SCR SSR SCMR BRR SEMR Average transfer rate generator (SCI_2) 10.667 MHz operation * 115.152 kbps * 460.606 kbps 16 MHz operation * 115.196 kbps * 460.784 kbps * 720 kbps 32 MHz operation * 720 kbps Figure 15.1 Block Diagram of SCI Rev. 1.00 Sep. 19, 2008 Page 837 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the serial communication interface. Table 15.1 Pin Configuration Channel 0 Pin Name* SCK0 RxD0/IrRxD TxD0/IrTxD 1 SCK1 RxD1 TxD1 2 SCK2 RxD2 TxD2 3 SCK3 RxD3 TxD3 4 SCK4 RxD4 TxD4 Note: * I/O I/O Input Output I/O Input Output I/O Input Output I/O Input Output I/O Input Output Function Channel 0 clock input/output Channel 0 receive data input (normal/IrDA) Channel 0 transmit data output (normal/IrDA) Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit data output Channel 2 clock input/output Channel 2 receive data input Channel 2 transmit data output Channel 3 clock input/output Channel 3 receive data input Channel 3 transmit data output Channel 4 clock input/output Channel 4 receive data input Channel 4 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. Rev. 1.00 Sep. 19, 2008 Page 838 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.3 Register Descriptions The SCI has the following registers. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions partially differ. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Receive shift register_0 (RSR_0) Transmit shift register_0 (TSR_0) Receive data register_0 (RDR_0) Transmit data register_0 (TDR_0) Serial mode register_0 (SMR_0) Serial control register_0 (SCR_0) Serial status register_0 (SSR_0) Smart card mode register_0 (SCMR_0) Bit rate register_0 (BRR_0) IrDA control register_0 (IrCR_0) Receive shift register_1 (RSR_1) Transmit shift register_1 (TSR_1) Receive data register_1 (RDR_1) Transmit data register_1 (TDR_1) Serial mode register_1 (SMR_1) Serial control register_1 (SCR_1) Serial status register_1 (SSR_1) Smart card mode register_1 (SCMR_1) Bit rate register_1 (BRR_1) Receive shift register_2 (RSR_2) Transmit shift register_2 (TSR_2) Receive data register_2 (RDR_2) Transmit data register_2 (TDR_2) Serial mode register_2 (SMR_2) Serial control register_2 (SCR_2) Serial status register_2 (SSR_2) Smart card mode register_2 (SCMR_2) Bit rate register_2 (BRR_2) Serial extension mode register_2 (SEMR_2) Rev. 1.00 Sep. 19, 2008 Page 839 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) * * * * * * * * * * * * * * * * * * Receive shift register_3 (RSR_3) Transmit shift register_3 (TSR_3) Receive data register_3 (RDR_3) Transmit data register_3 (TDR_3) Serial mode register_3 (SMR_3) Serial control register_3 (SCR_3) Serial status register_3 (SSR_3) Smart card mode register_3 (SCMR_3) Bit rate register_3 (BRR_3) Receive shift register_4 (RSR_4) Transmit shift register_4 (TSR_4) Receive data register_4 (RDR_4) Transmit data register_4 (TDR_4) Serial mode register_4 (SMR_4) Serial control register_4 (SCR_4) Serial status register_4 (SSR_4) Smart card mode register_4 (SCMR_4) Bit rate register_4 (BRR_4) Receive Shift Register (RSR) 15.3.1 RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. Rev. 1.00 Sep. 19, 2008 Page 840 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. 15.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting. TSR cannot be directly accessed by the CPU. 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the on-chip baud rate generator clock source. Some bit functions of SMR differ in normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0) Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. Rev. 1.00 Sep. 19, 2008 Page 841 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 5 Bit Name PE Initial Value 0 R/W R/W Description Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked regardless of the STOP bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)). Rev. 1.00 Sep. 19, 2008 Page 842 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of 1 bit), and clock output control mode addition is performed. For details, refer to section 15.7.8, Clock Output Control. 6 BLK 0 R/W When this bit is set to 1, the SCI operates in block transfer mode. For details on block transfer mode, refer to section 15.7.3, Block Transfer Mode. Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. In Smart Card interface mode, this bit must be set to 1. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. For details on setting this bit in Smart Card interface mode, refer to section 15.7.2, Data Format (Except for Block Transfer Mode). 5 PE 0 R/W Rev. 1.00 Sep. 19, 2008 Page 843 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 3 2 Bit Name BCP1 BCP0 Initial Value 0 0 R/W R/W R/W Description Basic Clock Pulse 1 and 0 These bits, in combination with the BCP2 bit in SCMR, select the number of basic clock cycles in a 1-bit transfer interval in Smart Card interface mode. BCP2 to BCP0 Settings: 000: 93 clock cycles (S = 93) 001: 128 clock cycles (S = 128) 010: 186 clock cycles (S = 186) 011: 512 clock cycles (S = 512) 100: 32 clock cycles (S = 32) (initial value) 101: 64 clock cycles (S = 64) 110: 372 clock cycles (S = 372) 111: 256 clock cycles (S = 256) For details, refer to section 15.7.4, Receive Data Sampling Timing and Reception Margin. S stands for the value of S in BRR (see section 15.3.9, Bit Rate Register (BRR)). 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)). Rev. 1.00 Sep. 19, 2008 Page 844 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.6 Serial Control Register (SCR) SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer/receive clock source. For details on interrupt requests, refer to section 15.9, Interrupt Sources. Some bit functions of SCR differ in normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit s set to 1, transmission is enabled. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. The TDRE flag in SSR is fixed at 1 if transmission is disabled by clearing this bit to 0. Rev. 1.00 Sep. 19, 2008 Page 845 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 4 Bit Name RE Initial Value 0 R/W R/W Description Receive Enable When this bit is set to 1, reception is enabled. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 15.5, Multiprocessor Communication Function. When receive data including MPB = 0 in SSR is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled. TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. Rev. 1.00 Sep. 19, 2008 Page 846 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1 and 0 Selects the clock source and SCK pin function. Asynchronous mode 00: On-chip baud rate generator SCK pin functions as I/O port 01: On-chip baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clocked synchronous mode 0x: Internal clock (SCK pin functions as clock output) 1x: External clock (SCK pin functions as clock input) Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 847 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. The TDRE flag in SSR is fixed at 1 if transmission is disabled by clearing this bit to 0. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode. Rev. 1.00 Sep. 19, 2008 Page 848 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 2 1 0 Bit Name TEIE CKE1 CKE0 Initial Value 0 0 0 R/W R/W R/W R/W Description Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. Clock Enable 1 and 0 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 15.7.8, Clock Output Control. When the GM bit in SMR is 0: 00: Output disabled (SCK pin can be used as an I/O port pin) 01: Clock output 1x: Reserved When the GM bit in SMR is 1: 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output Legend: x: Don't care Rev. 1.00 Sep. 19, 2008 Page 849 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0) Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR, and data writing to TDR is enabled. When 0 is written to TDRE after reading TDRE =1 When the DMAC or DTC is activated by a TXI interrupt request and transfers data to TDR [Clearing conditions] * * 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF =1 When the DMAC or DTC is activated by an RXI interrupt and transferred data from RDR [Clearing conditions] * * The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Exercise care because if reception of the next data is completed while the RDRF flag is set to 1, an overrun error occurs and receive data will be lost. Rev. 1.00 Sep. 19, 2008 Page 850 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 5 Bit Name ORER Initial Value 0 R/W R/(W)* Description Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. When 0 is written to ORER after reading ORER = 1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. [Clearing condition] * Rev. 1.00 Sep. 19, 2008 Page 851 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 4 Bit Name FER Initial Value 0 R/W R/(W)* Description Framing Error Indicates that a framing error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] * When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition] * When 0 is written to FER after reading FER = 1 The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 3 PER 0 R/(W)* Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] * When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition] * When 0 is written to PER after reading PER = 1 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. Rev. 1.00 Sep. 19, 2008 Page 852 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 2 Bit Name TEND Initial Value 1 R/W R Description Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after reading TDRE =1 When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR [Clearing conditions] * * 1 MPB 0 R Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT sets the multiprocessor bit to be added to the transmit data. Note: * Only 0 can be written, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 853 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR, and data writing to TDR is enabled. When 0 is written to TDRE after reading TDRE =1 When the DMAC or DTC is activated by a TXI interrupt request and transfers data to TDR [Clearing conditions] * * 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF =1 When the DMAC or DTC is activated by an RXI interrupt and transferred data from RDR [Clearing conditions] * * The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Exercise care because if reception of the next data is completed while the RDRF flag is set to 1, an overrun error occurs and receive data will be lost. Rev. 1.00 Sep. 19, 2008 Page 854 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 5 Bit Name ORER Initial Value 0 R/W R/(W)* Description Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 4 ERS 0 R/(W)* Error Signal Status [Setting condition] * When the low level of the error signal is sampled When 0 is written to ERS after reading ERS = 1 [Clearing conditions] * Rev. 1.00 Sep. 19, 2008 Page 855 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 3 Bit Name PER Initial Value 0 R/W R/(W)* Description Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] * When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. [Clearing condition] * When 0 is written to PER after reading PER = 1 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. Rev. 1.00 Sep. 19, 2008 Page 856 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 2 Bit Name TEND Initial Value 1 R/W R Description Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When the TE bit in SCR is 0 and the ERS bit is also 0 If the ERS bit is 0 and the TDRE bit is 1 after the specified interval after transmission of 1byte data Timing to set this bit differs according to the register settings. GM = 0, BLK = 0: 2.5 etu after transmission GM = 0, BLK = 1: 1.5 etu after transmission GM = 1, BLK = 0: 1.0 etu after transmission GM = 1, BLK = 1: 1.0 etu after transmission [Clearing conditions] * * When 0 is written to TEND after reading TEND =1 When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR 1 0 Note: MPB MPBT * 0 0 R R/W Multiprocessor Bit This bit is not used in Smart Card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in Smart Card interface mode. Only 0 can be written, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 857 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects Smart Card interface mode and its format. Bit 7 Bit Name BCP2 Initial Value 1 R/W R/W Description Basic Clock Pulse 2 Selects, in combination with the BCP1 and BCP0 bits in SMR, the number of basic clock cycles in a 1-bit transfer interval in Smart Card interface mode. For the settings, refer to section 15.3.5, Serial Mode Register (SMR). 6 to 4 3 SDIR All 1 0 R/W Reserved These bits are always read as 1. Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits. For 7-bit data, LSB-first is fixed. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 0 SMIF 1 0 R/W Reserved This bit is always read as 1. Smart Card Interface Mode Select This bit is set to 1 to make the SCI operate in Smart Card interface mode. 0: Normal asynchronous mode or clocked synchronous mode 1: Smart Card interface mode Rev. 1.00 Sep. 19, 2008 Page 858 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Table 15.2 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous Mode Clocked Synchronous Mode Smart Card Interface Mode Bit Rate B= x 106 64 x 2 2n-1 x (N + 1) x 106 8 x 2 2n-1 x (N + 1) x 106 S x 2 2n+1 x (N + 1) Error (%) = { x 106 B x S x 2 2n+1 x (N + 1) - 1 } x 100 Error B= B= Note: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following tables. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 SCMR Setting BCP2 0 0 0 0 1 1 1 1 BCP1 0 0 1 1 0 0 1 1 SMR Setting BCP0 0 1 0 1 0 1 0 1 S 93 128 186 512 32 64 372 256 Rev. 1.00 Sep. 19, 2008 Page 859 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock cycles in a 1-bit transfer interval) can be selected. For details, refer to section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.5 and 15.7 show the maximum bit rates with external clock input. Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency (MHz) 8 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.73 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.38 1.70 0.00 1.70 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.40 0.00 -2.40 Rev. 1.00 Sep. 19, 2008 Page 860 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency (MHz) 12.288 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.34 0.00 n 2 2 2 1 1 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.94 -0.94 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.69 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.73 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 Operating Frequency (MHz) 17.2032 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 18 N 79 233 116 233 116 233 116 58 28 17 14 19.6608 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.01 0.00 -2.40 20 n 3 3 2 2 1 1 0 0 0 0 0 n 3 2 2 1 1 0 0 0 0 0 0 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.73 0.00 N 88 64 129 64 129 64 129 64 32 19 15 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.38 0.00 1.70 Rev. 1.00 Sep. 19, 2008 Page 861 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency (MHz) 25 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 30 Error (%) -0.02 0.47 -0.15 0.47 -0.15 0.47 -0.15 0.47 -0.76 0.00 1.70 33 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 0.16 -0.35 -0.35 0.00 1.70 N 110 80 162 80 162 80 162 80 40 24 19 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 n 3 3 2 2 1 1 0 0 0 0 0 N 145 106 214 106 214 106 214 106 53 32 26 Error (%) 0.33 0.39 -0.07 0.39 -0.07 0.39 -0.07 0.39 -0.54 0.00 -0.54 Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 30 33 Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 781250 937500 1031250 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 1.00 Sep. 19, 2008 Page 862 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 30 33 External Input Clock (MHz) 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 6.2500 7.5000 8.2500 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 390625 468750 515625 Rev. 1.00 Sep. 19, 2008 Page 863 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate (bit/s) n 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* 1 1 0 0 0 0 0 0 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 2 1 1 0 0 0 0 0 0 0 0 124 249 124 199 99 49 19 9 4 1 0* 3 2 2 1 0 0 0 0 97 155 77 155 249 124 62 24 3 3 2 2 1 1 0 0 0 0 0 233 116 187 93 187 74 149 74 29 14 2 3 2 2 1 1 0 0 0 128 205 102 205 82 164 82 32 Operating Frequency (MHz) 8 N n 10 N n 16 N n 20 N n 25 N n 30 N n 33 N Legend: Blank: Cannot be set. : Can be set, but there will be a degree of error. *: Continuous transfer is not possible. Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) 8 10 12 14 16 External Input Clock (MHz) 1.3333 1.6667 2.0000 2.3333 2.6667 Maximum Bit Rate (bit/s) 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 (MHz) 18 20 25 30 33 External Input Clock (MHz) 3.0000 3.3333 4.1667 5.0000 5.5000 Maximum Bit Rate (bit/s) 3000000.0 3333333.3 4166666.7 5000000.0 5500000.0 Rev. 1.00 Sep. 19, 2008 Page 864 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) Operating Frequency (MHz) 10.00 Bit Rate (bit/s) 9600 n 0 N 1 Error (%) 30.00 n 0 10.7136 N 1 Error (%) 25.00 n 0 13.00 N 1 Error (%) 8.99 n 0 14.2848 N 1 Erro r (%) 0.00 Operating Frequency (MHz) 16.00 Bit Rate (bit/s) 9600 n 0 N 1 Error (%) 12.01 n 0 18.00 N 2 Error (%) 15.99 n 0 20.00 N 2 Error (%) 6.66 n 0 25.00 N 3 Erro r (%) 12.4 9 Operating Frequency (MHz) 30.00 Bit Rate (bit/s) 9600 n 0 N 3 Error (%) 5.01 n 0 33.00 N 4 Error (%) 7.59 Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) (MHz) 10.00 10.7136 13.00 14.2848 16.00 Maximum Bit Rate (bit/s) 13441 14400 17473 19200 21505 n 0 0 0 0 0 N 0 0 0 0 0 (MHz) 18.00 20.00 25.00 30.00 33.00 Maximum Bit Rate (bit/s) 24194 26882 33602 40323 44355 n 0 0 0 0 0 N 0 0 0 0 0 Rev. 1.00 Sep. 19, 2008 Page 865 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.10 IrDA Control Register (IrCR) IrCR selects the function of SCI_0. Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Specifies normal SCI mode or IrDA mode for SCI_0 input/output. 0: Pins TxD0/IrTxD and RxD0/IrRxD function as TxD0 and RxD0 1: Pins TxD0/IrTxD and RxD0/IrRxD function as IrTxD and IrRxD 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R/W R/W R/W IrDA Clock Select 2 to 0 Specifies the high pulse width in IrTxD output pulse encoding when the IrDA function is enabled. 000: Pulse width = B x 3/16 (3/16 of bit rate) 001: Pulse width = /2 010: Pulse width = /4 011: Pulse width = /8 100: Pulse width = /16 101: Pulse width = /32 110: Pulse width = /64 111: Pulse width = /128 3 IrTxINV 0 R/W IrTx Data Invert Specifies the logic level of the IrTxD output to be inverted. When inversion is performed, the high pulse width specified by bits 6 to 4 becomes the low pulse width. 0: Transmit data is used as IrTxD output without change 1: Transmit data is inverted before used as IrTxD output Rev. 1.00 Sep. 19, 2008 Page 866 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 2 Bit Name IrRxINV Initial Value 0 R/W R/W Description IrRx Data Invert Specifies the logic level of the IrRxD output to be inverted. When inversion is performed, the high pulse width specified by bits 6 to 4 becomes the low pulse width. 0: Transmit data is used as IrRxD output without change 1: Transmit data is inverted before used as IrRxD output 1, 0 All 0 Reserved These bits are always read as 0 and cannot be modified. 15.3.11 Serial Extension Mode Register (SEMR) SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by selecting the average transfer rate. Bit Bit Name Initial Value Undefined R/W Description Reserved If these bits are read, an undefined value will be returned and cannot be modified. 3 ABCS 0 R/W Asynchronous basic clock selection (valid only in asynchronous mode) Selects the basic clock for 1-bit period in asynchronous mode. 0: Operates on a basic clock with a frequency of 16 times the transfer rate. 1: Operates on a basic clock with a frequency of 8 times the transfer rate. 7 to 4 Rev. 1.00 Sep. 19, 2008 Page 867 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Bit 2 1 0 Bit Name ACS2 ACS1 ACS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Asynchronous clock source selection (valid when CKE1 = 1 in asynchronous mode) Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS. 000: External clock input 001: Selects 115.152 kbps which is the average transfer rate dedicated for = 10.667 MHz. (Operates on a basic clock with a frequency of 16 times the transfer rate.) 010: Selects 460.606 kbps which is the average transfer rate dedicated for = 10.667 MHz. (Operates on a basic clock with a frequency of 8 times the transfer rate.) 011: Selects 720 kbps which is the average transfer rate dedicated for = 32 MHz. (Operates on a basic clock with a frequency of 16 times the transfer rate.) 100: Reserved 101: Selects 115.196 kbps which is the average transfer rate dedicated for = 16 MHz (Operates on a basic clock with a frequency of 16 times the transfer rate.) 110: Selects 460.784 kbps which is the average transfer rate dedicated for = 16 MHz (Operates on a basic clock with a frequency of 16 times the transfer rate.) 111: Selects 720 kbps which is the average transfer rate dedicated for = 16 MHz (Operates on a basic clock with a frequency of 8 times the transfer rate.) Note that the average transfer rate does not correspond to the frequency other than 10.667, 16, or 32 MHz. Rev. 1.00 Sep. 19, 2008 Page 868 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a doublebuffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 1 1 1 Transmit/receive data 7 or 8 bits Parity Stop bit(s) bit 1 bit, or none 1 or 2 bits One unit of transfer data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 15.4.1 Data Transfer Format Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 15.5, Multiprocessor Communication Function. Rev. 1.00 Sep. 19, 2008 Page 869 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend: S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit Rev. 1.00 Sep. 19, 2008 Page 870 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched at the middle of each bit by sampling the data at the rising edge of the 8th pulse of the basic clock as shown in figure 15.3. Thus the reception margin in asynchronous mode is given by formula (1) below. M = { (0.5 - 1 D - 0.5 ) - (L - 0.5) F - (1 + F) } x 100 [%] 2N N ... Formula (1) Where M: Reception Margin N: Ratio of bit rate to clock (N = 16) D: Clock duty cycle (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula below. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal base clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 1.00 Sep. 19, 2008 Page 871 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Rev. 1.00 Sep. 19, 2008 Page 872 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Start of initialization Clear TE and RE bits in SCR to 0 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 15.5 Sample SCI Initialization Flowchart Rev. 1.00 Sep. 19, 2008 Page 873 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.5 Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 15.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Sep. 19, 2008 Page 874 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-dataempty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 15.7 Sample Serial Transmission Flowchart Rev. 1.00 Sep. 19, 2008 Page 875 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. 1 Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ERI interrupt request generated by framing error 1 frame Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Sep. 19, 2008 Page 876 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception. Table 15.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains its state before data reception. Rev. 1.00 Sep. 19, 2008 Page 877 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PER FER ORER = 1? ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error handling be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by an RXI interrupt and the RDR value is read. Figure 15.9 Sample Serial Reception Data Flowchart (1) Rev. 1.00 Sep. 19, 2008 Page 878 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Data Flowchart (2) Rev. 1.00 Sep. 19, 2008 Page 879 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle to the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 15.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends communication data with a 1 multiprocessor bit added to the ID code of the receiving station. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 1.00 Sep. 19, 2008 Page 880 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB= 1) ID transmission cycle = receiving station specification H'AA (MPB= 0) Data transmission cycle = data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Rev. 1.00 Sep. 19, 2008 Page 881 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 1.00 Sep. 19, 2008 Page 882 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.12 shows an example of SCI operation for multiprocessor format reception. Rev. 1.00 Sep. 19, 2008 Page 883 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 1 Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID1 If not this station's ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station's ID 1 Start bit Data (ID2) MPB D0 D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 0 1 Idle state (mark state) MPIE RDRF RDR value ID1 ID2 Data2 MPIE bit set to 1 again MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine Matches this station's ID, so reception continues, and data is received in RXI interrupt handling routine (b) Data matches station's ID Figure 15.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 1.00 Sep. 19, 2008 Page 884 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error handling and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ORER = 1? No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR [2] Yes [3] FER ORER = 1? No Read RDRF flag in SSR Yes [4] No RDRF = 1? Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error handling (Continued on next page) Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 1.00 Sep. 19, 2008 Page 885 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.00 Sep. 19, 2008 Page 886 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. One unit of transfer data (character or frame) * * Serial clock LSB Serial data Don't care MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Bit 0 Note: * High except in continuous transfer Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First) 15.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Rev. 1.00 Sep. 19, 2008 Page 887 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Start of initialization Clear TE and RE bits in SCR to 0 Set data transfer format in SMR and SCMR [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE and RE bits in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enable the TxD and RxD pins to be used. [2] Set value in BRR Wait [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 15.15 Sample SCI Initialization Flowchart 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. Rev. 1.00 Sep. 19, 2008 Page 888 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 15.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine 1 frame TEI interrupt request generated Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev. 1.00 Sep. 19, 2008 Page 889 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-dataempty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes Clear TE bit in SCR to 0 Figure 15.17 Sample Serial Transmission Flowchart Rev. 1.00 Sep. 19, 2008 Page 890 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 15.18 Example of SCI Operation in Reception Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart for serial data reception. Rev. 1.00 Sep. 19, 2008 Page 891 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER = 1? No [2] [3] Error processing (Continued below) [2] [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by a receivedata-full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Error handling Overrun error handling Clear ORER flag in SSR to 0 Figure 15.19 Sample Serial Reception Flowchart Rev. 1.00 Sep. 19, 2008 Page 892 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev. 1.00 Sep. 19, 2008 Page 893 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error handling: Read ORER flag in SSR Yes [3] Error handling ORER = 1? No If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-dataempty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive-data-full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 1.00 Sep. 19, 2008 Page 894 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.7 Operation in Smart Card Interface Mode The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 15.7.1 Pin Connection Example Figure 15.21 shows an example of connection with the Smart Card. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. When the clock generated on the SCI is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal. VCC TxD RxD SCK Rx (port) This LSI Connected equipment Data line Clock line Reset line I/O CLK RST IC card Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections Rev. 1.00 Sep. 19, 2008 Page 895 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.7.2 Data Format (Except for Block Transfer Mode) Figure 15.22 shows the transfer data format in Smart Card interface mode. * One frame consists of 8-bit data plus a parity bit in asynchronous mode. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If an error signal is sampled during transmission, the same data is retransmitted automatically after the elapse of 2 etu or longer. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Legend: : Start bit Ds D0 to D7 : Data bits : Parity bit Dp : Error signal DE Figure 15.22 Normal Smart Card Interface Data Format Data transfer with the types of IC cards (direct convention and inverse convention) are performed as described in the following. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0) Rev. 1.00 Sep. 19, 2008 Page 896 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) As in the above sample start character, with the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode. (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1) With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to the Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception. 15.7.3 Block Transfer Mode Operation in block transfer mode is the same as that in normal Smart Card interface, except for the following points. * In reception, though the parity check is performed, no error signal is output even if an error is detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the parity bit of the next frame. * In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. * In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu after transmission start. * As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transfer is not performed, this flag is always cleared to 0. Rev. 1.00 Sep. 19, 2008 Page 897 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP2 to BCP0. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, 128th, 46th, 64th, 93rd, or 256th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula. M = (0.5 - 1 D - 0.5 ) - (L - 0.5) F - (1 + F) x 100 [%] 2N N Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256, 93, 128, 186, or 512) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. M = (0.5 - 1/2 x 372) x 100% = 49.866% Rev. 1.00 Sep. 19, 2008 Page 898 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 372 clocks 186 clocks 0 Internal basic clock 185 371 0 185 371 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 15.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Bit Rate) Rev. 1.00 Sep. 19, 2008 Page 899 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR, and the BCP2 bit in SCMR. Set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. To switch from receive mode to transmit mode, after checking that the SCI has finished reception, initialize the SCI, and clear RE to 0 and set TE to 1. Whether SCI has finished reception can be checked with the RDRF, PER, or ORER flag. To switch from transmit mode to receive mode, after checking that the SCI has finished transmission, initialize the SCI, and clear TE to 0 and set RE to 1. Whether SCI has finished transmission can be checked with the TEND flag. 15.7.6 Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sampled from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The ERS bit in SSR should be cleared to 0 before the next parity bit is sampled. 2. The TEND bit in SSR is not set for a frame for which an error signal is received. Data is retransferred from TDR to TSR, and retransmitted automatically. 3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. Rev. 1.00 Sep. 19, 2008 Page 900 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 4. Transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is set at this time, a TXI interrupt request is generated. Writing transmit data to TDR transfers the next transmit data. Figure 15.28 shows a flowchart for transmission. The sequence of transmit operations can be performed automatically by specifying the DTC or DMAC to be activated with a TXI interrupt source. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or DMAC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or DMAC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures, refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC). Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [2] FER/ERS [1] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer to TSR from TDR Transfer to TSR from TDR [4] [3] Figure 15.26 Retransfer Operation in SCI Transmit Mode Rev. 1.00 Sep. 19, 2008 Page 901 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag generation timing is shown in figure 15.27. I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu 11.0 etu When GM = 1 Legend: Ds D0 to D7 Dp DE : Start bit : Data bits : Parity bit : Error signal Note: etu (Elementary Time Unit): Time for transfer of 1 bit Figure 15.27 TEND Flag Generation Timing in Transmission Operation Rev. 1.00 Sep. 19, 2008 Page 902 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 15.28 Example of Transmission Processing Flow Rev. 1.00 Sep. 19, 2008 Page 903 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 15.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The PER bit in SSR should be cleared to 0 before the next parity bit is sampled. 2. The RDRF bit in SSR is not set for a frame in which an error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. 4. The receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an RXI interrupt request is generated. Figure 15.30 shows a flowchart for reception. The sequence of receive operations can be performed automatically by specifying the DTC or DMAC to be activated with an RXI interrupt source. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. If an error occurs in receive mode and the ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated, and so the error flag must be cleared to 0. In the event of an error, the DTC or DMAC is not activated and receive data is skipped. Therefore, receive data is transferred for only the specified number of bytes in the event of an error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been received is transferred to RDR and can be read from there. Note: For details on receive operations in block transfer mode, refer to section 15.4, Operation in Asynchronous Mode. Rev. 1.00 Sep. 19, 2008 Page 904 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 [4] [3] Figure 15.29 Retransfer Operation in SCI Receive Mode Start Initialization Start reception ORER = 0 and PER = 0 Yes No Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 15.30 Example of Reception Processing Flow Rev. 1.00 Sep. 19, 2008 Page 905 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 15.31 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. CKE0 SCK Specified pulse width Specified pulse width Figure 15.31 Timing for Fixing Clock Output Level When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty cycle. Powering On: To secure the clock duty cycle from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to Smart Card mode operation. 4. Set the CKE0 bit in SCR to 1 to start clock output. When Changing from Smart Card Interface Mode to Software Standby Mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to halt the clock. Rev. 1.00 Sep. 19, 2008 Page 906 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 4. Wait for one serial clock cycle. During this interval, clock output is fixed at the specified level, with the duty cycle preserved. 5. Make the transition to the software standby state. When Returning to Smart Card Interface Mode from Software Standby Mode: 6. Exit the software standby state. 7. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty cycle. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 15.32 Clock Halt and Restart Procedure Rev. 1.00 Sep. 19, 2008 Page 907 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.8 IrDA Operation When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system. In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600 bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in this LSI does not include a function for varying the transfer rate automatically, the transfer rate setting must be changed by software. Figure 15.33 shows a block diagram of the IrDA function. IrDA SCI0 TxD0/IrTxD Pulse encoder TxD RxD RxD0/IrRxD Pulse decoder IrCR Figure 15.33 Block Diagram of IrDA Rev. 1.00 Sep. 19, 2008 Page 908 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) (1) Transmission In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the IrDA interface (see figure 15.34). When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one bit) is output (initial value). The high-level pulse can be varied according to the setting of bits IrCKS2 to IrCKS0 in IrCR. In the specification, the high pulse width is fixed at a minimum of 1.41 s, and a maximum of (3/16 + 2.5%) x bit rate or (3/16 x bit rate) + 1.08 s. When system clock is 20 MHz, 1.6 s can be set for a high pulse width with a minimum value of 1.41 s. When the serial data is 1, no pulse is output. UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Transmit Receive IR frame Start bit 0 1 0 1 0 Data Stop bit 0 1 1 0 1 Bit cycle Pulse width 1.6 s to 3/16 bit cycle Figure 15.34 IrDA Transmit/Receive Operations Rev. 1.00 Sep. 19, 2008 Page 909 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) (2) Reception In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI. When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 s will be identified as a 0 signal. (3) High Pulse Width Selection Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and operating frequencies of this LSI and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 15.12 Settings of IrCKS2 to IrCKS0 Bits Bit Rate (bps) (Above)/Bit Period x 3/16 (s) (Below) Operating Frequency (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 16.9344 17.2032 18 19.6608 20 25 30 33 2400 78.13 100 100 100 101 101 101 101 101 101 101 101 101 101 110 110 110 9600 19.53 100 100 100 101 101 101 101 101 101 101 101 101 101 110 110 110 19200 9.77 100 100 100 101 101 101 101 101 101 101 101 101 101 110 110 110 38400 4.88 100 100 100 101 101 101 101 101 101 101 101 101 101 110 110 110 57600 3.26 100 100 100 101 101 101 101 101 101 101 101 101 101 110 110 110 115200 1.63 100 100 100 101 101 101 101 101 101 101 101 101 101 Legend: : A bit rate setting cannot be made on the SCI side. Rev. 1.00 Sep. 19, 2008 Page 910 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.9 15.9.1 Interrupt Sources Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC or DMAC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt request can activate the DTC or DMAC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Rev. 1.00 Sep. 19, 2008 Page 911 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.13 SCI Interrupt Sources Channel 0 Name ERI0 RXI0 TXI0 TEI0 1 ERI1 RXI1 TXI1 TEI1 2 ERI2 RXI2 TXI2 TEI2 3 ERI3 RXI3 TXI3 TEI3 4 ERI4 RXI4 TXI4 TEI4 Interrupt Source Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible DMAC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Low Priority High Rev. 1.00 Sep. 19, 2008 Page 912 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.9.2 Interrupts in Smart Card Interface Mode Table 15.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 15.14 Interrupt Sources Channel 0 Name ERI0 RXI0 TXI0 1 ERI1 RXI1 TXI1 2 ERI2 RXI2 TXI2 3 ERI3 RXI3 TXI3 4 ERI4 RXI4 TXI4 Interrupt Source Receive Error, detection Receive Data Full Transmit Data Empty Receive Error, detection Receive Data Full Transmit Data Empty Receive Error, detection Receive Data Full Transmit Data Empty Receive Error, detection Receive Data Full Transmit Data Empty Receive Error, detection Receive Data Full Transmit Data Empty Interrupt Flag ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND DTC Activation Not possible Possible Possible Not possible Possible Possible Not possible Possible Possible Not possible Possible Possible Not possible Possible Possible DMAC Activation Not possible Possible Possible Not possible Possible Possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Low Priority High In Smart Card interface mode, as in normal serial communication interface mode, transfer can be carried out using the DTC or DMAC. In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or DMAC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or DMAC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. Rev. 1.00 Sep. 19, 2008 Page 913 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures, refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC). In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC or DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Rev. 1.00 Sep. 19, 2008 Page 914 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.10 Usage Notes 15.10.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 24, Power-Down Modes. 15.10.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 15.10.3 Mark State and Break Sending When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and clear DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Rev. 1.00 Sep. 19, 2008 Page 915 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.10.5 Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. 15.10.6 Restrictions on Use of DMAC or DTC * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 clock cycles after TDR is updated by the DMAC or DTC. Incorrect operation may occur if the transmit clock is input within 4 clocks after TDR is updated. (Figure 15.35) * When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant SCI receive-data-full interrupt (RXI). SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4 clocks. Figure 15.35 Example of Synchronous Transmission Using DTC Rev. 1.00 Sep. 19, 2008 Page 916 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) 15.10.7 Operation in Case of Mode Transition * Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode or software standby mode depend on the port settings, and become high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read TDR write TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 15.36 shows a sample flowchart for mode transition during transmission. Port pin states during mode transition are shown in figures 15.37 and 15.38. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode or software standby mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission. * Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made during reception, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 15.39 shows a sample flowchart for mode transition during reception. Rev. 1.00 Sep. 19, 2008 Page 917 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 No [1] Data being transmitted is interrupted. After exiting software standby mode, normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. [3] Includes module stop mode. [2] Transition to software standby mode Exit from software standby mode Change operating mode? Yes Initialization [3] No TE = 1 Figure 15.36 Sample Flowchart for Mode Transition during Transmission Rev. 1.00 Sep. 19, 2008 Page 918 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) Start of transmission End of transmission Transition to software standby Exit from software standby TE bit SCK output pin Port input/output TxD output pin Port input/output Port High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Figure 15.37 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission) Transition to software standby Exit from software standby Start of transmission End of transmission TE bit SCK output pin Port input/output TxD output pin Port input/output Port Marking output SCI TxD output Last TxD bit held Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 15.38 Port Pin States during Mode Transition (Internal Clock, Synchronous Transmission) Rev. 1.00 Sep. 19, 2008 Page 919 of 1270 REJ09B0466-0100 Section 15 Serial Communication Interface (SCI, IrDA) RDRF = 1 Yes Read receive data in RDR RE = 0 Transition to software standby mode Exit from software standby mode Change operating mode? Yes Initialization [2] [2] Includes module stop mode. No RE = 1 Figure 15.39 Sample Flowchart for Mode Transition during Reception Rev. 1.00 Sep. 19, 2008 Page 920 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Section 16 I2C Bus Interface 2 (IIC2) This LSI has a four-channel I2C bus interface. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 16.1 shows a block diagram of the I2C bus interface 2. Figure 16.2 shows an example of I/O pin connections to external circuits. 16.1 Features * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit-data-empty (including slave-address match), transmit-end, receive-data-full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, SCL and SDA pins function as NMOS open-drain outputs. Rev. 1.00 Sep. 19, 2008 Page 921 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Transfer clock generation circuit SCL Output control Transmission/ reception control circuit ICCRA ICCRB ICMR Noise canceler ICDRT SAR SDA Output control ICDRS Noise canceler Address comparator ICDRR Bus state decision circuit Arbitration decision circuit ICEIR Interrupt generator ICSR Legend: ICCRA ICCRB ICMR ICSR ICIER ICDRT ICDRR ICDRS SAR : : : : : : : : : I C bus control register A I2C bus control register B I2C mode register I2C status register I2C interrupt permission register I2C transmission data register I2C reception data register I2C bus shift register Slave address register 2 Figure 16.1 Block Diagram of I2C Bus Interface 2 Rev. 1.00 Sep. 19, 2008 Page 922 of 1270 REJ09B0466-0100 Internal data bus Interrupt request Section 16 I C Bus Interface 2 (IIC2) 2 Vcc Vcc SCL in SCL out SCL SCL SDA in SDA out SDA SDA SCL SDA (Master) SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Figure 16.2 External Circuit Connections of I/O Pins 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the I2C bus interface 2. Table 16.1 Pin Configuration Name Serial clock pin Serial data pin Serial clock pin Serial data pin Serial clock pin Serial data pin Serial clock pin Serial data pin Abbreviation SCL0 SDA0 SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 I/O I/O I/O I/O I/O I/O I/O I/O I/O Function IIC2_0 serial clock input/output IIC2_0 serial data input/output IIC2_1 serial clock input/output IIC2_1 serial data input/output IIC2_2 serial clock input/output IIC2_2 serial data input/output IIC2_3 serial clock input/output IIC2_3 serial data input/output Note: The pin symbols are represented as SCL and SDA; channel numbers are omitted in this manual. Rev. 1.00 Sep. 19, 2008 Page 923 of 1270 REJ09B0466-0100 SCL SDA Section 16 I C Bus Interface 2 (IIC2) 2 16.3 Register Descriptions The I2C bus interface has the following registers. Channel 0 * * * * * * * * * I2C bus control register A_0 (ICCRA_0) I2C bus control register B_0 (ICCRB_0) I2C bus mode register_0 (ICMR_0) I2C bus interrupt enable register_0 (ICIER_0) I2C bus status register_0 (ICSR_0) Slave address register_0 (SAR_0) I2C bus transmit data register_0 (ICDRT_0) I2C bus receive data register_0 (ICDRR_0) I2C bus shift register_0 (ICDRS_0) Channel 1 * * * * * * * * * I2C bus control register A_1 (ICCRA_1) I2C bus control register B_1 (ICCRB_1) I2C bus mode register_1 (ICMR_1) I2C bus interrupt enable register_1 (ICIER_1) I2C bus status register_1 (ICSR_1) Slave address register_1 (SAR_1) I2C bus transmit data register_1 (ICDRT_1) I2C bus receive data register_1 (ICDRR_1) I2C bus shift register_1 (ICDRS_1) Rev. 1.00 Sep. 19, 2008 Page 924 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Channel 2 * * * * * * * * * I2C bus control register A_2 (ICCRA_2) I2C bus control register B_2 (ICCRB_2) I2C bus mode register_2 (ICMR_2) I2C bus interrupt enable register_2 (ICIER_2) I2C bus status register_2 (ICSR_2) Slave address register_2 (SAR_2) I2C bus transmit data register_2 (ICDRT_2) I2C bus receive data register_2 (ICDRR_2) I2C bus shift register_2 (ICDRS_2) Channel 3 * * * * * * * * * I2C bus control register A_3 (ICCRA_3) I2C bus control register B_3 (ICCRB_3) I2C bus mode register_3 (ICMR_3) I2C bus interrupt enable register_3 (ICIER_3) I2C bus status register_3 (ICSR_3) Slave address register_3 (SAR_3) I2C bus transmit data register_3 (ICDRT_3) I2C bus receive data register_3 (ICDRR_3) I2C bus shift register_3 (ICDRS_3) Rev. 1.00 Sep. 19, 2008 Page 925 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.3.1 I2C Bus Control Register A (ICCRA) ICCRA is an 8-bit readable/writable register that enables or disables the I2C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I2C Bus Interface Enable 0: This module is halted. 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select When arbitration is lost in master mode, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. In addition, TRS is set to 1 automatically in slave receive mode if the seventh bit of the start condition matches the slave address set in SAR and the eighth bit is set to 1. Operating modes are described below according to MST and TRS combination. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode 3 2 1 0 CKS3 CKS2 CKS1 CKS0 0 0 0 0 R/W R/W R/W R/W Transfer Clock Select 3 to 0 In the master mode, these bits should be set according to the necessary transfer rate (see table 16.2). In the slave mode, they are used to secure the data setup time in transmit mode. The data setup time is 10 tcyc if CKS3 is cleared to 0 and 20 tcyc if CKS3 is set to 1. Rev. 1.00 Sep. 19, 2008 Page 926 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Table 16.2 Transfer Rate Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock /28 /40 /48 /64 /168 /100 /112 /128 /56 /80 /96 /128 /336 /200 /224 /256 = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 47.6 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 23.8 kHz 40.0 kHz 35.7 kHz 31.3 kHz = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 59.5 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 29.8 kHz 50.0 kHz 44.6 kHz 39.1 kHz Transfer Rate = 20 MHz 714 kHz* 500 kHz* 417 kHz* 313 kHz 119 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 59.5 kHz 100 kHz 89.3 kHz 78.1 kHz = 25 MHz 893 kHz* 625 kHz* 521 kHz* 391 kHz 149 kHz 250 kHz 223 kHz 195 kHz 446 kHz* 313 kHz 260 kHz 195 kHz 74.4 kHz 125 kHz 112 kHz 97.7 kHz = 33 MHz 1179 kHz* 825 kHz* 688 kHz* 516 kHz* 196 kHz 330 kHz 295 kHz 258 kHz 589 kHz* 413 kHz* 344 kHz 258 kHz 98.2 kHz 165 kHz 147 kHz 129 kHz Note: * Correct operation cannot be guaranteed since the transfer rate is beyond the I2C bus interface specification (normal mode: maximum 100 kHz, high-speed mode: maximum 400 kHz). Rev. 1.00 Sep. 19, 2008 Page 927 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.3.2 I2C Bus Control Register B (ICCRB) ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in I2C control. Bit 7 Bit Name BBSY Initial Value 0 R/W R/W Description Bus Busy This bit enables to confirm whether the I C bus is occupied or released and to issue start and stop conditions in master mode. This bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also retransmitting a start condition. Write 0 to BBSY and 0 to SCP to issue a stop condition. To issue a start/stop condition, use the MOV instruction. 6 SCP 1 R/W Start Condition/Stop Condition Prohibit The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R This bit monitors SDA output level. When reading and SDA0 is 1, the SDA pin outputs high. When reading and SDA0 is 0, the SDA pin outputs low. The write value should always be 1. 4 3 SCLO 1 1 R/W R Reserved The write value should always be 1. This bit monitors SCL output level. When reading and SCLO is 1, the SCL pin outputs high. When reading and SCLO is 0, the SCL pin outputs low. Reserved This bit is always read as 1. 2 2 1 Rev. 1.00 Sep. 19, 2008 Page 928 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Bit 1 Bit Name IICRST Initial Value 0 R/W R/W Description IIC Control Part Reset This bit resets control parts except for I C registers. If this bit is set to 1 when hang-up is occurred because of communication failure during 2 2 I C operation, I C control part can be reset without setting ports and initializing registers. 2 0 1 Reserved This bit is always read as 1. 16.3.3 I2C Bus Mode Register (ICMR) ICMR controls the master mode wait and selects the number of transfer bits. Bit 7 6 Bit Name WAIT Initial Value 0 0 R/W R/W Description Reserved The write value should always be 0. Wait Insertion This bit selects whether to insert a wait after data transfer except for the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The setting of this bit is invalid in slave mode. 5, 4 3 BCWP All 1 1 R/W Reserved These bits are always read as 1. BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid. Rev. 1.00 Sep. 19, 2008 Page 929 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Bit 2 1 0 Bit Name BC2 BC1 BC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. The data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The value returns to 000 at the end of a data transfer, including the acknowledge bit. 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits Rev. 1.00 Sep. 19, 2008 Page 930 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive data full interrupt request (RXI) when a received data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) is disabled. 1: Receive data full interrupt request (RXI) is enabled. Rev. 1.00 Sep. 19, 2008 Page 931 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Bit 4 Bit Name NAKIE Initial Value 0 R/W R/W Description NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, AL, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled. 3 STIE 0 R/W Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled. 2 ACKE 0 R/W Acknowledge Bit Judgement Select 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. 1: If the acknowledge bit is 1, continuous transfer is interrupted. 1 ACKBR 0 R Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1 0 ACKBT 0 R/W Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. Rev. 1.00 Sep. 19, 2008 Page 932 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.3.5 I2C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags and status. Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Data Register Empty [Setting condition] * * * * * * * 6 TEND 0 R/W When data is transferred from ICDRT to ICDRS and ICDRT becomes empty. When TRS has been set. When a start condition (including retransmission) has been issued. When a transition from the receive mode to the transmit mode has been made in the slave mode. [Clearing conditions] When 0 is written in TDRE after reading TDRE = 1. When data is written in ICDRT. Transmit End [Setting condition] * When the ninth clock of SCL is rose while the TDRE flag is 1. When 0 is written in TEND after reading TEND = 1. When data is written in ICDRT. [Clearing conditions] * * 5 RDRF 0 R/W Receive Data Register Full [Setting condition] * When a received data is transferred from ICDRS to ICDRR. When 0 is written in RDRF after reading RDRF = 1. When data is read from ICDRR. [Clearing conditions] * * Rev. 1.00 Sep. 19, 2008 Page 933 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Bit 4 Bit Name NACKF Initial Value 0 R/W R/W Description No Acknowledge Detection Flag [Setting condition] * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1. When 0 is written in NACKF after reading NACKF = 1. [Clearing condition] * 3 STOP 0 R/W Stop Condition Detection Flag [Setting condition] * * In master mode, when a stop condition is detected after frame transfer. In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR. When 0 is written in STOP after reading STOP = 1. [Clearing condition] * 2 AL 0 R/W Arbitration Lost Flag This flag indicates that arbitration was lost in master mode. When two or more master devices attempt to seize the bus at nearly the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode. When the SDA pin outputs high in master mode while a start condition is detected. When 0 is written in AL after reading AL =1. [Clearing condition] * Rev. 1.00 Sep. 19, 2008 Page 934 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Bit 1 Bit Name AAS Initial Value 0 R/W R/W Description Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting condition] * * When the slave address is detected in slave receive mode. When the general call address is detected in slave receive mode. When 0 is written in AAS after reading AAS=1 [Clearing condition] * 0 ADZ 0 R/W General Call Address Recognition Flag This bit is valid in slave receive mode. [Setting condition] * When the general call address is detected in slave receive mode. When 0 is written in ADZ after reading ADZ=1. [Clearing conditions] * 16.3.6 Slave Address Register (SAR) SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device. Bit 7 to 1 Bit Name SVA6 to SVA0 Initial Value All 0 R/W R/W Description Slave Address 6 to 0 These bits set a unique address in bits SVA6 to SVA0, differing from the addresses of other slave 2 devices connected to the I C bus. 0 R/W Reserved This bit is readable/writable. The write value should always be 0. 0 Rev. 1.00 Sep. 19, 2008 Page 935 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the I2C bus shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. The initial value of ICDRT is H'FF. 16.3.8 I2C Bus Receive Data Register (ICDRR) ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the received data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot be written to this register. The initial value of ICDRR is H'FF. 16.3.9 I2C Bus Shift Register (ICDRS) ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read from the CPU. Rev. 1.00 Sep. 19, 2008 Page 936 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.4 16.4.1 Operation I2C Bus Format Figure 16.3 shows the I2C bus formats. Figure 16.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits. (a) I2C bus format S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) (b) I2C bus format (start condition retransmission) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 1 n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) Figure 16.3 I2C Bus Formats SDA SCL S 1-7 SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A P Figure 16.4 I2C Bus Timing Rev. 1.00 Sep. 19, 2008 Page 937 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Legend: S: SLA: R/W: A: Start condition. The master device drives SDA from high to low while SCL is high. Slave address Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Acknowledge. The receiving device drives SDA to low. DATA: Transferred data P: 16.4.2 Stop condition. The master device drives SDA from low to high while SCL is high. Master Transmit Operation In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV instruction. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. After this, when TDRE is cleared to 0, data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT, and clear TDRE and TEND. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set, thus clearing TDRE. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode. Rev. 1.00 Sep. 19, 2008 Page 938 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 SCL (master output) SDA (master output) 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W 9 1 Bit 7 2 Bit 6 Slave address SDA (slave output) TDRE A TEND ICDRT Address + R/W Data 1 Data 2 ICDRS Address + R/W Data 1 User [2] Instruction of start processing condition issuance [4] Write data to ICDRT (second byte). [3] Write data to ICDRT (first byte). [5] Write data to ICDRT (third byte). Figure 16.5 Master Transmit Mode Operation Timing 1 SCL (master output) SDA (master output) SDA (slave output) TDRE A 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 A/A TEND ICDRT Data n ICDRS Data n User [5] Write data to ICDRT. processing [6] Issue stop condition. Clear TEND. [7] Set slave receive mode Figure 16.6 Master Transmit Mode Operation Timing 2 Rev. 1.00 Sep. 19, 2008 Page 939 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise of 9th receive clock pulse. At this time, the received data is read by reading ICDRR. 4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, read ICDRR. Then, clear RCVD. 7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RDRF to 0. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode. Rev. 1.00 Sep. 19, 2008 Page 940 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Master transmit mode SCL (master output) SDA (master output) SDA (slave output) Master receive mode 9 1 2 3 4 5 6 7 8 9 A 1 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 16.7 Master Receive Mode Operation Timing 1 Rev. 1.00 Sep. 19, 2008 Page 941 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 SCL (master output) SDA (master output) SDA (slave output) 9 A 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n-1 Data n ICDRR User processing Data n-1 Data n [5] Read ICDRR after setting RCVD. [6] Issue stop condition [7] Read ICDRR and clear RCVD [8] Set slave receive mode Figure 16.8 Master Receive Mode Operation Timing 2 16.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS in ICCRA and TDRE in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by clearing TDRE after writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free. 5. Clear TDRE. Rev. 1.00 Sep. 19, 2008 Page 942 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Slave receive mode SCL (master output) SDA (master output) SCL (slave output) SDA (slave output) Slave transmit mode 9 1 2 3 4 5 6 7 8 9 A 1 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT Data 1 Data 2 Data 3 ICDRS Data 1 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1). [2] Write data to ICDRT (data 2). [2] Write data to ICDRT (data 3). Figure 16.9 Slave Transmit Mode Operation Timing 1 Rev. 1.00 Sep. 19, 2008 Page 943 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Slave receive mode Slave transmit mode SCL (master output) SDA (master output) SCL (slave output) SDA (slave output) TDRE 9 A 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 16.10 Slave Transmit Mode Operation Timing 2 Rev. 1.00 Sep. 19, 2008 Page 944 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read) and RDRF is cleared. (Since the read data show the slave address and R/W, it is not used.) 3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR. Rev. 1.00 Sep. 19, 2008 Page 945 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 SCL (master output) SDA (master output) SCL (slave output) SDA (slave output) 9 1 2 3 4 5 6 7 8 9 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [2] Read ICDRR (dummy read). [2] Read ICDRR. Figure 16.11 Slave Receive Mode Operation Timing 1 SCL (master output) SDA (master output) SCL (slave output) SDA (slave output) 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [3] Set ACKBT [3] Read ICDRR. [4] Read ICDRR. Figure 16.12 Slave Receive Mode Operation Timing 2 Rev. 1.00 Sep. 19, 2008 Page 946 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.4.6 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch March detector Internal SCL or SDA signal System clock period Sampling clock Figure 16.13 Block Diagram of Noise Canceler 16.4.7 Example of Use Flowcharts in respective modes that use the I2C bus interface are shown in figures 16.14 to 16.17. Rev. 1.00 Sep. 19, 2008 Page 947 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Start Initialize Read BBSY in ICCRB [1] Test the status of the SCL and SDA lines. Select master transmit mode. Start condition issuance. Select transmit data for the first byte (slave address + R/W). No [1] BBSY=0 ? Yes Set MST = 1 and TRS = 1 in ICCRA. Write BBSY = 1 and SCP = 0. Write transmit data in ICDRT [2] [3] [4] [2] [3] [5] Wait for 1 byte to be transmitted. Test the acknowledge bit, transferred from the specified slave device. Set transmit data for the second and subsequent data (except for the final byte). [4] [6] [7] Read TEND in ICSR No [5] TEND=1 ? Yes Read ACKBR in ICIER [6] ACKBR=0 ? Yes Transmit mode? Yes No [8] [9] Wait for ICDRT empty. Set the final byte of transmit data. No [10] Wait for the completion of transmission for the final byte. [11] Clear TEND flag. Master receive mode [12] Clear STOP flag. Write transmit data in ICDRT Read TDRE in ICSR No [7] [13] Stop condition issuance. [8] TDRE=1 ? Yes [14] Wait for the generation of the stop condition. [15] Set slave receive mode. Clear TDRE. No Final byte? [9] Yes Write transmit data in ICDRT Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ICSR [11] [12] Write BBSY = 0 and SCP = 0 Read STOP in ICSR No [13] [14] STOP=1 ? Yes Set MST = 0 and TRS = 0 in ICCRA [15] Clear TDRE in ICSR End Figure 16.14 Sample Flowchart for Master Transmit Mode Rev. 1.00 Sep. 19, 2008 Page 948 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Mater receive mode [1] Clear TEND in ICSR Set TRS = 0 (ICCRA) Clear TDRE of ICSR Set ACKBT = 0 (ICIER) Dummy read ICDRR Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes [5] [4] [2] Clear TEND, select master receive mode, and then clear TDRE.* Set acknowledge to the transmitting device.* Dummy read ICDDR.* Wait for 1 byte to be received. Check if the (last receive - 1). Read the receive data. Set acknowledge of the final byte. Disable continuous receive (RCVD = 1). Read receive data of (final byte - 1). Wait for the final byte to be received. [2] [1] [3] [4] [5] [6] [7] [8] [9] [3] [10] Clear STOP flag. [6] [11] Stop condition issuance. [12] Wait for the generation of stop condition. Set ACKBT = 1 (ICIER) [7] [13] Read the receive data of the final byte. [14] Clear RCVD to 0. Set RCVD = 1 (ICCRA) Read ICDRR Read RDRF in ICSR No RDRF=1 ? Yes Clear STOP in ICSR Write BBSY = 0 and SCP = 0 Read STOP of ICSR No [12] [9] [8] [15] Set slave receive mode. [10] [11] STOP=1 ? Yes Read ICDRR [13] [14] Set RCVD = 0 (ICCRA) Set MST = 0 (ICCRA) End [15] Note: * Ensure that no interrupts are received while steps [1] through [3] are being processed. Additional information: If only one byte is received, steps [2] through [6] are omitted following step [1], and processing jumps to step [7]. Step [8] is ICDDR dummy read. Figure 16.15 Sample Flowchart for Master Receive Mode Rev. 1.00 Sep. 19, 2008 Page 949 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No [3] TDRE=1 ? Yes No End of transmission? [1] Clear the flag AAS. [1] [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. [2] [4] Set the last byte of the transmit data. [5] Wait the transmission end of the last byte. [6] Clear the flag TEND. [7] Set slave receive mode. [8] Dummy read ICDRR to release the SCL line. [4] [9] Clear the flag TDRE. Yes Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Clear TEND in ICSR Set TRS=0 in ICCRA Dummy read ICDRR Clear TDRE in ICSR End [6] [7] [8] [9] Figure 16.16 Sample Flowchart for Slave Transmit Mode Rev. 1.00 Sep. 19, 2008 Page 950 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 Slave receive mode [1] Clear the flag AAS. Clear AAS in ICSR Set ACKBT=0 in ICIER Dummy read ICDRR [1] [2] Set the acknowledge for the transmit device. [2] [3] Dummy read ICDRR. [3] [4] Wait the reception end of 1 byte. [5] Check if the (last receive - 1). [4] [6] Read the received data. [7] Set the acknowledge for the last byte. Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes [5] [8] Read the received data of the (last byte - 1). [9] Wait the reception end of the last byte. [6] [10] Read the received data of the last byte. Set ACKBT=1 in ICIER [7] Read ICDRR Read RDRF in ICSR [8] No [9] RDRF=1 ? Yes Read ICDRR End [10] Additional information: If only one byte is received, steps [2] through [6] are omitted following step [1], and processing jumps to step [7]. Step [8] is ICDRR dummy read. Figure 16.17 Sample Flowchart for Slave Receive Mode Rev. 1.00 Sep. 19, 2008 Page 951 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost. Table 16.3 shows the contents of each interrupt request. Table 16.3 Interrupt Requests Interrupt Request Transmit Data Empty Transmit End Receive Data Full STOP Recognition NACK Detection Arbitration Lost Abbreviation TXI TEI RXI STPI NAKI Interrupt Condition (TDRE=1) * (TIE=1) (TEND=1) * (TEIE=1) (RDRF=1) * (RIE=1) (STOP=1) * (STIE=1) {(NACKF=1)+(AL=1)} * (NAKIE=1) Interrupt exception handling is performed when the interrupt conditions listed in table 16.3 are set to 1 and the CPU is ready to accept interrupts. During exception handling, the interrupt sources should be cleared. Note, however, that TDRE and TEND are automatically cleared by writing transmit data to ICDRT, and RDRF is automatically cleared by reading data from ICDRR. In particular, if TDRE is set at the same time transmit data is written to ICDRT, and then TDRE is cleared again, an extra byte of data may be transmitted. Rev. 1.00 Sep. 19, 2008 Page 952 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.6 Bit Synchronous Circuit In master mode, * When SCL is driven to low by the slave device * When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up resistance) This module has a possibility that high level period may be short in the two states described above. Therefore it monitors SCL and communicates by bit with synchronization. Figure 16.18 shows the timing of the bit synchronous circuit and table 16.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored. SCL monitor timing reference clock SCL VIH Internal SCL Figure 16.18 Timing of the Bit Synchronous Circuit Table 16.4 Time for monitoring SCL CKS3 0 CKS2 0 1 1 0 1 Time for monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc Rev. 1.00 Sep. 19, 2008 Page 953 of 1270 REJ09B0466-0100 Section 16 I C Bus Interface 2 (IIC2) 2 16.7 Usage Notes 1. Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check SCLO in the I2C control register B (IICRB) to confirm the fall of the ninth clock. When the start/stop conditions are issued (retransmitted) at the specific timing under the following condition (i) or (ii), such conditions may not be output successfully. This does not occur in other cases. (i) When the rising of SCL falls behind the time specified in section 16.6, Bit Synchronous Circuit, by the load of the SCL bus (load capacitance or pull-up resistance) (ii) When the bit synchronous circuit is activated by extending the low period of eighth and ninth clocks, that is driven by the slave device 2. Control WAIT in the I2C bus mode register (ICMR) to be set to 0. When WAIT is set to 1, and SCL is driven low for two or more transfer clocks by the slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. This does not occur in other cases. Rev. 1.00 Sep. 19, 2008 Page 954 of 1270 REJ09B0466-0100 Section 17 A/D Converter Section 17 A/D Converter This LSI includes two units (units 0 and 1) of successive approximation type 10-bit A/D converter. In the H8S/2426 group and H8S/2426R group, the A/D converter units 0 and 1 allow up to eight analog input channels to be selected. In the H8S/2424 group, unit 0 allows up to eight analog input channels to be selected while unit 1 allows up to two channels. Figures 17.1 and 17.2 show block diagrams of the A/D converter units 0 and 1, respectively. 17.1 Features * 10-bit resolution * Input channels: H8S/2426 group and H8S/2426R group: Eight channels (total of 16 channels for the two units) H8S/2424 group: Eight channels for unit 0 and two channels for unit 1 (total of 10 channels for the two units) * Conversion cycle: 64 cycles or 40 cycles (A/D conversion clock) * Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels*1 * Separate A/D conversion clock specifiable for each unit (P, P/2, P/4, or P/8) * Eight data registers for A/D converter unit 0 and eight data registers for unit 1*2 (total of 16 data registers for the two units) Results of A/D conversion are held in a 16-bit data register for each channel. * Sample and hold functionality * Three types of conversion start Conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit (TPU) or 8-bit timer (TMR), or an external trigger signal. * Interrupt source A/D conversion end interrupt (ADI) request can be generated. * Module stop state specifiable Notes: 1. Continuous A/D conversion on 1 to 2 channels in the H8S/2424 group. 2. Two data registers for unit 1 (total of ten data registers for the two units) in the H8S/2424 group. Rev. 1.00 Sep. 19, 2008 Page 955 of 1270 REJ09B0466-0100 Section 17 A/D Converter Module data bus Bus interface ADDRG_0 ADDRC_0 ADDRD_0 ADDRH_0 ADDRA_0 ADDRB_0 ADDRE_0 ADCSR_0 ADDRF_0 Internal data bus AVCC 10-bit A/D Successive approximation register Vref AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Multiplexer + - Comparator Sample-andhold circuit Control circuit ADCR_0 ADTRG0-A ADTRG0-B [Legend] ADCR_0: ADCSR_0: ADDRA_0: ADDRB_0: ADDRC_0: ADI0 interrupt signal Conversion start trigger from TPU (units 0, 1) or TMR A/D control register_0 A/D control/status register_0 A/D data register A_0 A/D data register B_0 A/D data register C_0 ADDRD_0: ADDRE_0: ADDRF_0: ADDRG_0: ADDRH_0: A/D data register D_0 A/D data register E_0 A/D data register F_0 A/D data register G_0 A/D data register H_0 Figure 17.1 Block Diagram of A/D Converter Unit 0 (AD_0) Rev. 1.00 Sep. 19, 2008 Page 956 of 1270 REJ09B0466-0100 Section 17 A/D Converter Module data bus Bus interface ADDRG_1 ADDRC_1 ADDRD_1 ADDRH_1 ADDRA_1 ADDRB_1 ADDRE_1 ADCSR_1 ADDRF_1 Internal data bus AVCC 10-bit A/D Successive approximation register Vref AVSS AN8* AN9* Multiplexer + - Comparator Sample-andhold circuit Control circuit AN10* AN11* AN12 AN13 AN14* AN15* ADCR_1 ADTRG1-A ADI1 interrupt signal Conversion start trigger from TPU (units 0, 1) A/D control register_1 A/D control/status register_1 A/D data register A_1 A/D data register B_1 A/D data register C_1 ADDRD_0: ADDRE_0: ADDRF_0: ADDRG_0: ADDRH_0: A/D data register D_1 A/D data register E_1 A/D data register F_1 A/D data register G_1 A/D data register H_1 [Legend] ADCR_1: ADCSR_1: ADDRA_1: ADDRB_1: ADDRC_1: Note: * The H8S/2424 group does not have these pins. Figure 17.2 Block Diagram of A/D Converter Unit 1 (AD_1) Rev. 1.00 Sep. 19, 2008 Page 957 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.2 Input/Output Pins Tables 17.1 and 17.2 show the pin configuration of the A/D converter. Table 17.1 Pin Configuration (H8S/2426 Group and H8S/2426R Group) Unit 0 Symbol Pin Name AD_0 Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin 0_A A/D external trigger input pin 0_B 1 AD_1 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 A/D external trigger input pin 1 Common Analog power supply pin Analog ground pin Reference voltage pin Symbol AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG0-A ADTRG0-B AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ADTRG1 AVCC AVSS Vref I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input pin A for starting A/D conversion Analog block power supply Analog block ground A/D conversion reference voltage External trigger input pin 0_A for starting A/D conversion* External trigger input pin 0_B for starting A/D conversion* Analog inputs Function Analog inputs Note: * Selectable by setting of the TRGS1, TRGS0, and EXTRGS bits in ADCR. Rev. 1.00 Sep. 19, 2008 Page 958 of 1270 REJ09B0466-0100 Section 17 A/D Converter Table 17.2 Pin Configuration (H8S/2424 Group) Unit 0 Abbr. AD_0 Pin Name Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin 0_A A/D external trigger input pin 0_B 1 AD_1 Analog input pin 12 Analog input pin 13 A/D external trigger input pin 1 Common Analog power supply pin Analog ground pin Reference voltage pin Note: * Symbol AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG0-A I/O Input Input Input Input Input Input Input Input Input External trigger input pin 0_A for starting A/D conversion* External trigger input pin 0_B for starting A/D conversion* Analog inputs Function Analog inputs ADTRG0-B Input AN12 AN13 ADTRG1 AVCC AVSS Vref Input Input Input Input Input Input External trigger input pin A for starting A/D conversion Analog block power supply Analog block ground A/D conversion reference voltage Selectable by setting of the TRGS1, TRGS0, and EXTRGS bits in ADCR. Rev. 1.00 Sep. 19, 2008 Page 959 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.3 Register Descriptions The A/D converter has the following registers. Unit 0 (A/D_0) registers: * * * * * * * * * * A/D data register A_0 (ADDRA_0) A/D data register B_0 (ADDRB_0) A/D data register C_0 (ADDRC_0) A/D data register D_0 (ADDRD_0) A/D data register E_0 (ADDRE_0) A/D data register F_0 (ADDRF_0) A/D data register G_0 (ADDRG_0) A/D data register H_0 (ADDRH_0) A/D control/status register_0 (ADCSR_0) A/D control register_0 (ADCR_0) Unit 1 (A/D_1) registers: * * * * * * * * * * A/D data register A_1 (ADDRA_1) A/D data register B_1 (ADDRB_1) A/D data register C_1 (ADDRC_1) A/D data register D_1 (ADDRD_1) A/D data register E_1 (ADDRE_1) A/D data register F_1 (ADDRF_1) A/D data register G_1 (ADDRG_1) A/D data register H_1 (ADDRH_1) A/D control/status register_1 (ADCSR_1) A/D control register_1 (ADCR_1) Rev. 1.00 Sep. 19, 2008 Page 960 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in tables 17.3 and 17.4. The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units. Table 17.3 Analog Input Channels and Corresponding ADDR Registers (H8S/2426 Group and H8S/2426R Group) Analog Input Channel Channel Set 0 (CH3 = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog Input Channel Data Register Storing Channel Set 0 Data Register Storing Conversion Result Conversion Result (CH3 = 0) ADDRA_0 AN8 ADDRA_1 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 Rev. 1.00 Sep. 19, 2008 Page 961 of 1270 REJ09B0466-0100 Section 17 A/D Converter Table 17.4 Analog Input Channels and Corresponding ADDR Registers (H8S/2424 Group) Analog Input Channel Channel Set 0 (CH3 = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 Analog Input Channel Data Register Storing Channel Set 0 Conversion Result (CH3 = 0) ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 AN12 AN13 Data Register Storing Conversion Result ADDRE_1 ADDRF_1 Rev. 1.00 Sep. 19, 2008 Page 962 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.3.2 A/D Control/Status Register for Unit 0 (ADCSR_0) ADCSR_0 controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value 0 R/W Description 6 5 ADIE ADST 0 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * Completion of A/D conversion in single mode * Completion of A/D conversion on all specified channels in scan mode [Clearing conditions] * Writing of 0 after reading ADF = 1 * Reading from ADDR after activation of the DMAC or DTC by an ADI interrupt R/W A/D Interrupt Enable Setting this bit to 1 enables ADI interrupts by ADF. R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when A/D conversion on the specified channel ends. In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. While the ADSTCLR bit in ADCR is set to 1, the ADST bit is cleared to 0 automatically when A/D conversion on all selected channels ends, and then A/D conversion stops. The timing to clear the ADST bit automatically differs from that of ADF setting; the ADST bit is cleared before the ADF bit is set. R/W Clock Extension Select Specifies the A/D conversion time in combination with the CKS1 and CKS0 bits in ADCR. Be sure to set these three bits at one time. For details, see the description of the ADCR resisters. 4 EXCKS 0 Rev. 1.00 Sep. 19, 2008 Page 963 of 1270 REJ09B0466-0100 Section 17 A/D Converter Bit 3 2 1 0 Bit Name CH3 CH2 CH1 CH0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. * When SCANE = 0 and SCANS = x 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1xxx: Setting prohibited * When SCANE = 1 and SCANS = 0 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 0111: AN4 to AN7 1xxx: Setting prohibited * When SCANE = 1 and SCANS = 1 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 1xxx: Setting prohibited [Legend] x: Don't care Note: * Only 0 can be written to this bit, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 964 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.3.3 A/D Control/Status Register for Unit 1 (ADCSR_1) ADCSR_1 controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value 0 R/W Description 6 5 ADIE ADST 0 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * Completion of A/D conversion in single mode * Completion of A/D conversion on all specified channels in scan mode [Clearing conditions] * Writing of 0 after reading ADF = 1 * Reading from ADDR after activation of the DTC by an ADI interrupt R/W A/D Interrupt Enable Setting this bit to 1 enables ADI interrupts by ADF. R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when A/D conversion on the specified channel ends. In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. While the ADSTCLR bit in ADCR is set to 1, the ADST bit is cleared to 0 automatically when A/D conversion on all selected channels ends, and then A/D conversion stops. The timing to clear the ADST bit automatically differs from that of ADF setting; the ADST bit is cleared before the ADF bit is set. R/W Clock Extension Select Specifies the A/D conversion time in combination with the CKS1 and CKS0 bits in ADCR. Be sure to set these three bits at one time. For details, see the description of the ADCR resisters. 4 EXCKS 0 Rev. 1.00 Sep. 19, 2008 Page 965 of 1270 REJ09B0466-0100 Section 17 A/D Converter * H8S/2426 Group and H8S/2426R Group Bit 3 2 1 0 Bit Name CH3 CH2 CH1 CH0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. * When SCANE = 0 and SCANS = x 0XXX: Setting prohibited 1000: AN8 1001: AN9 1010: AN10 1011: AN11 1100: AN12 1101: AN13 1110: AN14 1111: AN15 * When SCANE = 1 and SCANS = 0 0XXX: Setting prohibited 1000: AN8 1001: AN8 and AN9 1010: AN8 to AN10 1011: AN8 to AN11 1100: AN12 1101: AN12 and AN13 1110: AN12 to AN14 1111: AN12 to AN15 * When SCANE = 1 and SCANS = 1 0XXX: Setting prohibited 1000: AN8 1001: AN8 and AN9 1010: AN8 to AN10 1011: AN8 to AN11 1100: AN8 to AN12 1101: AN8 to AN13 1110: AN8 to AN14 1111: AN8 to AN15 [Legend] x: Don't care Note: * Only 0 can be written to this bit, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 966 of 1270 REJ09B0466-0100 Section 17 A/D Converter * H8S/2424 Group Bit 3 2 1 0 Bit Name CH3 CH2 CH1 CH0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. * When SCANE = 0 and SCANS = x 0XXX: Setting prohibited 10XX: Setting prohibited 1100: AN12 1101: AN13 111X: Setting prohibited * When SCANE = 1 and SCANS = 0 0XXX: Setting prohibited 10XX: Setting prohibited 1100: AN12 1101: AN12 and AN13 111X: Setting prohibited * Setting SCANE = 1 and SCANS = 1 are prohibited. [Legend] x: Don't care Note: * Only 0 can be written to this bit, to clear the flag. Rev. 1.00 Sep. 19, 2008 Page 967 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.3.4 A/D Control Register (ADCR_0) Unit 0 ADCR enables A/D conversion to be started by an external trigger input. Bit 7 6 0 Bit Name TRGS1 TRGS0 EXTRGS Initial Value 0 0 0 R/W R/W R/W R/W Description Timer Trigger Select 1 and 0 and Extended Trigger Select These bits enable or disable the start of A/D conversion by a trigger signal. 000: Disables A/D conversion start by external trigger 010: Enables A/D conversion start by external trigger from TPU (unit 0) 100: Enables A/D conversion start by external trigger from TMR 110: Enables A/D conversion start by the ADTRG0-A pin 001: Enables A/D conversion start by the ADTRG0-B pin 011: Enables simultaneous A/D conversion start in multiple units by external trigger from TPU (units 0 and 1) 101: Enables simultaneous A/D conversion start in multiple units by external trigger from TMR 111: Enables simultaneous A/D conversion start in multiple units by the ADTRG0-B pin Rev. 1.00 Sep. 19, 2008 Page 968 of 1270 REJ09B0466-0100 Section 17 A/D Converter Bit 5 4 Bit Name SCANE SCANS Initial Value 0 0 R/W R/W R/W Description Scan Mode These bits select the A/D conversion operating mode. 0x: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4. 11: Scan mode. A/D conversion is performed continuously for channels 1 to 8. 3 2 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the A/D conversion clock (ADCLK) and specify the A/D conversion time in combination with the EXCKS bit. First select the A/D conversion time while ADST = 0 in ADCSR and then set the mode of A/D conversion. Before entering software standby mode or module stop mode, set these bits to B'11. Set CKS1 and CKS0 bits appropriately so that the ADCLK frequency is 10 MHz or less. EXCKS, CKS1, and CKS0 000: Setting prohibited 001: A/D conversion time = 268 states (max.) at ADCLK = /4 010: A/D conversion time = 138 states (max.) at ADCLK = /2 011: A/D conversion time = 73 states (max.) at ADCLK = 100: Setting prohibited 101: A/D conversion time = 172 states (max.) at ADCLK = /4 110: A/D conversion time = 90 states (max.) at ADCLK = /2 111: A/D conversion time = 49 states (max.) at ADCLK = 1 ADSTCLR 0 R/W A/D Start Clear This bit enables or disables automatic clearing of the ADST bit in scan mode. 0: The ADST bit is not automatically cleared to 0 in scan mode. 1: The ADST bit is cleared to 0 upon completion of the A/D conversion for all of the selected channels in scan mode. [Legend] x: Don't care Rev. 1.00 Sep. 19, 2008 Page 969 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.3.5 A/D Control Register (ADCR_1) Unit 1 ADCR enables A/D conversion to be started by an external trigger input. Bit 7 6 0 Bit Name TRGS1 TRGS0 EXTRGS Initial Value 0 0 0 R/W R/W R/W R/W Description Timer Trigger Select 1 and 0 and Extended Trigger Select These bits enable or disable the start of A/D conversion by a trigger signal. 000: Disables A/D conversion start by external trigger 010: Enables A/D conversion start by external trigger from TPU (units 0 and 1) 100: Enables A/D conversion start by external trigger from TMR 110: Enables A/D conversion start by the ADTRG1 pin 001: Setting prohibited 011: Enables simultaneous A/D conversion start in multiple units by external trigger from TPU (units 0 and 1) 101: Enables simultaneous A/D conversion start in multiple units by external trigger from TMR 111: Enables simultaneous A/D conversion start in multiple units by the ADTRG0-B pin 5 4 SCANE SCANS 0 0 R/W R/W Scan Mode These bits select the A/D conversion operating mode. 0x: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4. 11: Scan mode. A/D conversion is performed continuously for channels 1 to 8.* Rev. 1.00 Sep. 19, 2008 Page 970 of 1270 REJ09B0466-0100 Section 17 A/D Converter Bit 3 2 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 1 and 0 These bits select the A/D conversion clock (ADCLK) and specify the A/D conversion time in combination with the EXCKS bit. First select the A/D conversion time while ADST = 0 in ADCSR and then set the mode of A/D conversion. Before entering software standby mode or module stop mode, set these bits to B'11. Set CKS1 and CKS0 bits appropriately so that the ADCLK frequency is 10 MHz or less. EXCKS, CKS1, and CKS0 000: Setting prohibited 001: A/D conversion time = 268 states (max.) at ADCLK = /4 010: A/D conversion time = 138 states (max.) at ADCLK = /2 011: A/D conversion time = 73 states (max.) at ADCLK = 100: Setting prohibited 101: A/D conversion time = 172 states (max.) at ADCLK = /4 110: A/D conversion time = 90 states (max.) at ADCLK = /2 111: A/D conversion time = 49 states (max.) at ADCLK = 1 ADSTCLR 0 R/W A/D Start Clear This bit enables or disables automatic clearing of the ADST bit in scan mode. 0: The ADST bit is not automatically cleared to 0 in scan mode. 1: The ADST bit is cleared to 0 upon completion of the A/D conversion for all of the selected channels in scan mode. [Legend] x: Don't care Note: * Setting prohibited in the H8S/2424 group. Rev. 1.00 Sep. 19, 2008 Page 971 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.4 Operation The A/D converter has two operating modes: single mode and scan mode. First select the clock for A/D conversion (ADCLK). When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 17.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the analog input of the specified single channel. 1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger input. 2. When A/D conversion is completed, the A/D conversion result is transferred to the corresponding A/D data register of the channel. 3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains at 1 during A/D conversion, and is automatically cleared to 0 when A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters a wait state. Rev. 1.00 Sep. 19, 2008 Page 972 of 1270 REJ09B0466-0100 Section 17 A/D Converter Set* ADIE Set* ADST A/D conversion start Clear* ADF Clear* Set* Channel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state ADDRA Waiting for conversion Waiting for conversion A/D conversion 1 Waiting for conversion A/D conversion 2 Waiting for conversion Waiting for conversion Waiting for conversion Reading A/D conversion result Reading A/D conversion result A/D conversion result 2 ADDRB ADDRC A/D conversion result 1 ADDRD Note: * indicates the timing of instruction execution by software. Figure 17.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 1.00 Sep. 19, 2008 Page 973 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.4.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight* channels. Two types of scan mode are provided, that is, continuous scan mode where A/D conversion is repeatedly performed and one-cycle scan mode where A/D conversion is performed for the specified channels for one cycle. (1) Continuous Scan Mode 1. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger input, A/D conversion starts on the first channel in the specified channel group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight channels (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is performed on four channels, A/D conversion starts on AN0 when CH3 and CH2 of unit 0 = B'00, on AN4 when CH3 and CH2 of unit 1 = B'01, on AN8* when CH3 and CH2 of unit 1 = B'10, or on AN12 when CH3 and CH2 of unit 1= B'11. When consecutive A/D conversion is performed on eight channels, A/D conversion starts on AN0 when CH3 = B'0 or on AN8* when CH3 = B'1. 2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially transferred to the corresponding ADDR of each channel. 3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of the first channel in the group starts again. 4. The ADST bit is not cleared automatically, and steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from the first channel in the group. Note: * Only possible in the H8S/2426 group and H8S/2426R group. Rev. 1.00 Sep. 19, 2008 Page 974 of 1270 REJ09B0466-0100 Section 17 A/D Converter A/D conversion consecutive execution Set*1 ADST Clear*1 Clear*1 ADF Channel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state ADDRA Waiting for conversion A/D conversion 1 A/D conversion time Waiting for conversion A/D conversion 2 A/D conversion 4 Waiting for conversion A/D conversion 5 Waiting for conversion Waiting for conversion Waiting for conversion A/D conversion 3 *2 Waiting for conversion Waiting for conversion Waiting for conversion Transfer A/D conversion result 1 A/D conversion result 4 ADDRB A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Notes: 1. indicates the timing of instruction execution by software. 2. Data being converted is ignored. Figure 17.4 Example of A/D Conversion (Continuous Scan Mode, Three Channels (AN0 to AN2) Selected) Rev. 1.00 Sep. 19, 2008 Page 975 of 1270 REJ09B0466-0100 Section 17 A/D Converter (2) One-Cycle Scan Mode 1. Set the ADSTCLR bit in ADCR to 1. 2. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger input, A/D conversion starts on the first channel in the specified channel group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight channels (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is performed on four channels, A/D conversion starts on AN0 when CH3 and CH2 of unit 0 = B'00, on AN4 when CH3 and CH2 of unit 1 = B'01, on AN8* when CH3 and CH2 of unit 1 = B'10, or on AN12 when CH3 and CH2 of unit 1= B'11. When consecutive A/D conversion is performed on eight channels, A/D conversion starts on AN0 when CH3 = B'0 or on AN8* when CH3 = B'1. 3. When A/D conversion for each channel is completed, the A/D conversion result is sequentially transferred to the corresponding ADDR of each channel. 4. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 5. The ADST bit is automatically cleared when A/D conversion is completed for all of the channels that have been selected. A/D conversion stops and the A/D converter enters a wait state. Note: * Only possible in the H8S/2426 group and H8S/2426R group. Rev. 1.00 Sep. 19, 2008 Page 976 of 1270 REJ09B0466-0100 Section 17 A/D Converter A/D conversion one-cycle execution Set * ADST Clear* ADF A/D conversion time Channel 4 (AN4) Waiting for conversion operation state A/D conversion 1 Waiting for conversion Channel5 (AN5) operation state Channel 6 (AN6) operation state Channel 7 (AN7) operation state Waiting for conversion A/D conversion 2 Waiting for conversion Waiting for conversion A/D conversion 3 Waiting for conversion Waiting for conversion Transfer ADDRE A/D conversion result 1 ADDRF A/D conversion result 2 ADDRG A/D conversion result 3 ADDRH Note: * indicates the timing of instruction execution by software. Figure 17.5 Example of A/D Conversion (One-Cycle Scan Mode, Three Channels (AN4 to AN6) Selected) Rev. 1.00 Sep. 19, 2008 Page 977 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 17.6 shows the A/D conversion timing. Tables 17.5 and 17.6 show the A/D conversion time. As shown in figure 17.6, the A/D conversion time (tCONV) includes the A/D conversion start delay time (tD) and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in tables 17.5 and 17.6. In scan mode, the values given in tables 17.5 and 17.6 apply to the first conversion time. The values given in table 17.7 apply to the second and subsequent conversions. In either case, bit EKCKS in ADCSR, and bits CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the A/D conversion characteristics. (1) P Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay time tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 17.6 A/D Conversion Timing Rev. 1.00 Sep. 19, 2008 Page 978 of 1270 REJ09B0466-0100 Section 17 A/D Converter Table 17.5 A/D Conversion Characteristics (EXCKS = 0) CKS1 = 0 CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time tSPL tCONV 515 319 530 259 159 266 131 79 134 67 29 68 Symbol tD Min. 18 Typ. Max. 33 Min. 10 CKS = 1 Typ. Max. 17 Min. 6 CKS = 0 Typ. Max. 9 Min. 4 CKS1 = 1 CKS = 1 Typ. Max. 5 Note: Values in the table are the number of states. Table 17.6 A/D Conversion Characteristics (EXCKS = 1) (Units 1 and 2) CKS1 = 0 CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time tSPL tCONV 325 120 332 165 60 168 85 30 87 45 15 46 Symbol tD Min. 3 Typ. Max. 10 Min. 3 CKS = 1 Typ. Max. 6 Min. 3 CKS = 0 Typ. Max. 5 Min. 3 CKS1 = 1 CKS = 1 Typ. Max. 4 Note: Values in the table are the number of states. Table 17.7 A/D Conversion Time (Scan Mode) EXCKS 0 CKS1 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Conversion Time (Number of States) 512 (fixed) 256 (fixed) 128 (fixed) 64 (fixed) 512 (fixed) 256 (fixed) 128 (fixed) 64 (fixed) Rev. 1.00 Sep. 19, 2008 Page 979 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.4.4 External Trigger Input Timing A/D conversion can be externally triggered. For unit 0, an external trigger is input from the ADTRG0 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 or B'001 in ADCR_0. For unit 1, an external trigger is input from the ADTRG1 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 in ADCR_1. For multiple-unit simultaneous start, an external trigger is input from the ADTRG0 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'111 in ADCR. A/D conversion starts when the ADST bit in ADCSR is set to 1 on the falling edge of the ADTRG0 pin. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 17.7 shows the timing. Figure 17.8 shows the timing of multiple-unit simultaneous start. P ADTRG0 Internal trigger signal ADST A/D conversion Figure 17.7 External Trigger Input Timing (TRGS1, TRGS0, and EXTRGS B'111) Rev. 1.00 Sep. 19, 2008 Page 980 of 1270 REJ09B0466-0100 Section 17 A/D Converter P ADTRG0 Internal trigger signal ADST A/D conversion Figure 17.8 External Trigger Input Timing when Multiple Units Start Simultaneously (TRSG1, TRGS0, and EXTRGS = B'111) 17.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is completed enables ADI interrupt requests. The data transfer controller (DTC)* and DMA controller (DMAC) can be activated by an ADI interrupt. Having the converted data read by the DTC* or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. Note: * Only possible in unit 0. Table 17.8 A/D Converter Interrupt Source Name ADI0 Note: * Interrupt Source A/D conversion end Only possible in unit 0. Interrupt Flag ADF DTC Activation Possible* DMAC Activation Possible Rev. 1.00 Sep. 19, 2008 Page 981 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes. * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.9). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 17.10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 17.10). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 17.10). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 1.00 Sep. 19, 2008 Page 982 of 1270 REJ09B0466-0100 Section 17 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 17.9 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage Offset error Figure 17.10 A/D Conversion Accuracy Definitions Rev. 1.00 Sep. 19, 2008 Page 983 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.7 17.7.1 Usage Notes Module Stop Function Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing the module stop state. Set the CKS1 and CKS2 bits to 1 to set ADCLK to , and clear the ADST, TRGS1, TRGS0, and EXTRGS bits all to 0 to disable A/D conversion when entering module stop state after operation of the A/D converter. After that, set the module stop control register after executing a dummy read by one word. For details, see section 24, Power-Down Modes. 17.7.2 A/D Input Hold Function in Software Standby Mode When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are retained, and the analog power supply current is equal to as during A/D conversion. If the analog power supply current needs to be reduced in software standby mode, set the CKS1 and CKS2 bits to 1 to set ADCLK to , and clear the ADST, TRGS1, TRGS0, and EXTRGS bits all to 0 to disable A/D conversion. After that, enter software standby mode after executing a dummy read by one word. 17.7.3 Restarting the A/D Converter When the ADST bit has been cleared to 0, A/D converter stops in synchronization with the ADCLK and then enters the standby sate. After the ADST bit has been cleared, the converter may not actually make the transition to the standby state for up to 10 cycles (), so do not change the channels of the ADCLK, motion mode, or analog input at this time. When restarting the A/D converter right after the ADST bit has been cleared to 0, read the 16 bytes from ADDRA to ADDRH and then start the A/D converter by setting the ADST bit to 1. If the converter is in single mode or one-cycle scan mode, however, the ADST bit can be set to 1 by clearing the ADF bit to 0 after confirming that the ADF bit had been set to 1 on completion of the previous round of conversion. Rev. 1.00 Sep. 19, 2008 Page 984 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.7.4 Permissible Signal Source Impedance This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of 5 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 17.11). When converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted. This LSI Sensor output impedance R to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF 7 pF Equivalent circuit of the A/D converter 10 k Figure 17.11 Example of Analog Input Circuit Rev. 1.00 Sep. 19, 2008 Page 985 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.7.5 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, acting as antennas. 17.7.6 Setting Range of Analog Power Supply and Other Pins If the conditions shown below are not met, the reliability of the LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN Vref. * Relation between AVcc, AVss and Vcc, Vss As the relationship between AVcc, AVss and Vcc, Vss, set AVcc = Vcc 0.3 V and AVss = Vss. If the A/D converter is not used, set AVcc = Vcc and AVss = Vss. * Vref setting range The reference voltage at the Vref pin should be set in the range Vref AVcc. Rev. 1.00 Sep. 19, 2008 Page 986 of 1270 REJ09B0466-0100 Section 17 A/D Converter 17.7.7 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Digital circuitry must be isolated from the analog input pins (AN0 to AN15*), analog reference power supply (Vref), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. Note: * In the H8S/2424 group, only AN0 to AN7, AN11, and AN12 are available as analog input pins. 17.7.8 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15*) should be connected between AVcc and AVss as shown in figure 17.12. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to the AN0 to AN11 pins must be connected to AVss. If a filter capacitor is connected, the input currents at the AN0 to AN15* pins are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. Note: * In the H8S/2424 group, only AN0 to AN7, AN11, and AN12 are available as analog input pins. Rev. 1.00 Sep. 19, 2008 Page 987 of 1270 REJ09B0466-0100 Section 17 A/D Converter AVCC Vref Rin* 2 *1 *1 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 100 AN0 to AN15* 3 2. Rin: Input impedance 3. The H8S/2424 group has only AN0 to AN7, AN11, and AN12 as analog input pins. Figure 17.12 Example of Analog Input Protection Circuit Table 17.9 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min. Max. 15 5 Unit pF k Rev. 1.00 Sep. 19, 2008 Page 988 of 1270 REJ09B0466-0100 Section 18 D/A Converter Section 18 D/A Converter 18.1 Features D/A converter features are listed below. * * * * * * 8-bit resolution Output channels: Two channels Maximum conversion time of 10 s (with 20 pF load) Output voltage of 0 V to Vref D/A output hold function in software standby mode Setting the module stop mode Rev. 1.00 Sep. 19, 2008 Page 989 of 1270 REJ09B0466-0100 Section 18 D/A Converter Vref 8-bit DA3 DA2 AVss D/A Control circuit Legend: DADR2: D/A data register 2 DADR3: D/A data register 3 DACR23: D/A control register 23 Figure 18.1 Block Diagram of D/A Converter Rev. 1.00 Sep. 19, 2008 Page 990 of 1270 REJ09B0466-0100 DACR23 DADR2 DADR3 AVcc Bus interface Module data bus Internal data bus Section 18 D/A Converter 18.2 Input/Output Pins Table 18.1 shows the pin configuration of the D/A converter. Table 18.1 Pin Configuration Pin Name Analog power pin Analog ground pin Reference voltage pin Analog output pin 2 Analog output pin 3 Symbol AVCC AVSS Vref DA2 DA3 I/O Input Input Input Output Output Function Analog power Analog ground Reference voltage of D/A converter Channel 2 analog output Channel 3 analog output Rev. 1.00 Sep. 19, 2008 Page 991 of 1270 REJ09B0466-0100 Section 18 D/A Converter 18.3 Register Descriptions The D/A converter has the following registers. * D/A data register 2 (DADR2) * D/A data register 3 (DADR3) * D/A control register 23 (DACR23) 18.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3) DADR2 and DADR3 are 8-bit readable/writable registers that store data for conversion. Whenever analog output is enabled, the values in DADR are converted and output to the analog output pins. 18.3.2 D/A Control Register 23 (DACR23) DACR23 controls the operation of channels 2 and 3 in the D/A converter. Bit 7 Bit Name DAOE3 Initial Value 0 R/W R/W Description D/A Output Enable 3 Controls D/A conversion and analog output. 0: Channel 3 analog output (DA3) is disabled. 1: Channel 3 D/A conversion is enabled; channel 3 analog output (DA3) is enabled. 6 DAOE2 0 R/W D/A Output Enable 2 Controls D/A conversion and analog output. 0: Channel 2 analog output (DA2) is disabled. 1: Channel 2 D/A conversion is enabled; channel 2 analog output (DA2) is enabled. Rev. 1.00 Sep. 19, 2008 Page 992 of 1270 REJ09B0466-0100 Section 18 D/A Converter Bit 5 Bit Name DAE Initial Value 0 R/W R/W Description D/A Enable This bit is used together with the DAOE2 and DAOE3 bits to control D/A conversion. When the DAE bit is cleared to 0, channel 2 and 3 D/A conversions are controlled independently. When the DAE bit is set to 1, channel 2 and 3 D/A conversions are controlled together. Output of conversion results is always controlled independently by the DAOE2 and DAOE3 bits. For details, see table 18.2. 4 to 0 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. Rev. 1.00 Sep. 19, 2008 Page 993 of 1270 REJ09B0466-0100 Section 18 D/A Converter Table 18.2 Control of D/A Conversion Bit 5 DAE 0 Bit 7 Bit 6 DAOE3 DAOE2 0 0 1 Description D/A conversion disabled Channel 2 D/A conversion enabled, and channel 3 D/A conversion disabled. Channel 2 analog output (DA2) enabled, and channel 3 analog output (DA3) disabled. 1 0 Channel 2 D/A conversion disabled, and channel 3 D/A conversion enabled. Channel 2 analog output (DA2) disabled, channel 3 analog output (DA3) enabled. 1 1 0 0 1 Channel 2 and 3 D/A conversions enabled. Channel 2 and 3 analog outputs (DA2 and DA3) enabled. Channel 2 and 3 D/A conversions enabled. Channel 2 and 3 analog outputs (DA2 and DA3) disabled. Channel 2 and 3 D/A conversions enabled. Channel 2 analog output (DA2) enabled, and channel 3 analog output (DA3) disabled. 1 0 Channel 2 and 3 D/A conversions enabled. Channel 2 analog output (DA2) disabled, and channel 3 analog output (DA3) enabled. 1 Channel 2 and 3 D/A conversions enabled. Channel 2 and 3 analog outputs (DA2 and DA3) enabled. Rev. 1.00 Sep. 19, 2008 Page 994 of 1270 REJ09B0466-0100 Section 18 D/A Converter 18.4 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When DAOE bit in DACR23 is set to 1, D/A conversion is enabled and the conversion result is output. The following shows an example of D/A conversion on channel 2. Figure 18.2 shows the timing of this operation. 1. Write the conversion data to DADR2. 2. Set the DAOE2 bit in DACR23 to 1. D/A conversion is started. The conversion result is output from the analog output pin DA2 after the conversion time tDCONV has elapsed. The conversion result is continued to output until DADR2 is written to again or the DAOE2 bit is cleared to 0. The output value is expressed by the following formula: DADR contents x Vref 256 3. If DADR2 is written to again, the conversion is immediately started. The conversion result is output after the conversion time tDCONV has elapsed. 4. If the DAOE2 bit is cleared to 0, analog output is disabled. Rev. 1.00 Sep. 19, 2008 Page 995 of 1270 REJ09B0466-0100 Section 18 D/A Converter DADR2 write cycle DACR23 write cycle DADR2 write cycle DACR23 write cycle Address DADR2 Conversion data 1 Conversion data 2 DAOE2 DA2 High-impedance state tDCONV Legend: tDCONV: D/A conversion time Conversion result 1 tDCONV Conversion result 2 Figure 18.2 Example of D/A Converter Operation Rev. 1.00 Sep. 19, 2008 Page 996 of 1270 REJ09B0466-0100 Section 18 D/A Converter 18.5 18.5.1 Usage Notes Setting for Module Stop Mode It is possible to enable/disable the D/A converter operation using the module stop control register; the D/A converter does not operate by the initial value of the register. The register can be accessed by releasing the module stop mode. For details, see section 24, Power-Down Modes. 18.5.2 D/A Output Hold Function in Software Standby Mode If D/A conversion is enabled and this LSI enters software standby mode, D/A output is held and analog power supply current remains at the same level during D/A conversion. When the analog power supply current is required to go low in software standby mode, bits DAOE and DAE should be cleared to 0, and D/A output should be disabled. Rev. 1.00 Sep. 19, 2008 Page 997 of 1270 REJ09B0466-0100 Section 18 D/A Converter Rev. 1.00 Sep. 19, 2008 Page 998 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Section 19 Synchronous Serial Communication Unit (SSU) This LSI has one channel of synchronous serial communication unit (SSU). The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity and clock phase. Figure 19.1 is a block diagram of the SSU. 19.1 * * * * * * Features * * * * * Choice of SSU mode and clock synchronous mode Choice of master mode and slave mode Choice of standard mode and bidirectional mode Synchronous serial communication with devices with different clock polarity and clock phase Choice of 8/16/24/32-bit width of transmit/receive data Full-duplex communication capability The shift register is incorporated, enabling transmission and reception to be executed simultaneously. Consecutive serial communication Choice of LSB-first or MSB-first transfer Choice of a clock source Seven internal clocks (/4, /8, /16, /32, /64, /128, /256) or an external clock Five interrupt sources Transmit-end, transmit-data-register-empty, receive-data-full, overrun-error, and conflict error Module stop mode can be set Rev. 1.00 Sep. 19, 2008 Page 999 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Figure 19.1 shows a block diagram of the SSU. Module data bus Bus interface Internal data bus SSCRH SSTDR 0 SSTDR 1 SSTDR 2 SSTDR 3 SSRDR 0 SSRDR 1 SSRDR 2 SSRDR 3 SSCRL SSMR SSER SSSR Control circuit OEI CEI RXI TXI TEI SSTRSR Shiftout Shiftin Clock Clock selector /4 /8 /16 /32 /64 /128 /256 Selector SSI [Legend] SSCRH: SSCRL: SSCR2: SSMR: SSER: SSSR: SSTDR0 to SSTDR3: SSRDR0 to SSRDR3: SSTRSR: SSO SCS SSCK (External clock) SS control register H SS control register L SS control register 2 SS mode register SS enable register SS status register SS transmit data registers 0 to 3 SS receive data registers 0 to 3 SS shift register Figure 19.1 Block Diagram of SSU Rev. 1.00 Sep. 19, 2008 Page 1000 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.2 Input/Output Pins Table 19.1 shows the SSU pin configuration. Table 19.1 Pin Configuration Channel 0 Symbol SSCK0 SSI0 SSO0 SCS0 Note: * I/O I/O I/O I/O I/O Function SSU clock input/output SSU data input/output SSU data input/output SSU chip select input/output Because channel numbers are omitted in later descriptions, these are shown SSCK, SSI, SSO, and SCS. 19.3 Register Descriptions The SSU has the following registers. * * * * * * * * * * * * * * * SS control register H_0 (SSCRH_0) SS control register L_0 (SSCRL_0) SS mode register_0 (SSMR_0) SS enable register_0 (SSER_0) SS status register_0 (SSSR_0) SS control register 2_0 (SSCR2_0) SS transmit data register 0_0 (SSTDR0_0) SS transmit data register 1_0 (SSTDR1_0) SS transmit data register 2_0 (SSTDR2_0) SS transmit data register 3_0 (SSTDR3_0) SS receive data register 0_0 (SSRDR0_0) SS receive data register 1_0 (SSRDR1_0) SS receive data register 2_0 (SSRDR2_0) SS receive data register 3_0 (SSRDR3_0) SS shift register_0 (SSTRSR_0) Rev. 1.00 Sep. 19, 2008 Page 1001 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.3.1 SS Control Register H (SSCRH) SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. Bit 7 Bit Name MSS Initial Value 0 R/W R/W Description Master/Slave Device Select Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. 0: Slave mode is selected. 1: Master mode is selected. 6 BIDE 0 R/W Bidirectional Mode Enable Selects that both serial data input pin and output pin are used or one of them is used. However, transmission and reception are not performed simultaneously when bidirectional mode is selected. For details, section 19.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: Standard mode (two pins are used for data input and output) 1: Bidirectional mode (one pin is used for data input and output) 5 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 1002 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Bit 4 Bit Name SOL Initial Value 0 R/W R/W Description Serial Data Output Value Select The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit. When specifying the output level, use the MOV instruction after clearing the SOLP bit to 0. Since writing to this bit during data transmission causes malfunctions, this bit should not be changed. 0: Serial data output is changed to low. 1: Serial data output is changed to high. 3 SOLP 1 R/W SOL Bit Write Protect When changing the output level of serial data, set the SOL bit to 1 or clear the SOL bit to 0 after clearing the SOLP bit to 0 using the MOV instruction. 0: Output level can be changed by the SOL bit 1: Output level cannot be changed by the SOL bit. This bit is always read as 1. 2 SCKS 0 R/W SSCK Pin Select Selects that the SSCK pin functions as a port or a serial clock pin. When the SSCK pin is used as a serial clock pin, this bit must be set to 1. 0: Functions as an I/O port. 1: Functions as a serial clock. 1 0 CSS1 CSS0 0 0 R/W R/W SCS Pin Select Select that the SCS pin functions as a port or SCS input or output. However, when MSS = 0, the SCS pin functions as an input pin regardless of the CSS1 and CSS0 settings. 00: I/O port 01: Function as SCS input 10: Function as SCS automatic input/output (function as SCS input before and after transfer and output a low level during transfer) 11: Function as SCS automatic output (outputs a high level before and after transfer and outputs a low level during transfer) Rev. 1.00 Sep. 19, 2008 Page 1003 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.3.2 SS Control Register L (SSCRL) SSCRL selects operating mode, software reset, and transmit/receive data length. Bit 7 Bit Name Initial Value 0 R/W R/W Description Reserved This bit is always read as 0. The write value should always be 0. 6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock synchronous mode. 0: SSU mode 1: Clock synchronous mode 5 SRES 0 R/W Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer. After that, this bit is automatically cleared. The ORER, TEND, TDRE, RDRF, and CE bits in SSSR and the TE and RE bits in SSER are also initialized. Values of other bits for SSU registers are held. To stop transfer, set this bit to 1 to reset the SSU internal sequencer. 4 to 2 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 1 0 DATS1 DATS0 0 0 R/W R/W Transmit/Receive Data Length Select Select serial data length. 00: 8 bits 01: 16 bits 10: 32 bits 11: 24 bits Rev. 1.00 Sep. 19, 2008 Page 1004 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.3.3 SS Mode Register (SSMR) SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication. Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB First/LSB First Select Selects that the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first Clock Polarity Select Selects the SSCK clock polarity. 0: High output in idle mode, and low output in active mode 1: Low output in idle mode, and high output in active mode Clock Phase Select (Only for SSU Mode) Selects the SSCK clock phase. 0: Data changes at the first edge. 1: Data is latched at the first edge. Reserved These bits are always read as 0. The write value should always be 0. Transfer Clock Rate Select Select the transfer clock rate when an internal clock is selected. 000: Reserved 100: /32 001: /4 101: /64 010: /8 110: /128 011: /16 111: /256 6 CPOS 0 R/W 5 CPHS 0 R/W 4, 3 All 0 R/W 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Rev. 1.00 Sep. 19, 2008 Page 1005 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.3.4 SS Enable Register (SSER) SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. Bit 7 6 5, 4 Bit Name TE RE Initial Value 0 0 All 0 R/W R/W R/W R/W Description Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Reserved These bits are always read as 0. The write value should always be 0. 3 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. 2 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 1 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, an RXI interrupt request and an OEI interrupt request are enabled. 0 CEIE 0 R/W Conflict Error Interrupt Enable When this bit is set to 1, a CEI interrupt request is enabled. Rev. 1.00 Sep. 19, 2008 Page 1006 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.3.5 SS Status Register (SSSR) SSSR is a status flag register for interrupts. Bit 7 Bit Name Initial Value 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. Overrun Error If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination. SSRDR stores 1-frame receive data before an overrun error occurs and loses data to be received later. While ORER = 1, consecutive serial reception cannot be continued. Serial transmission cannot be continued, either. [Setting condition] When one byte of the next reception is completed with RDRF = 1 [Clearing condition] When writing 0 after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 5, 4 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 6 ORER 0 R/W Rev. 1.00 Sep. 19, 2008 Page 1007 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Bit 3 Bit Name TEND Initial Value 1 R/W R Description Transmit End [Setting condition] * When the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is cleared to 0 and the TDRE bit is set to 1 * After the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is set to 1 and the TDRE bit is set to 1 [Clearing conditions] * When writing 0 after reading TEND = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When writing data to SSTDR Transmit Data Empty Indicates whether or not SSTDR contains transmit data. [Setting conditions] * When the TE bit in SSER is 0 * When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to. [Clearing conditions] * When writing 0 after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When writing data to SSTDR with TE = 1 Receive Data Register Full Indicates whether or not SSRDR contains receive data. [Setting condition] * When receive data is transferred from SSTRSR to SSRDR after successful serial data reception [Clearing conditions] * When writing 0 after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) When reading receive data from SSRDR 2 TDRE 1 R/W 1 RDRF 0 R/W * Rev. 1.00 Sep. 19, 2008 Page 1008 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Bit 0 Bit Name CE Initial Value 0 R/W R/W Description Conflict/Incomplete Error Indicates that a conflict error has occurred when 0 is externally input to the SCS pin with SSUMS = 0 (SSU mode) and MSS = 1 (master device). If the SCS pin level changes to 1 with SSUMS = 0 (SSU mode) and MSS = 0 (slave device), an incomplete error occurs because it is determined that a master device has terminated the transfer. Data reception does not continue while the CE bit is set to 1. Serial transmission also does not continue. Reset the SSU internal sequencer by setting the SRES bit in SSCRL to 1 before resuming transfer after incomplete error. [Setting condition] * When a low level is input to the SCS pin in master device (the MSS bit in SSCRH is set to 1) * When the SCS pin is changed to 1 during transfer in slave device (the MSS bit in SSCRH is cleared to 0) [Clearing condition] * When writing 0 after reading CE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Rev. 1.00 Sep. 19, 2008 Page 1009 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.3.6 SS Control Register 2 (SSCR2) SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of the TEND bit. Bit 7 Bit Name SDOS Initial Value 0 R/W R/W Description Serial Data Pin Open Drain Select Selects whether the serial data output pin is used as a CMOS or an NMOS open drain output. Pins to output serial data differ according to the register setting. For details, 19.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: CMOS output 1: NMOS open drain output 6 SSCKOS 0 R/W SSCK Pin Open Drain Select Selects whether the SSCK pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output 5 SCSOS 0 R/W SCS Pin Open Drain Select Selects whether the SCS pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output 4 TENDSTS 0 R/W Selects the timing of setting the TEND bit (valid in SSU and master mode). 0: Sets the TEND bit when the last bit is being transmitted 1: Sets the TEND bit after the last bit is transmitted Rev. 1.00 Sep. 19, 2008 Page 1010 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Bit 3 Bit Name SCSATS Initial Value 0 R/W R/W Description Selects the assertion timing of the SCS pin (valid in SSU and master mode). 0: Min. values of tLEAD and tLAG are 1/2 x tSUcyc 1: Min. values of tLEAD and tLAG are 3/2 x tSUcyc 2 SSODTS 0 R/W Selects the data output timing of the SSO pin (valid in SSU and master mode) 0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data 1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data while the SCS pin is driven low 1, 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 1011 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3) SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 24-bit data length is selected, SSTDR0, SSTDR1, and SSTDR2 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Be sure not to access to invalid SSTDRs. When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has already been written to SSTDR during serial transmission, the SSU performs consecutive serial transmission. Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is set to 1. Table 19.2 Correspondence Between DATS Bit Setting and SSTDR DATS[1:0] (SSCRL[1:0]) SSTDR 0 1 2 3 00 Valid Invalid Invalid Invalid 01 Valid Valid Invalid Invalid 10 Valid Valid Valid Valid 11 (Setting Invalid) Valid Valid Valid Invalid Rev. 1.00 Sep. 19, 2008 Page 1012 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 24-bit data length is selected, SSRDR0, SSRDR1, and SSRDR2 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. Be sure not to access to invalid SSRDR. When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR function as a double buffer in this way, consecutive receive operations can be performed. Read SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR is a read-only register, therefore, cannot be written to by the CPU. Table 19.3 Correspondence Between DATS Bit Setting and SSRDR DATS[1:0] (SSCRL[1:0]) SSRDR 0 1 2 3 00 Valid Invalid Invalid Invalid 01 Valid Valid Invalid Invalid 10 Valid Valid Valid Valid 11 (Setting Invalid) Valid Valid Valid Invalid 19.3.9 SS Shift Register (SSTRSR) SSTRSR is a shift register that transmits and receives serial data. When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to perform serial data transmission. In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB (bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed by the CPU. Rev. 1.00 Sep. 19, 2008 Page 1013 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.4 19.4.1 Operation Transfer Clock A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin. 19.4.2 Relationship of Clock Phase, Polarity, and Data The relationship of clock phase, polarity, and transfer data depends on the combination of the CPOS and CPHS bits in SSMR. Figure 19.2 shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting is valid. Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the LSB. (1) When CPHS = 0 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO (2) When CPHS = 1 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 19.2 Relationship of Clock Phase, Polarity, and Data Rev. 1.00 Sep. 19, 2008 Page 1014 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.4.3 Relationship between Data Input/Output Pins and Shift Register The connection between data input/output pins and the SS shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 19.3 shows the relationship. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 19.3 (1)). The SSU transmits serial data from the SSI pin and receives serial data from the SSO pin when operating with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 19.3 (2)). The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode when operating with BIDE = 1 (bidirectional mode) (see figures 19.3 (3) and (4)). However, even if both the TE and RE bits are set to 1, transmission and reception are not performed simultaneously. Either the TE or RE bit must be selected. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function as an input pin when MSS = 0 (see figures 19.3 (5) and (6)). (1) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 1, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSO SSI (4) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 1, and either TE or RE = 1 SSCK Shift register (SSTRSR) SSO SSI (5) When SSUMS = 1 and MSS = 1 SSCK Shift register (SSTRSR) SSO SSI (2) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 0, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSO SSI (3) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 0, and either TE or RE = 1 SSCK Shift register (SSTRSR) SSO SSI (6) When SSUMS = 1 and MSS = 0 SSCK Shift register (SSTRSR) SSO SSI Figure 19.3 Relationship between Data Input/Output Pins and the Shift Register Rev. 1.00 Sep. 19, 2008 Page 1015 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.4.4 Communication Modes and Pin Functions The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the communication modes and register settings. When a pin is used as an input pin, set the corresponding bit in the input buffer control register (ICR) to 1. The relationship of communication modes and input/output pin functions are shown in tables 19.4 to 19.6. Table 19.4 Communication Modes and Pin States of SSI and SSO Pins Communication Mode SSU communication mode Register Setting SSUMS 0 BIDE 0 MSS 0 TE 0 1 RE 1 0 1 1 0 1 1 0 1 SSU (bidirectional) 0 communication mode 1 0 0 1 1 0 1 Clock synchronous 1 communication mode 0 0 0 1 1 0 1 0 1 0 1 1 0 1 [Legend] : Not used as SSU pin (can be used as I/O port) 1 0 1 SSI Output Output Input Input Input Input Input Input Pin State SSO Input Input Output Output Input Output Input Output Output Output Output Output Rev. 1.00 Sep. 19, 2008 Page 1016 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Table 19.5 Communication Modes and Pin States of SSCK Pin Communication Mode SSU communication mode Register Setting SSUMS 0 MSS 0 SCKS 0 1 1 0 1 Clock synchronous 1 communication mode 0 0 1 1 [Legend] : Not used as SSU pin 0 1 Pin State SSCK Input Output Input Output Table 19.6 Communication Modes and Pin States of SCS Pin Communication Mode SSU communication mode Register Setting SSUMS 0 MSS 0 1 CSS1 x 0 0 1 1 Clock synchronous 1 communication mode [Legend] x: Don't care : Not used as SSU pin x x CSS0 x 0 1 0 1 x Pin State SCS Input Input Automatic input/output Output Rev. 1.00 Sep. 19, 2008 Page 1017 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.4.5 SSU Mode In SSU mode, data communications are performed via four lines: clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS). In addition, the SSU supports bidirectional mode in which a single pin functions as data input and data output lines. (1) Initial Settings in SSU Mode Figure 19.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values. Start setting initial values Clear TE and RE bits in SSER to 0 [1] Set a bit in ICR to 1 Specify MSS, BIDE, SOL, SCKS, CSS1, and CSS0 bits in SSCRH Clear SSUMS in SSCRL to 0 and specify bits DATS1 and DATS0 Specify MLS, CPOS, CPHS, CKS2, CKS1, and CKS0 bits in SSMR Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS and SSODTS bits in SSCR2 [5] Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER smulataneously [1] When the pin is used as an input. [2] Specify master/slave mode selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. [3] Selects SSU mode and specify transmit/receive data length. [4] Specify MSB first/LSB first selection, clock polarity selection, clock phase selection, and transfer clock rate selection. [5] Enables/disables interrupt request to the CPU. [2] [3] [4] End Figure 19.4 Example of Initial Settings in SSU Mode Rev. 1.00 Sep. 19, 2008 Page 1018 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) (2) Data Transmission Figure 19.5 shows an example of transmission operation, and figure 19.6 shows a flowchart example of data transmission. When transmitting data, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0. Rev. 1.00 Sep. 19, 2008 Page 1019 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) SCS SSCK SSO Bit 0 Bit 1 Bit 2 1 frame 1 frame Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) TDRE TEND TXI interrupt generated Data written to SSTDR0 TEI interrupt generated TXI interrupt generated Data written to SSTDR0 TEI interrupt generated LSI operation User operation Figure 19.5 (1) Example of Transmission Operation (SSU Mode) When 8-Bit Data Length is Selected (SSTDR0 is Valid) with CPOS = 0 and CPHS = 0 1 frame SCS SSCK SSO (LSB first) SSO (MSB first) TDRE TEND Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSTDR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 SSTDR0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR0 SSTDR1 LSI operation User operation TXI interrupt generated Data written to SSTDR0 and SSTDR1 TEI interrupt generated Figure 19.5 (2) Example of Transmission Operation (SSU Mode) When 16-Bit Data Length is Selected (SSTDR0 and SSTDR1 are Valid) with CPOS = 0 and CPHS = 0 Rev. 1.00 Sep. 19, 2008 Page 1020 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) SCS SSCK SSO (LSB first) SSO (MSB first) TDRE TEND Bit 0 Bit 1 to Bit 6 Bit 7 Bit 0 1 frame Bit 1 to Bit 6 Bit 7 Bit 0 Bit 1 to Bit 6 Bit 7 SSTDR2 Bit 7 Bit 6 to Bit 1 Bit 0 Bit 7 SSTDR1 Bit 6 to Bit 1 Bit 0 Bit 7 SSTDR0 Bit 6 to Bit 1 Bit 0 SSTDR0 SSTDR1 SSTDR2 LSI operation User operation TXI interrupt generated Data written to SSTDR0, SSTDR1, and SSTDR2 TEI interrupt generated Figure 19.5 (3) Example of Transmission Operation (SSU Mode) When 24-Bit Data Length is Selected (SSTDR0, SSTDR1, and SSTDR2 are Valid) with CPOS = 0 and CPHS = 0 1 frame SCS SSCK SSO (LSB first) Bit 0 to Bit 7 Bit 0 to Bit 7 Bit 0 to Bit 7 Bit 0 to Bit 7 SSTDR3 SSTDR2 Bit 7 to Bit 0 SSTDR1 Bit 7 to Bit 0 Bit 7 SSTDR0 to Bit 0 SSO (MSB first) Bit 7 to Bit 0 SSTDR0 SSTDR1 SSTDR2 SSTDR3 TDRE TEND LSI operation User operation TXI interrupt generated TEI interrupt generated Data written to SSTDR0, SSTDR1, SSTDR2 and SSTDR3 Figure 19.5 (4) Example of Transmission Operation (SSU Mode) When 32-Bit Data Length is Selected (SSTDR0, SSTDR1, SSTDR2 and SSTDR3 are Valid) with CPOS = 0 and CPHS = 0 Rev. 1.00 Sep. 19, 2008 Page 1021 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Start [1] [2] Initial setting Read TDRE in SSSR TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR [1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Yes No Set TDRE to 1 to start transmission [3] Consecutive data transmission? No Read TEND in SSSR TEND = 1? Yes Clear TEND to 0 Confirm that TEND is cleared to 0 [4] One bit time quantum elapsed? Yes Clear TE in SSER to 0 End transmission Note: Hatching boxes represent SSU internal operations. No No Figure 19.6 Flowchart Example of Data Transmission (SSU Mode) Rev. 1.00 Sep. 19, 2008 Page 1022 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) (3) Data Reception Figure 19.7 shows an example of reception operation, and figure 19.8 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0. 1 frame 1 frame SCS SSCK SSI Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR0 (LSB first transmission) SSRDR0 (MSB first transmission) RDRF REI interrupt generated Dummy-read SSRDR0 Read SSRDR0 REI interrupt generated LSI operation User operation Figure 19.7 (1) Example of Reception Operation (SSU Mode) When 8-Bit Data Length is Selected (SSRDR0 is Valid) with CPOS = 0 and CPHS = 0 Rev. 1.00 Sep. 19, 2008 Page 1023 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) SCS SSCK SSI (LSB first) SSI (MSB first) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 1 frame Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSRDR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 SSRDR0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR0 SSRDR1 RDRF RXI interrupt generated Dummy-read SSRDR0 and SSRDR1 LSI operation User operation Figure 19.7 (2) Example of Reception Operation (SSU Mode) When 16-Bit Data Length is Selected (SSRDR0 and SSRDR1 are Valid) with CPOS = 0 and CPHS = 0 1 frame SCS SSCK SSI (LSB first) SSI (MSB first) Bit 0 Bit 1 to Bit 6 Bit 7 Bit 0 Bit 1 to Bit 6 Bit 7 Bit 0 Bit 1 to Bit 6 Bit 7 SSRDR2 Bit 7 Bit 6 to Bit 1 Bit 0 Bit 7 SSRDR1 Bit 6 to Bit 1 Bit 0 Bit 7 SSRDR0 Bit 6 to Bit 1 Bit 0 SSRDR0 SSRDR1 SSRDR2 RDRF LSI operation User operation Dummy-read SSRDR0, SSRDR1, and SSRDR2 RXI interrupt generated Figure 19.7 Example of Reception Operation (SSU Mode) When 24-Bit Data Length is Selected (SSRDR0, SSRDR1, and SSRDR2 are Valid) with CPOS = 0 and CPHS = 0 (3) Rev. 1.00 Sep. 19, 2008 Page 1024 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) SCS SSCK SSI (LSB first) Bit 0 to Bit 7 Bit 0 to 1 frame Bit 7 Bit 0 to Bit 7 Bit 0 to Bit 7 SSRDR3 SSRDR2 Bit 7 to Bit 0 SSRDR1 Bit 7 to Bit 0 SSRDR0 Bit 7 to Bit 0 SSI (MSB first) Bit 7 to Bit 0 SSRDR0 SSRDR1 SSRDR2 SSRDR3 RDRF LSI operation User operation Dummy-read SSRDR0, SSRDR1, SSRDR2 and SSRDR3 RXI interrupt generated Figure 19.7 Example of Reception Operation (SSU Mode) When 32-Bit Data Length is Selected (SSRDR0, SSRDR1, SSRDR2 and SSRDR3 are Valid) with CPOS = 0 and CPHS = 0 (4) Rev. 1.00 Sep. 19, 2008 Page 1025 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Start [1] [2] [1] Initial setting Dummy-read SSRDR [2] Initial setting: Specify the receive data format. Start reception: When SSRDR is dummy-read with RE = 1, reception is started. Read SSSR No RDRF = 1? Yes ORER = 1? No [4] Consecutive data reception? Yes Read received data in SSRDR RDRF automatically cleared [5] No Yes [3] [3], [6] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [4] To continue single reception: When continuing single reception, wait for time of tSUcyc while the RDRF flag is set to 1 and then read receive data in SSRDR. The next single reception starts after reading receive data in SSRDR. To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed. [5] RE = 0 Read receive data in SSRDR End reception [6] Overrun error processing Clear ORER in SSSR End reception Note: Hatching boxes represent SSU internal operations. Figure 19.8 Flowchart Example of Data Reception (SSU Mode) Rev. 1.00 Sep. 19, 2008 Page 1026 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) (4) Data Transmission/Reception Figure 19.9 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bit to 1. Rev. 1.00 Sep. 19, 2008 Page 1027 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Start [1] [2] Initial setting Read TDRE in SSSR No [1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission/ reception is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR [3] No RDRF = 1? Yes Yes [4] ORER = 1? No Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? No Read TEND in SSSR No TEND = 1? Yes Clear TEND in SSSR to 0 Yes [5] Error processing No Has the 1 bit transfer period elapsed? Yes Clear TE and RE in SSER to 0 End transmission/reception Note: Hatching boxes represent SSU internal operations. Figure 19.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode) Rev. 1.00 Sep. 19, 2008 Page 1028 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.4.6 SCS Pin Control and Conflict Error When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is cleared to 0, the SCS pin functions as an input (Hi-Z) to detect conflict error. The conflict detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0. Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0 before resuming the transmission or reception. External input to SCS Internal-clocked SCS MSS Internal signal for transfer enable CE Data written to SSTDR (Hi-Z) Conflict error detection period Maximum time for internally clocking SCS SCS output Figure 19.10 Conflict Error Detection Timing (Before Transfer) P SCS (Hi-Z) MSS Internal signal for transfer enable CE Transfer end Conflict error detection period Figure 19.11 Conflict Error Detection Timing (After Transfer End) Rev. 1.00 Sep. 19, 2008 Page 1029 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.4.7 Clock Synchronous Communication Mode In clock synchronous communication mode, data communications are performed via three lines: clock line (SSCK), data input line (SSI), and data output line (SSO). (1) Initial Settings in Clock Synchronous Communication Mode Figure 19.12 shows an example of the initial settings in clock synchronous communication mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values. Start setting initial values Clear TE and RE bits in SSER to 0 [1] When the pin is used as an input. [2] Specify master/slave mode selection and SSCK pin selection. [3] Selects clock synchronous communication mode and specify transmit/receive data length. [4] Specify clock polarity selection and transfer clock rate selection. [5] Enables/disables interrupt request to the CPU. [1] Set a bit in ICR to 1 [2] Specify MSS and SCKS in SSCRH [3] Set SSUMS in SSCRL to 1 and specify bits DATS1 and DATS0 [4] Specify CPOS, CKS2, CKS1, and CKS0 bits in SSMR Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS, and SSODTS bits in SSCR2 [5] Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER simultaneously End Figure 19.12 Example of Initial Settings in Clock Synchronous Communication Mode Rev. 1.00 Sep. 19, 2008 Page 1030 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) (2) Data Transmission Figure 19.13 shows an example of transmission operation, and figure 19.14 shows a flowchart example of data transmission. When transmitting data in clock synchronous communication mode, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0. SSCK SSO Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 7 TDRE TEND LSI operation User operation TXI interrupt generated Data written to SSTDR Data written to SSTDR TXI interrupt generated TEI interrupt generated Figure 19.13 Example of Transmission Operation (Clock Synchronous Communication Mode) Rev. 1.00 Sep. 19, 2008 Page 1031 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Start [1] [2] Initial setting Read TDRE in SSSR TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR [4][1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Yes No Set TDRE to 1 to start transmission [3] Consecutive data transmission? No Read TEND in SSSR TEND = 1? Yes Clear TEND to 0 Confirm that TEND is cleared to 0 [4] One bit time quantum elapsed? Yes Clear TE in SSER to 0 End transmission No No Note: Hatching boxes represent SSU internal operations. Figure 19.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode) Rev. 1.00 Sep. 19, 2008 Page 1032 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) (3) Data Reception Figure 19.15 shows an example of reception operation, and figure 19.16 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit in SSER to 1, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0. SSCK SSO Bit 0 1 frame Bit 7 Bit 0 1 frame Bit 7 Bit 0 Bit 7 RDRF LSI operation User operation Dummy-read SSRDR RXI interrupt generated RXI interrupt generated Read data from SSRDR RXI interrupt generated Read data from SSRDR Figure 19.15 Example of Reception Operation (Clock Synchronous Communication Mode) Rev. 1.00 Sep. 19, 2008 Page 1033 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [1] Initial setting: Specify the receive data format. Read SSSR No RDRF = 1? Yes ORER = 1? No Consecutive data reception? [2], [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [3] Yes [2] To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed. No Yes Read received data in SSRDR RDRF automatically cleared [3] RE = 0 Read receive data in SSRDR End reception [4] Overrun error processing Clear ORER in SSSR End reception Note: Hatching boxes represent SSU internal operations. Figure 19.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode) Rev. 1.00 Sep. 19, 2008 Page 1034 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) (4) Data Transmission/Reception Figure 19.17 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bits to 1. Rev. 1.00 Sep. 19, 2008 Page 1035 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Start [1] [2] Initial setting Read TDRE in SSSR TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR [3] No RDRF = 1? Yes ORER = 1? No Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? No Read TEND in SSSR No TEND = 1? Yes Clear TEND in SSSR to 0 Yes [5] Yes [4] No [1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. Error processing No Has the 1 bit transfer period elapsed? Yes Clear TE and RE in SSER to 0 End transmission/reception Note: Hatching boxes represent SSU internal operations. Figure 19.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode) Rev. 1.00 Sep. 19, 2008 Page 1036 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) 19.5 Interrupt Requests The SSU interrupt requests are an overrun error, a conflict error, a receive data register full, transmit data register empty, and a transmit end interrupts. Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector address, and both a transmit data register empty and a transmit end interrupts are allocated to the SSTXI vector address, the interrupt source should be decided by their flags. Table 19.7 lists the interrupt sources. When an interrupt condition shown in table 19.7 is satisfied, an interrupt is requested. Clear the interrupt source by CPU or DMAC data transfer. Table 19.7 Interrupt Sources Channel Abbreviation Interrupt Source 0 SSERI0 Overrun error Conflict error SSRXI0 SSTXI0 Receive data register full Transmit data register empty Transmit end Symbol Interrupt Condition OEI0 CEI0 RXI0 TXI0 TEI0 (RIE = 1) * (ORER = 1) (CEIE = 1) * (CE = 1) (RIE = 1) * (RDRF = 1) (TIE = 1) * (TDRE = 1) (TEIE = 1) * (TEND = 1) DMAC Activation 19.6 19.6.1 Usage Note Setting of Module Stop Mode The SSU can be enabled/disabled by setting the module stop control register setting and is disabled by the initial value. Canceling module stop mode enables to access the SSU register. For details, see section 24, Power-Down Modes. Rev. 1.00 Sep. 19, 2008 Page 1037 of 1270 REJ09B0466-0100 Section 19 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Sep. 19, 2008 Page 1038 of 1270 REJ09B0466-0100 Section 20 RAM Section 20 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). Product Type H8S/24269 H8S/24269R H8S/24249 H8S/24268 H8S/24268R H8S/24265 H8S/24265R H8S/24248 H8S/24245 H8S/24262 H8S/24262R H8S/24242 H8S/24261 H8S/24261R H8S/24241 Note: * R4F24269 R4F24269R R4F24249 R4F24268 R4F24268R R4F24265 R4F24265R R4F24248 R4F24245 R4S24262 R4S24262R R4S24242 R4S24261 R4S24261R R4S24241 48 Kbytes H'FF0000 to H'FFBFFF ROM-less version 64 Kbytes* H'FEC000 to H'FFBFFF 48 Kbytes H'FF0000 to H'FFBFFF ROM Type Flash memory version RAM Capacity 64 Kbytes* RAM Address H'FEC000 to H'FFBFFF In planning. Rev. 1.00 Sep. 19, 2008 Page 1039 of 1270 REJ09B0466-0100 Section 20 RAM Rev. 1.00 Sep. 19, 2008 Page 1040 of 1270 REJ09B0466-0100 Section 21 Flash Memory Section 21 Flash Memory The flash memory in this LSI can be accessed in three programming modes: user programming mode, on-board programming mode, and programmer mode. Table 21.1 gives an overview of the flash memory specifications (refer to section 1, Overview, for items that are not shown in table 21.1). Table 21.1 Overview of Flash Memory Specifications Item Flash memory programming modes Erase block division Programming method Erase method Programming and erase control method Commands Programming and erase count Data retention User ROM Description Three modes (user programming mode, boot mode, and programmer mode) See figure 21.1. Word or byte units*1 Block units Programming and erasure are controlled by software commands Six commands 100 times*2 Ten years Notes: 1. The flash memory can be programmed in byte units only in parallel I/O mode. 2. The programming and erase count determine the number of times the erase operation can be performed in each block. For example, if 1-word programming is done 2,048 times, each at a different address in a 4-Kbyte block and then the block is erased, this is counted as one erase count. If the allowed programming and erase count are 100 times, each block can be erased 100 times. Rev. 1.00 Sep. 19, 2008 Page 1041 of 1270 REJ09B0466-0100 Section 21 Flash Memory Table 21.2 Overview of Flash Memory Programming Modes Flash Memory Programming Mode Item Functional overview User Programming Mode The user ROM is programmed by the CPU through execution of software commands. EW0 mode: Programming can be done from outside of the flash memory. Programmable User ROM, Data Flash* area Operating mode ROM programmer Note: * On-board Programming Mode Programmer Mode The user ROM is programmed The user ROM is through the on-chip SCI programmed through a interface. dedicated parallel programmer. Standard serial I/O mode 1: Clock-synchronous serial I/O Standard serial I/O mode 2: Asynchronous serial I/O User ROM, Data Flash* User ROM, Data Flash* Programmer mode Single-chip mode, Boot mode memory-expanded mode (EW0 mode) Parallel programmer Data flash is in planning. Rev. 1.00 Sep. 19, 2008 Page 1042 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.1 Memory Map This ROM is divided into the user ROM and the data flash. Figure 21.1 shows a block diagram of the flash memory. The user ROM and data flash are divided into multiple blocks. The user ROM can be programmed in user programming mode, on-board programming mode, or programmer mode. H'F00000 H'F00FFF H'F01000 H'F01FFF H'000000 Block A Data flash Block B Block 7: 64K H'00FFFF H'010000 Block 6: 64K H'01FFFF H'020000 User ROM Block 5: 64K H'02FFFF H'030000 Block 4: 64K H'03FFFF Notes: 1. To specify a block, use an even address in the block. 2. This is a block diagram in single-chip mode. Figure 21.1 Block Diagram of Flash Memory 21.1.1 Boot Mode Setting the mode pins to mode 3 and resetting the hardware shifts the flash memory into boot mode. In this mode, the embedded standard program is executed. Rev. 1.00 Sep. 19, 2008 Page 1043 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.2 Register Descriptions The flash memory has the following registers. * Flash memory control register 1 (FLMCR1) * Flash memory data block protect register (DFPR) * Flash memory status register (FLMSTR) Rev. 1.00 Sep. 19, 2008 Page 1044 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.2.1 Bit 7 6 Flash Memory Control Register 1 (FLMCR1) Bit Name CBIDB Initial Value 0 1 R/W R/W Description Reserved The initial value should not be changed. CPU Programming Mode Select Setting this bit to 0 (CPU programming mode) enables command acceptance. 0: CPU programming mode enabled 1: CPU programming mode disabled 5 4 3 2 1 0 0 0 0 1 0 R/W Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Flash Memory Software Command Enable Setting this bit to 1 (CPU programming mode) enables command acceptance. 0: Flash memory software commands disabled 1: Flash memory software commands enabled To set this bit to 1, be sure to write 0 and then write 1 in a row. FMCMDEN 0 Note: * To set the FMCMDEN bit to 1, write 0 to FMCMDEN and then write 1 in a row. Rev. 1.00 Sep. 19, 2008 Page 1045 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.2.2 Bit 7 6 5 4 3 2 1 0 Flash Memory Data Block Protect Register (DFPR) Bit Name FMDBPT0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W Description Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Data Flash E/W Protect* 0: Data flash E/W enabled 1: Data flash E/W disabled To set this bit to 1, be sure to write 0 and then write 1 in a row. Note: * To set the FMDBPT0 bit to 1, set the FMCMDEN bit to 1. Rev. 1.00 Sep. 19, 2008 Page 1046 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.2.3 Bit 7 6 5 Flash Memory Status Register (FLMSTR) Bit Name FMERSF* Initial Value 0 0 0 R/W R Description Reserved The initial value should not be changed. Reserved The initial value should not be changed. Erase or Blank Check Status Flag 0: Successfully completed 1: Ended with an error 4 FMERCF 0 R Erase Suspend Flag 0: Other than erase-suspended state 1: Erase-suspended state 3 FMPRSF* 0 R Program Status Flag 0: Successfully completed 1: Ended with an error 2 FMPRCF 0 R Program Suspend Flag 0: Other than program-suspended state 1: Program-suspended state 1 0 FMRDY 1 1 R Reserved The initial value should not be set. Flash Memory Ready/Busy Status 0: Busy (Interrupt processing or erasure is in progress) 1: Ready Note: * The FMERSF and FMPRSF bits are cleared to 0 by a clear status command. Rev. 1.00 Sep. 19, 2008 Page 1047 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.3 On-Board Programming Mode When the mode pins (MD0, MD1, and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. On-board programming mode has two operating modes: SCI boot mode by P27 and P26 settings, and user program mode. Table 21.3 shows the pin setting for each operating mode. Table 21.3 On-Board Programming Mode Setting Mode Setting SCI boot mode User programming mode EMLE 0 MD2 0 MD1 1 MD0 1 P27 0 P26 0 Mode 4, Mode 7 Rev. 1.00 Sep. 19, 2008 Page 1048 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.3.1 SCI Boot Mode SCI boot mode executes programming/erasing of the user MAT by means of the control command and program data transmitted from the externally connected host via the on-chip SCI_1. In SCI boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The serial communication mode is set to asynchronous mode. The system configuration in SCI boot mode is shown in figure 21.2. Interrupts are ignored in SCI boot mode. Configure the user system so that interrupts do not occur. This LSI P27 and P26 MD2 to MD0 Software for analyzing control commands (on-chip) Control command, program data RxD1 SCI_1 TxD1 On-chip RAM 00 011 Host Flash memory Programming tool and program data Response Figure 21.2 System Configuration in SCI Boot Mode Rev. 1.00 Sep. 19, 2008 Page 1049 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.3.2 User Programming Mode In the user programming mode, the flash memory can be programmed by the CPU through execution of software commands. In this mode, the user ROM can be programmed without using a ROM programmer with the microcomputer mounted on a system board. The programming and block erase commands should be executed only in each block area of the user program. The user programming mode provides the erase/write 0 mode (EW0 mode). Table 21.4 gives an overview of the EW0 mode specifications. Table 21.4 EW0 Mode Specifications Item Operating mode Description * * Single-chip mode Memory-expanded mode Area for storing the programming User ROM control program Area for executing the programming control program Programmable area Limitations on software commands Mode after programming or erasure CPU state during automatic programming or erasure Flash memory status detection The programming control program should be transferred to an area outside the flash memory (such as RAM) before execution*2 User ROM None Read status register mode Operating*1 * * Reading the FMPRSF and FMERSF bits in FLMSTR by a program. Executing a read status register command to read the SR7, SR5, and SR4 bits in the status register. Notes: 1. Make sure that no interrupt (except NMI) or DMA transfer is generated. 2. In the user programming mode, the programming control program should be executed in the on-chip RAM or an external area. Rev. 1.00 Sep. 19, 2008 Page 1050 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.3.3 EW0 Mode Setting the FMCMDEN bit in FLMCR1 to 1 shifts the flash memory into the user programming mode, in which commands can be accepted. Figure 21.3 shows how to set and clear the EW0 mode. Programming and erasure are controlled through software commands. The flash memory state after programming or erasure can be checked through FLMSTR or the status register. EW0 mode processing procedures Programming control program*4 Single-chip mode or memory-expanded mode Write 0 to the FMCMDEN bit and then write 1 to it (user programming mode enabled).*1 Clear CBIDB to 0. Transfer the programming control program to an area outside the flash memory. *4 Execute software commands. Set the FLSHE in SYSCR. Execute a read array command.*2 Set the FMCMDENT in FLMCR1 to 1 Set the CBIDB in FLMCR to 1 Write 1 to the CBIDB bit (CPU programming mode disabled). Jump to the programming control program transferred to an area outside the flash memory. (The subsequent processing should be done by the transferred programming control program.) Jump to a desired address in the flash memory. Notes: 1. 2. 3. To set the FMR01 bit to 1, write 0 to the bit and then write 1 to it in a row. Write to the FMR01 bit from an area outside the on-chip flash memory. After a read array command, disable the CPU programming mode. In the CPU programming mode, the PM10 and PM13 bits in PM1 become 1. Execute the programming control program in the on-chip RAM or an external area that can be used while the PM13 bit is 1. When using the 4-Mbyte mode while the PM13 bit is 1, do not use the area where the access space is expanded (H'40000 to H'BFFFF). Figure 21.3 Setting and Clearing EW0 Mode Rev. 1.00 Sep. 19, 2008 Page 1051 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.4 21.4.1 Notes on User Programming Mode Prohibited Interrupts (EW0 Mode) * The NMI and watchdog timer interrupts can be used because FLMCR1 is forcibly initialized when an interrupt is generated; specify the destination address of each interrupt routine in the fixed vector table. Flash memory programming is terminated when an NMI interrupt or a watchdog timer interrupt occurs. In this case, reexecute the programming program after the interrupt routine is completed. * The address-match interrupt cannot be used because the interrupt processing accesses data in the flash memory. 21.4.2 Access Method To set the FMCMDEN bit to 1, be sure to write 0 to the bit and then write 1 in a row. Make sure that no interrupt, EXDMAC transfer, DTC transfer, or DMA transfer is generated between writing 0 and 1. 21.4.3 Programming (EW0 Mode) If the power-supply voltage falls during programming of the block that stores the programming control program, the programming control program cannot be correctly modified and the flash memory may not be programmed after that. In this case, use the on-board programming mode or programmer mode instead. 21.4.4 Writing Commands or Data The address to write a command code or data should be a multiple of four (0, 4, 8, C, ...). 21.4.5 Software Standby Mode Before entering the stop mode, set the FMCMDEN bit to 0 (CPU programming mode disabled), disable the DMA transfer, and then make a transition to the software standby mode. Rev. 1.00 Sep. 19, 2008 Page 1052 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.5 Software Commands The following describes the software commands. A command or data should be read or written in 16-bit units at an even address in the user ROM or data flash area. When a command code is written, the upper eight bits (D15 to D8) are ignored. Table 21.5 List of Software Commands First Bus Cycle Software Command Read array Read status register Clear status register Program Block erase Block blank check Second Bus Cycle Third Bus Cycle Data Data Data (D15 to (D15 to (D15 to Mode Address D0) Mode Address D0) Mode Address D0) Write Write Write Write Write Write x x x WA0 x x H'xxFF H'xx70 H'xx50 H'xx41 H'xx20 Write Write WA0 BA BA WD0 H'xxD0 H'xxD0 Write WA1 WD1 Read x SRD H'Xx25 Write [Legend] SRD: Status register data (D7 to D0) WA0: Address to write the lower word (the address for the first bus cycle must be the same even address as that for the second bus cycle). WA1: Address to write the upper word WD0: Lower word of write data (16 bits) WD1: Upper word of write data (16 bits) BA: Highest address of the block (note that this should be an even address). x: A desired even address in program ROM1, program ROM2, or data flash. xx: Upper eight bits of command code (ignored) Rev. 1.00 Sep. 19, 2008 Page 1053 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.5.1 Read Array This command reads the flash memory. Write H'xxFF in the first bus cycle to shift the flash memory into the read array mode. Specify the target read address in the next bus cycle, and data is read from the address in 16-bit units. As the flash memory stays in the read array mode until another command is issued, multiple addresses can be read in sequence. 21.5.2 Read Status Register This command reads the status register. Write H'xx70 in the first bus cycle, and the status register can be read in the second bus cycle (refer to section 21.6, Status Register). Specify an even address in the program ROM or data flash to read the status register. Do not issue this command in the EW1 mode. 21.5.3 Clear Status Register This command clears the status register. Write H'xx50 in the first bus cycle, and the FMERSF and FMPRSF bits in FLMSTR are cleared to 0. 21.5.4 Program This command writes data to the flash memory in 2-word (4-byte) units. Write H'xx41 in the first bus cycle and write data to the target address in the second and third bus cycles; the flash memory starts automatic writing (programming and verifying data). The address value specified in the first bus cycle should be the same even address as that specified in the second bus cycle. Completion of automatic writing can be checked through the FMRDY bit in FLMSTR. The FMRDY bit is 0 (busy) during automatic writing and becomes 1 (ready) when writing is completed. Rev. 1.00 Sep. 19, 2008 Page 1054 of 1270 REJ09B0466-0100 Section 21 Flash Memory After automatic writing is completed, the result can be checked through the FMPRSF bit in FMRSTR (refer to section 21.7, Full Status Check). Once an address is programmed, no additional data can be written to the address. Figure 21.4 shows a flowchart of the program command processing. In the EW0 mode, the read status register mode is entered as soon as automatic writing starts, and the status register can be read. The SR7 bit in the status register becomes 0 when automatic writing starts and returns to 1 when writing is completed. In this case, the flash memory stays in the read status register mode until a read array command is issued. After automatic writing is completed, the result of writing can be checked by reading the status register. Start Write command code "H'xx41" to the target write address. Write data to the target write address. FMRDY = 1? NO YES Full status check End of programming Note: Write the command code and data to even addresses. Figure 21.4 Flowchart of Program Command Processing Rev. 1.00 Sep. 19, 2008 Page 1055 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.5.5 Block Erase Write H'xx20 in the first bus cycle and H'xxD0 to the highest address (an even address) of the target block in the second cycle; automatic erasure (erasing data and verifying the erased status) starts in the specified block. Completion of automatic erasure can be checked through the FMRDY bit in FLMSTR. The FMRDY bit is 0 (busy) during automatic erasure and becomes 1 (ready) when erasure is completed. After automatic erasure is completed, the result can be checked through the FMERSF bit in FLMSTR (refer to section 21.7, Full Status Check). Figure 21.5 shows a flowchart of the block erase command processing. In the EW0 mode, the read status register mode is entered as soon as automatic erasure starts, and the status register can be read. The SR7 bit in the status register becomes 0 when automatic erasure starts and returns to 1 when erasure is completed. In this case, the flash memory stays in the read status register mode until a read array command is issued. If an erase error occurs, repeat a sequence of the clear status register command -> block erase command at least three times until no erase error occurs. Rev. 1.00 Sep. 19, 2008 Page 1056 of 1270 REJ09B0466-0100 Section 21 Flash Memory Start Write command code "H'xx20h"*1 Write H'xxD0 to the highest address of the block. NO FMRDY = 1? YES Full status check *2*3 End of block erase Notes:1. Write the command code and data to even addresses. 2. See figure 21.6. 3. If an erase error occurs, repeat a sequence of the clear status register command -> block erase command at least three times until no erase error occurs. Figure 21.5 Flowchart of Block Erase Command Processing Rev. 1.00 Sep. 19, 2008 Page 1057 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.5.6 Block Blank Check This command checks if a block is blank (the erased state). Write H'xx25 in the first bus cycle and H'xxD0 to the highest address (an even address) of the target block in the second cycle; the check result will be stored in the FMERSF bit in FLMSTR. After the FMRDY bit in FLMSTR has become 1 (ready), read the FMERSF bit. Figure 21.6 shows a flowchart of the block blank check command processing. Start Write command code "H'xx25". Write "H'xxD0" to the highest address of the block. NO FMRDY = 1? YES NO FMERSF = 0? YES Blank Not blank Note: Write the command code and data to even addresses. Figure 21.6 Flowchart of Block Blank Check Command Processing Rev. 1.00 Sep. 19, 2008 Page 1058 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.6 Status Register The status register indicates the state of flash memory operation and whether erasure or programming has ended successfully or with an error. The status register contents can be read through the FMRDY, FMPRSF, and FMERSF bits in FLMSTR. Table 21.6 shows the status register. In the EW0 mode, the status register can be read with the following timing. * When a read status register command is issued and then an even address in the user ROM or data flash is read * When a program command, a block erase command, or a block blank check command is issued and then an even address in the user ROM or data flash is read before a read array command is issued Table 21.6 Status Register Bits in Status Register SR0 (D0) SR1 (D1) SR2 (D2) SR3 (D3) SR4 (D4) SR5 (D5) SR6 (D6) SR7 (D7) Bits in FMLSTR FMPRSF FMERSF FMRDY Status Status Name Reserved Reserved Reserved Reserved Programming status Erase status Reserved 0 Completed successfully Completed successfully 1 Ended with error Ended with error Ready 1 Value after Reset 0 0 Sequencer status Busy [Legend] D0 to D7: Data bus from which the bit is read when a read status register command is issued. Note: The FMERSF (SR5) and FMPRSF (SR4) bits are cleared to 0 by a clear status register command. When the FMERSF (SR5) or FMPRSF (SR4) bit is 1, the program, block erase, and block blank check commands are not accepted. Rev. 1.00 Sep. 19, 2008 Page 1059 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.6.1 Sequencer Status (FMRDY Bit) The sequencer status bit indicates the state of flash memory operation. Its value is 0 during execution of a program, block erase, or block blank check and 1 in other cases. 21.6.2 Erase Status (FMERSF Bit) Refer to section 21.7, Full Status Check. 21.6.3 Programming Status (FMPRSF Bit) Refer to section 21.7, Full Status Check. Rev. 1.00 Sep. 19, 2008 Page 1060 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.7 Full Status Check When an error occurs, the FMERSF or FMPRSF bit in FLMSTR becomes 1 to indicate occurrence of the error. Read these status bits (full status check) to check the operation results. Table 21.7 shows the errors and FLMSTR status and figure 21.7 shows a flowchart of full status check processing and corrective actions for each error. Table 21.7 Errors and Register Status State of FLMSTR (Status Register) FMERSF Bit (SR5) 1 FMPRSF Bit (SR4) 1 Error Command sequence error Error Conditions * * When a command is not issued correctly When an invalid value (a value other than H'xxD0 or H'xxFF) is written in the second bus cycle of a block erase command* When a block erase command is issued but the block is not erased correctly When a block blank check command is issued and the checked block is not blank When a program command is issued but automatic writing is not done correctly 1 0 Erase error * * 0 Note: * 1 Programming error * When H'xxFF is written in the second bus cycle of this command, the flash memory enters the read array mode and the command code written in the first bus cycle is ignored. Rev. 1.00 Sep. 19, 2008 Page 1061 of 1270 REJ09B0466-0100 Section 21 Flash Memory Full status check FMPRSF = 1 and FMERSF =1 ? YES Command sequence error . . . (1) Execute a clear status register command to clear the FMPRSF and FMERSF bits to 0 (successfully completed state). (2) Check if the command was input correctly, and execute it again. NO FMERSF = 0? NO Erase error . . . (1) Execute a clear stats register command to clear the FMERSF bit to 0 (successfully completed state). (2) Execute a block erase command. Repeat steps (1), (2), and (3) at least three times until no block erase error occurs. Note: If an error still occurs, the block cannot be used. YES FMPRSF = 0? NO Programming error . . . [During program execution] (1) Execute a clear stats register command to clear the FMPRSF bit to 0 (successfully completed state). (2) Execute a block erase command again. Note: If an error still occurs, the block cannot be used. YES End of full status check Note: When either the FMPRSF or FMERSF bit is 1 (ended with error), the program, block erase, and block blank check commands are not accepted. Execute a clear status register command and then execute a desired command again. Figure 21.7 Flowchart of Full Status Check Processing and Corrective Actions for Each Error Rev. 1.00 Sep. 19, 2008 Page 1062 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.8 Programmer Mode Along with the on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In the programmer mode, a generalpurpose PROM programmer can be used to freely write programs to the on-chip ROM. Program/erase is possible on the user MAT. The PROM programmer must support Renesas microcomputers with 256-Kbyte flash memory as a device type. A status-polling system is adopted for operation in automatic program, automatic erase, and status-read modes. In the status-read mode, details of the system's internal signals are output after execution of automatic programming or automatic erasure. In the PROM mode, provide a 12-MHz input-clock signal. Rev. 1.00 Sep. 19, 2008 Page 1063 of 1270 REJ09B0466-0100 Section 21 Flash Memory 21.9 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the on-chip SCI_I. The serial communication interface specification is shown below. (1) Status The boot program has three states. 1. Bit-Rate-Adjustment State In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rate-adjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. 2. Inquiry/Selection State In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The program transfers the libraries required for erasure to the RAM and erases the user MATs before the transition. 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. Rev. 1.00 Sep. 19, 2008 Page 1064 of 1270 REJ09B0466-0100 Section 21 Flash Memory These boot program states are shown in figure 21.8. Reset Bit-rate-adjustment state Inquiry/response wait Transition to programming/erasing Response Inquiry Operations for inquiry and selection Operations for response Operations for erasing user MATs Programming/erasing wait Programming Operations for programming Erasing Operations for erasing Checking Operations for checking Figure 21.8 Boot Program States Rev. 1.00 Sep. 19, 2008 Page 1065 of 1270 REJ09B0466-0100 Section 21 Flash Memory (2) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 21.9. Host H'00 (30 times maximum) Boot Program Measuring the 1-bit length H'00 (Completion of adjustment) H'55 H'E6 (Boot response) H'FF (error) Figure 21.9 Bit-Rate-Adjustment Sequence Rev. 1.00 Sep. 19, 2008 Page 1066 of 1270 REJ09B0466-0100 Section 21 Flash Memory (3) Communications Protocol After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These commands and responses are comprised of a single byte. These are consists of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The amount of programming data is not included under this heading because it is determined in another command. 3. Error response The error response is a response to inquiries. It consists of an error response and an error code and comes two bytes. 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. 5. Memory read response This response consists of 4 bytes of data. Rev. 1.00 Sep. 19, 2008 Page 1067 of 1270 REJ09B0466-0100 Section 21 Flash Memory One-byte command or one-byte response n-byte Command or n-byte response Command or response Data Size Command or response Checksum Error response Error code Error response 128-byte programming Address Command Data (n bytes) Checksum Memory read response Size Response Data Checksum Figure 21.10 Communication Protocol Format * Command (one byte): Commands including inquiries, selection, programming, erasing, and checking * Response (one byte): Response to an inquiry * Size (one byte): The amount of data for transmission excluding the command, data, and checksum * Data (n bytes): Detailed data of a command or response * Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. * Error response (one byte): Error response to a command * Error code (one byte): Type of the error * Address (four bytes): Address for programming * Data (n bytes): Data to be programmed (the size is indicated in the response to the programming unit inquiry.) * Size (four bytes): Four-byte response to a memory read Rev. 1.00 Sep. 19, 2008 Page 1068 of 1270 REJ09B0466-0100 Section 21 Flash Memory (4) Inquiry/Selection State The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Inquiry and selection commands are listed below. Table 21.8 Inquiry and Selection Commands Command H'20 H'10 H'21 H'11 H'22 Command Name Supported Device Inquiry Device Selection Clock Mode Inquiry Clock Mode Selection Multiplication Ratio Inquiry Description Inquiry regarding device codes and product name Selection of device code Inquiry regarding numbers of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of frequencymultiplied clock types, the number of multiplication ratios, and the values of each multiple Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks Inquiry regarding the number of user MATs and the start and last addresses of each MAT Inquiry regarding the number of blocks and the start and last addresses of each block Inquiry regarding the unit of programming data Selection of new bit rate Erasing of user MAT and entry to programming/erasing state Inquiry regarding the operated status of the boot program H'23 H'25 H'26 H'27 H'3F H'40 H'4F Operating Clock Frequency Inquiry User MAT Information Inquiry Block for Erasing Information Inquiry Programming Unit Inquiry New Bit Rate Selection Transition to Programming/Erasing State Boot Program Status Inquiry The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. These commands will certainly be needed. When two or more selection commands are sent at once, the last command will be valid. Rev. 1.00 Sep. 19, 2008 Page 1069 of 1270 REJ09B0466-0100 Section 21 Flash Memory All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition command (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid even after the boot program has received the programming/erasing transition command (H'40). (a) Supported Device Inquiry The boot program will return the device codes of supported devices and the product name in response to the supported device inquiry. Command H'20 * Command, H'20, (one byte): Inquiry regarding supported devices Response H'30 Number of characters *** SUM Size Number of devices Product name Device code * Response, H'30, (one byte): Response to the supported device inquiry * Size (one byte): Number of bytes to be transmitted, excluding the command, size, and checksum, that is, the amount of data contributes by the number of devices, characters, device codes and product names * Number of devices (one byte): The number of device types supported by the boot program * Number of characters (one byte): The number of characters in the device codes and boot program's name * Device code (four bytes): ASCII code of the supporting product * Product name (n bytes): Type name of the boot program in ASCII-coded characters * SUM (one byte): Checksum The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. Rev. 1.00 Sep. 19, 2008 Page 1070 of 1270 REJ09B0466-0100 Section 21 Flash Memory (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM * Command, H'10, (one byte): Device selection * Size (one byte): Amount of device-code data This is fixed at 2. * Device code (four bytes): Device code (ASCII code) returned in response to the supported device inquiry * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR * Error response, H'90, (one byte): Error response to the device selection command ERROR: (one byte): Error code H'11: Checksum error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21 * Command, H'21, (one byte): Inquiry regarding clock mode Response H'31 Size Mode *** SUM * * * * Response, H'31, (one byte): Response to the clock-mode inquiry Size (one byte): Amount of data that represents modes Mode (one byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.) SUM (one byte): Checksum Rev. 1.00 Sep. 19, 2008 Page 1071 of 1270 REJ09B0466-0100 Section 21 Flash Memory (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size Mode SUM * Command, H'11, (one byte): Selection of clock mode * Size (one byte): Amount of data that represents the modes This is fixed at 1. * Mode (one byte): A clock mode returned in reply to the supported clock mode inquiry. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to the clock mode selection command ACK will be returned when the clock mode matches. Error Response H'91 ERROR * Error response, H'91, (one byte): Error response to the clock mode selection command * ERROR, (one byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match. Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must be selected using these respective values. Rev. 1.00 Sep. 19, 2008 Page 1072 of 1270 REJ09B0466-0100 Section 21 Flash Memory (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios. Command H'22 * Command, H'22, (one byte): Inquiry regarding multiplication ratio Response H'32 Number of multiplication ratios *** SUM Size Multiplication ratio Number of types *** * Response, H'32, (one byte): Response to the multiplication ratio inquiry * Size (one byte): The amount of data that represents the number of clock types and multiplication ratios and the multiplication ratios * Number of types (one byte): The number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be H'02.) * Number of multiplication ratios (one byte): The number of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) * Multiplication ratio (one byte) Multiplication ratio: The value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04.) Division ratio: The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types. * SUM (one byte): Checksum Rev. 1.00 Sep. 19, 2008 Page 1073 of 1270 REJ09B0466-0100 Section 21 Flash Memory (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 * Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Minimum value of operating Maximum value of operating clock clock frequency frequency *** SUM * Response, H'33, (one byte): Response to operating clock frequency inquiry * Size (one byte): The number of bytes that represents the minimum values, maximum values, and the number of frequencies. * Number of operating clock frequencies (one byte): The number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02.) * Minimum value of operating clock frequency (two bytes): The minimum value of the multiplied or divided clock frequency. The minimum and maximum values represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100 (e.g. when the value is 64 MHz, it will be 6400 and H'1900). * Maximum value (two bytes): Maximum value of the multiplied or divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequency. * SUM (one byte): Checksum Rev. 1.00 Sep. 19, 2008 Page 1074 of 1270 REJ09B0466-0100 Section 21 Flash Memory (g) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 * Command, H'25, (one byte): Inquiry regarding user MAT information Response H'35 *** SUM Size Number of areas Area-last address Area-start address * Response, H'35, (one byte): Response to the user MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start address, and area-last address * Number of areas (one byte): The number of consecutive user MAT areas When the user MAT areas are consecutive, the number of areas returned is H'01. * Area-start address (four bytes): Start address of the area * Area-last address (four byte): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum Rev. 1.00 Sep. 19, 2008 Page 1075 of 1270 REJ09B0466-0100 Section 21 Flash Memory (h) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 * Command, H'26, (one byte): Inquiry regarding erased block information Response H'36 *** SUM Size Number of blocks Block-last address Block-start address * Response, H'36, (one byte): Response to the number of erased blocks and addresses * Size (two bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. * Number of blocks (one byte): The number of erased blocks * Block-start address (four bytes): Start address of a block * Block-last Address (four bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are blocks. * SUM (one byte): Checksum (i) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27 * Command, H'27, (one byte): Inquiry regarding programming unit Response H'37 Size Programming unit SUM * Response, H'37, (one byte): Response to programming unit inquiry * Size (one byte): The number of bytes that indicate the programming unit, which is fixed to 2 * Programming unit (two bytes): A unit for programming This is the unit for reception of programming data. * SUM (one byte): Checksum Rev. 1.00 Sep. 19, 2008 Page 1076 of 1270 REJ09B0466-0100 Section 21 Flash Memory (j) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Number of multiplication ratios SUM Size Multiplication ratio 1 Bit rate Multiplication ratio 2 Input frequency * Command, H'3F, (one byte): Selection of new bit rate * Size (one byte): The number of bytes that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratio * Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19,200 bps, the bit rate is H'00C0, which is 192.) * Input frequency (two bytes): Frequency of the clock input to the boot program This is valid to the hundredths place and represents the value in MHz multiplied by 100 (e.g. when the value is 64 MHz, the input frequency is H'1900 (= 6400)). * Number of multiplication ratios (one byte): The number of multiplication ratios to which the device can be set. * Multiplication ratio 1 (one byte): The value of multiplication or division ratios for the main operating frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE. H'FE = [-2]) * Multiplication ratio 2 (one byte): The value of multiplication or division ratios for the peripheral frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) (Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = [-2]) Rev. 1.00 Sep. 19, 2008 Page 1077 of 1270 REJ09B0466-0100 Section 21 Flash Memory * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error Response H'BF ERROR * Error response, H'BF, (one byte): Error response to selection of new bit rate * ERROR: (one byte): Error code H'11: Checksum error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Multiplication-ratio error The ratio does not match an available ratio. H'27: Operating frequency error The frequency is not within the specified range. Rev. 1.00 Sep. 19, 2008 Page 1078 of 1270 REJ09B0466-0100 Section 21 Flash Memory (5) Received Data Check The methods for checking of received data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2. Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches a multiplication or division ratio for the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 3. Operating frequency error The operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below. Operating frequency = Input frequency x Multiplication ratio, or Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency () and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is 4% or more, a bit rate error is generated. The error is calculated using the following expression: Error (%) = {[ x 106 (N + 1) x B x 64 x 2(2xn - 1) ] - 1} x 100 Rev. 1.00 Sep. 19, 2008 Page 1079 of 1270 REJ09B0466-0100 Section 21 Flash Memory When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 * Confirmation, H'06, (one byte): Confirmation of a new bit rate Response H'06 * Response, H'06, (one byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 21.11. Host Setting a new bit rate Waiting for one-bit period at the specified bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) Boot program Setting a new bit rate Figure 21.11 New Bit-Rate Selection Sequence Rev. 1.00 Sep. 19, 2008 Page 1080 of 1270 REJ09B0466-0100 Section 21 Flash Memory (6) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs. On completion of this erasure, ACK will be returned and the programming/erasing state will be entered. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. These procedures should be carried out before sending of the programming selection command or program data. Command H'40 * Command, H'40, (one byte): Transition to programming/erasing state Response H'06 * Response, H'06, (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MAT has been erased by the transferred erasing program. Error Response H'C0 H'51 * Error code, H'51, (one byte): Erasing error An error occurred and erasure was not completed. Rev. 1.00 Sep. 19, 2008 Page 1081 of 1270 REJ09B0466-0100 Section 21 Flash Memory (7) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples. Error Response H'80 H'xx * Error response, H'80, (one byte): Command error * Command, H'xx, (one byte): Received command (8) Command Order The order for commands in the inquiry/selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. 7. After selection of the device and clock mode, the information of the user MAT should be made to inquire about the user MATs information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state. Rev. 1.00 Sep. 19, 2008 Page 1082 of 1270 REJ09B0466-0100 Section 21 Flash Memory (9) Programming/Erasing State A programming selection command makes the boot program select the programming method, an 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/erasing commands are listed below. Table 21.9 Programming/Erasing Commands Command H'43 H'50 H'48 H'58 H'52 H'4B H'4D H'4F Command Name User MAT programming selection 128-byte programming Erasing selection Block erasing Memory read User MAT sum check User MAT blank check Boot program status inquiry Description Transfers the user MAT programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the checksum of the user MAT Checks whether the contents of the user MAT are blank Inquires into the boot program's status * Programming Programming is executed by a programming-selection command and a 128-byte programming command. Firstly, the host should send the programming-selection command and select the programming method and programming MATs. The programming selection command is user MAT programming selection, regardless of the area and method for programming. After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. Rev. 1.00 Sep. 19, 2008 Page 1083 of 1270 REJ09B0466-0100 Section 21 Flash Memory The sequence for programming-selection and 128-byte programming commands is shown in figure 21.12. Host Programming selection (H'42, H'43, H'44) Boot program Transfer of the programming program ACK 128-byte programming (address, data) Repeat ACK 128-byte programming (H'FFFFFFFF) ACK Programming Figure 21.12 Programming Sequence (a) User-program programming selection The boot program will transfer a program for programming. The data is programmed to the user MATs by the transferred program for programming. Command H'43 * Command, H'43, (one byte): User-program programming selection Response H'06 * Response, H'06, (one byte): Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK. Rev. 1.00 Sep. 19, 2008 Page 1084 of 1270 REJ09B0466-0100 Section 21 Flash Memory (b) 128-byte programming The boot program will use the programming program transferred by the programming selection to program the user MATs in response to 128-byte programming. Command H'50 Data *** SUM Address *** * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00: H'01000000) * Programming Data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum Error H'2A: Address error The address is not within the specified MAT. H'53: Programming error A programming error has occurred and programming cannot be continued. Rev. 1.00 Sep. 19, 2008 Page 1085 of 1270 REJ09B0466-0100 Section 21 Flash Memory The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower byte of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing. Command H'50 Address SUM * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error Response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming and programming cannot be continued. Rev. 1.00 Sep. 19, 2008 Page 1086 of 1270 REJ09B0466-0100 Section 21 Flash Memory (10) Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block-erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequences of the issuing of erasure selection commands and the erasure of data are shown in figure 21.13. Host Preparation for erasure (H'48) Transfer of erasure program ACK Erasure (Erasure block number) ACK Erasure (H'FF) ACK Boot program Repeat Erasure Figure 21.13 Erasure Sequence Rev. 1.00 Sep. 19, 2008 Page 1087 of 1270 REJ09B0466-0100 Section 21 Flash Memory (a) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program. Command H'48 * Command, H'48, (one byte): Erasure selection Response H'06 * Response, H'06, (one byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK. (b) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM * Command, H'58, (one byte): Erasure * Size (one byte): The number of bytes that represents the erasure block number This is fixed to 1. * Block number (one byte): Number of the block to be erased * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to Erasure After erasure has been completed, the boot program will return ACK. Error Response H'D8 ERROR * Error Response, H'D8, (one byte): Response to Erasure * ERROR (one byte): Error code H'11: Checksum error H'29: Block number error Block number is incorrect. H'51: Erasure error An error has occurred during erasure. Rev. 1.00 Sep. 19, 2008 Page 1088 of 1270 REJ09B0466-0100 Section 22 Boundary Scan (JTAG) Section 22 Boundary Scan (JTAG) For details, contact your Renesas Technology sales agency. Rev. 1.00 Sep. 19, 2008 Page 1089 of 1270 REJ09B0466-0100 Section 22 Boundary Scan (JTAG) Rev. 1.00 Sep. 19, 2008 Page 1090 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator Section 23 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock () and internal clocks. The clock pulse generator consists of an oscillator circuit, a system-clock PLL circuit and a divider. Figure 23.1 shows a block diagram of the clock pulse generator. PLLCR STC0, STC1 EXTAL Oscillator XTAL System-clock PLL circuit (x1, 2) Divider Legend: PLLCR: PLL control register System clock to pin Internal clock to peripheral modules Figure 23.1 Block Diagram of Clock Pulse Generator The frequency of the system clock from the oscillator can be changed by means of the systemclock PLL circuit and divider. Frequency changes are made by software by means of settings in the PLL control register (PLLCR). Rev. 1.00 Sep. 19, 2008 Page 1091 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator 23.1 Register Descriptions The clock pulse generator has the following registers. * System clock control register (SCKCR) * PLL control register (PLLCR) 23.1.1 System Clock Control Register (SCKCR) SCKCR controls clock output and selects operation when the PLLCR register setting is changed. Bit 7 Bit Name PSTOP Initial Value 0 R/W R/W Description Clock Output Disable Controls output. Normal Operation 0: output 1: Fixed high Sleep Mode 0: output 1: Fixed high Software Standby Mode 0: Fixed high 1: Fixed high Hardware Standby Mode 0: High impedance 1: High impedance All module clock stop mode 0: output 1: Fixed high 6 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 1.00 Sep. 19, 2008 Page 1092 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator Bit 5 Bit Name SDPSTP* Initial Value 0 R/W R/W Description SDRAM Output Disable Controls SDRAM. 0: SDRM output. 1: Can be used as PH1/CS5/RAS5. When the SDRAM output is selected, the pin functions as follows in each power-down mode. Normal operation: SDRAM output Sleep mode: SDRAM output Software standby mode: Fixed at a low level Hardware standby mode: High-impedance state All module clock stop mode: SDRAM output 4 -- 0 -- Reserved This bit is always read as 0 and cannot be modified. 3 STCS 0 R/W Frequency Multiplication Factor Switching Mode Select Selects the operation when the PLLCR register setting is changed. 0: Specified multiplication factor is valid after transition to software standby mode. 1: Specified multiplication factor is valid immediately after STC1 and STC0 bits are rewritten. 2 1 0 Note: -- 0 0 0 R/W R/W R/W Reserved These bits are always read as 0 and cannot be modified. * The H8S/2426 group and H8S/2424 group do not have this bit. The pin always functions as an I/O port regardless of this bit setting. Rev. 1.00 Sep. 19, 2008 Page 1093 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator 23.1.2 PLL Control Register (PLLCR) PLLCR sets the frequency multiplication factor used by the system-clock PLL circuit. Care must be taken when writing to this register. For details, see section 23.3, System-Clock PLL Circuit and Divider. Bit 7 to 4 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 3 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 2 -- 0 -- Reserved This bit is always read as 0 and cannot be modified. 1 0 STC1 STC0 0 0 R/W R/W Frequency Multiplication Factor for SystemClock PLL Circuit and System Clock Divider Setting The STC bits specify the frequency multiplication factor and dividing ratio with respect to the oscillator frequency. 00: x 1 01: x 2 10: Setting prohibited 11: 1/2 Rev. 1.00 Sep. 19, 2008 Page 1094 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator 23.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 23.2.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in the example in figure 23.2. Select the damping resistance Rd according to table 23.1. An AT-cut parallel-resonance type should be used. When a crystal resonator is used, the range of its frequencies is from 8 to 20 MHz. Figure 23.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 23.2. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 23.2 Connection of Crystal Resonator (Example) Table 23.1 Damping Resistance Value Frequency (MHz) Rd () 8 200 12 0 16 0 20 0 CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 23.3 Crystal Resonator Equivalent Circuit Rev. 1.00 Sep. 19, 2008 Page 1095 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator Table 23.2 Crystal Resonator Characteristics Frequency (MHz) RS max () C0 max (pF) 8 80 7 12 60 7 16 50 7 20 40 7 23.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 23.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode. Table 23.3 shows the input conditions for the external clock. When an external clock is used, the range of its frequencies is from 8 to 20 MHz. EXTAL XTAL Open state External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Counter clock input at XTAL pin Figure 23.4 Connection of External Clock Input (Examples) Rev. 1.00 Sep. 19, 2008 Page 1096 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator Table 23.3 External Clock Input Conditions VCC = 3.0 V to 3.6 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width Clock high pulse width Symbol tEXL tEXH tEXr tEXf tCL tCH Min 20 20 -- -- 0.4 0.4 Max -- -- 5 5 0.6 0.6 Unit ns ns ns ns tcyc tcyc Test Conditions Figure 23.5 tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 23.5 External Clock Input Timing Rev. 1.00 Sep. 19, 2008 Page 1097 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator 23.3 System-Clock PLL Circuit and Divider The system-clock PLL circuit and divider have the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or dividing by 2. The system clock frequency is set with the STC1 and STC0 bits in PLLCR. The phase of the rising edge of the internal clock is controlled so as to match that of the rising edge of the EXTAL pin. When the frequency is changed with the system-clock PLL circuit and divider, operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0, the setting of the changed frequency becomes valid after a transition to software standby mode. The transition time count is performed in accordance with the setting of bits STS3 to STS0 in SBYCR. For details on SBYCR, see section 24.1.1, Standby Control Register (SBYCR). 1. The initial PLL circuit multiplication factor is 1. 2. A value is set in bits STS3 to STS0 to give the specified transition time. 3. The target value is set in bits STC1 and STC0, and a transition is made to software standby mode. 4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. 5. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS3 to STS0. 6. After the set transition time has elapsed, this LSI resumes operation using the target multiplication factor. When STCS = 1, a change to the frequency setting becomes effective a maximum of four cycles after the setting is changed. If the clock frequency is changed during access to an external address space, correct operation cannot be guaranteed. Therefore, be sure to store instructions that change the STC1 and STC0 bits and other instructions to be executed within a maximum of four cycles after the change to the frequency setting in on-chip ROM or on-chip RAM, so that instructions do not access an external address space before the frequency clock is switched over. Rev. 1.00 Sep. 19, 2008 Page 1098 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator 23.4 23.4.1 Usage Notes Notes on Clock Pulse Generator 1. The following points should be noted since the frequency of changes according to the settings of PLLCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of the Electrical Characteristics. In other words, must be set to a value between 8 MHz (minimum) and 33 MHz (maximum). The setting of must not be less than 8 MHz or greater than 33 MHz. 2. All the on-chip peripheral modules operate on the . Therefore, note that the time processing of modules such as a timer and SCI differ before and after changing the clock division ratio. In addition, wait time for clearing software standby mode differs by changing the clock division ratio. See the description, Setting Oscillation Stabilization Time after Clearing Software Standby Mode in section 24.2.3, Software Standby Mode, for details. 3. Note that the frequency of will be changed when setting PLLCR while executing the external bus cycle with the write-data-buffer function. 23.4.2 Notes on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the parameters for the oscillation circuit will depend on the floating capacitance of the resonator and the user board, the parameters should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin. Rev. 1.00 Sep. 19, 2008 Page 1099 of 1270 REJ09B0466-0100 Section 23 Clock Pulse Generator 23.4.3 Notes on Board Design When using the crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillation circuit to prevent induction from interfering with correct oscillation. See figure 23.6. Prohibited Signal A Signal B This LSI CL2 XTAL EXTAL CL1 Figure 23.6 Note on Board Design for Oscillation Circuit Figure 23.7 shows the external circuitry recommended for the PLL circuit. Separate PLLVcc and PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. PLLVCC CPB: 0.1 F* PLLVSS VCC CB: 0.1 F* VSS Note: * CB and CPB are laminated ceramic capacitors. Figure 23.7 Recommended External Circuitry for PLL Circuit Rev. 1.00 Sep. 19, 2008 Page 1100 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes Section 24 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power consumption is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on. This LSI's operating modes are high-speed mode and six power down modes: * * * * * * Clock division mode Sleep mode Module stop function All module clocks stop mode Software standby mode Hardware standby mode Sleep mode is a CPU state, clock division mode is an on-chip peripheral function (including bus masters and the CPU) state, and module stop function is an on-chip peripheral function (including bus masters other than the CPU) state. A combination of these modes can be set. After a reset, this LSI is in high-speed mode. Table 24.1 shows the internal states of this LSI in each mode. Figure 24.1 shows the mode transition diagram. Rev. 1.00 Sep. 19, 2008 Page 1101 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes Table 24.1 Operating Modes and Internal states of the LSI High Speed Mode Operating Operating Clock Division Mode Operating Operating Sleep Mode Operating Stopped Retained Operating Operating Operating Operating Operating Module Stop Function Operating Operating All Module Software Clocks Stop Standby Mode Mode Operating Stopped Stopped Stopped Retained Operating Hardware Standby Mode Stopped Stopped Undefined Stopped Operating State Clock pulse generator CPU Instruction execution Register External interrupts NMI IRQ0 to 1 15* Peripheral WDT functions TMR Operating Operating Operating Operating Operating Operating Operating Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped* (Reset/ retained) 4 Operating Operating/ Stopped 2 (Retained)* Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped* (Reset/ retained) 5 4 Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped (Retained) Stopped* (Reset/ retained) 5 4 Stopped (Reset) Stopped (Reset) Stopped (Reset) Stopped (Reset) Stopped (Reset) Stopped (Reset) Stopped (Reset) Stopped (Reset) Stopped (Reset) Stopped (Reset) 5 EXDMAC* Operating DMAC DTC TPU PPG D/A A/D SCI Operating Operating Operating Operating Operating Operating Operating 3 Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating IIC2 Operating Operating Operating Stopped* * Stopped* * (Reset/ (Reset/ retained) retained) Stopped (Reset) Stopped (Retained) Operating Stopped (Reset) Operating Retained 4 4 Stopped* * Stopped (Reset/ (Reset) retained) Stopped (Reset) Retained Retained Stopped (Reset) Retained High impedance 4 SSU RAM I/O Operating Operating Operating Operating Operating Operating Operating Operating Operating Rev. 1.00 Sep. 19, 2008 Page 1102 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes Notes: 1. 2. 3. 4. 5. Stopped (Retained) in the table means that internal register values are retained and internal operations are suspended. Stopped (Reset) in the table means that internal register values and internal states are initialized. In module stop function, only modules for which a stop setting has been made are stopped (reset or retained). IRQ8 to IRQ15 are not supported by the H8S/2424 group. The active or stopped state can be selected by means of the MSTP0 bit in MSTPCR. Not supported by the H8S/2424 group. TDR, SSR, and RDR are stopped (reset) and other registers are stopped (retained). BC2 to BC0 are stopped (reset) and other registers are stopped (retained). Rev. 1.00 Sep. 19, 2008 Page 1103 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes STBY pin = low Reset state Hardware standby mode STBY pin = high RES pin = low RES pin = high SSBY = 0 SLEEP instruction High-speed mode (Internal clock is PLL circuit output clock) Sleep mode MSTPCR = H'FFFF (H'FFFE), EXMSTPCR = H'FFFF, SSBY = 0 All module-clocks-stop mode SSBY = 1 Software standby mode Any interrupt SLEEP instruction STC1, STC0 11 STC1, STC0 = 11 Interrupt*1 SLEEP instruction Clock division mode External interrupt*2 Program execution state : Transition after exception handling Notes: * * Program-halted state : Power- down mode From any state, a transition to hardware standby mode occurs when STBY is driven low. From any state except hardware standby mode, a transition to the reset state occurs when RES is driven low. 1. NMI, IRQ0 to IRQ15*3, 8-bit timer interrupts, watchdog timer interrupts. (8-bit timer interrupts are valid when MSTP0 = 0.) 2. NMI, IRQ0 to IRQ15*3 (IRQ0 to IRQ15*3 are valid when the corresponding bit in SSIER is 1.) 3. IRQ8 to IRQ15 are not supported by the H8S/2424 group. Figure 24.1 Mode Transitions Rev. 1.00 Sep. 19, 2008 Page 1104 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes 24.1 Register Descriptions The registers relating to the power-down mode are shown below. For details on the PLL control register (PLLCR), see section 23.1.2, PLL Control Register (PLLCR). * * * * * * * * PLL control register (PLLCR) Standby control register (SBYCR) Module stop control register H (MSTPCRH) Module stop control register L (MSTPCRL) Extension module stop control register H (EXMSTPCRH) Extension module stop control register L (EXMSTPCRL) RAM module stop control register H (RMMSTPCRH) RAM module stop control register L (RMMSTPCRL) Standby Control Register (SBYCR) 24.1.1 SBYCR performs software standby mode control. Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode after the SLEEP instruction is executed 1: Shifts to software standby mode after the SLEEP instruction is executed This bit does not change from 1 when clearing the software standby mode by using external interrupts and shifting to normal operation. This bit should be written 0 when clearing. 6 OPE 1 R/W Output Port Enable Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS) is retained or set to the high-impedance state in software standby mode. 0: In software standby mode, address bus and bus control signals are high-impedance 1: In software standby mode, address bus and bus control signals retain output state Rev. 1.00 Sep. 19, 2008 Page 1105 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes Bit 5 Bit Name Initial Value 0 R/W Description Reserved This bit is always read as 0. The initial value should not be changed. 4 0 Reserved This bit is always read as 0. The write value should always be 0. 3 2 1 0 STS3 STS2 STS1 STS0 1 1 1 1 R/W R/W R/W R/W Standby Timer Select 3 to 0 These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, see table 24.2 and make a selection according to the operating frequency so that the standby time is at least the oscillation stabilization time. With an external clock, a PLL circuit stabilization time is necessary. See table 24.2 to set the standby time. When DRAM is used and self-refreshing in the software standby state is selected, note that the DRAM's tRAS (self-refresh RAS pulse width) specification must be satisfied. 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: Setting prohibited 0100: Setting prohibited 0101: Standby time = 64 states 0110: Standby time = 512 states 0111: Standby time = 1024 states 1000: Standby time = 2048 states 1001: Standby time = 4096 states 1010: Standby time = 16384 states 1011: Standby time = 32768 states 1100: Standby time = 65536 states 1101: Standby time = 131072 states 1110: Standby time = 262144 states 1111: Standby time = 524288 states Rev. 1.00 Sep. 19, 2008 Page 1106 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes 24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop mode control. Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode. * MSTPCRH Bit 15 Bit Name ACSE Initial Value 0 R/W R/W Module All Module Clocks Stop Mode Enable Enables or disables all module clocks stop mode, in which, when the CPU executes a SLEEP instruction after module stop mode has been set for all the on-chip peripheral functions controlled by MSTPCR or the on-chip peripheral functions except the TMR. 0: All module clocks stop mode disabled 1: All module clocks stop mode enabled 14 13 12 11 10 9 8 Note: MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 * 0 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W EXDMA controller (EXDMAC)* DMA controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit 0 (TPU_0) Programmable pulse generator (PPG) 16-bit timer pulse unit 1 (TPU_1) D/A converter (channels 2 and 3) Not supported by the H8S/2424 group. Rev. 1.00 Sep. 19, 2008 Page 1107 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes * MSTPCRL Bit 7 6 5 4 3 2 1 0 Bit Name MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Module A/D converter unit 1 A/D converter unit 0 Serial communication interface 4 (SCI_4) Serial communication interface 3 (SCI_3) Serial communication interface 2 (SCI_2) Serial communication interface 1 (SCI_1) Serial communication interface 0 (SCI_0) 8-bit timer (TMR) 24.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) EXMSTPCR performs all module clocks stop mode control with MSTPCR. When entering all module clocks stop mode, set EXMSTPCR to H'FFFF. * EXMSTPCRH Bit 15 14 13 12 11 10 9 8 Bit Name MSTP31 MSTP30 MSTP29 MSTP28 MSTP27 MSTP26 MSTP25 MSTP24 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Module Rev. 1.00 Sep. 19, 2008 Page 1108 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes * EXMSTPCRL Bit 7 6 5 4 3 2 Bit Name MSTP23 MSTP22 MSTP21 MSTP20 MSTP19 MSTP18 Initial Value 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W Module Synchronous serial communication unit (SSU) I2C bus interface 2_3 (IIC2_3) I2C bus interface 2_2 (IIC2_2) I2C bus interface 2_1 (IIC2_1) I2C bus interface 2_0 (IIC2_0) Reserved This bit can be read or written to. The write value should always be 1. 1 MSTP17 1 R/W Reserved This bit can be read or written to. The write value should always be 1. 0 MSTP16 1 R/W 24.1.4 RAM Module Stop Control Registers H and L (RMMSTPCRH, RMMSTPCRL) Setting bits MSTP32 to MSTP39 to 1 stops the corresponding on-chip RAM area. During access to an on-chip RAM area, do not set bits MSTP32 to MSTP39 corresponding to the area to 1. While bit RAME in SYSCR is 1, and bits MSTP32 to MSTP39 are 1, do not access the corresponding RAM area. * RMMSTPCRH Bit 15 14 13 12 11 10 9 8 Bit Name MSTP47 MSTP46 MSTP45 MSTP44 MSTP43 MSTP42 MSTP41 MSTP40 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Module Rev. 1.00 Sep. 19, 2008 Page 1109 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes * RMMSTPCRL Bit 7 6 5 4 3 2 1 0 Note: Bit Name MSTP39 MSTP38 MSTP37 MSTP36 MSTP35 MSTP34 MSTP33 MSTP32 * Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Module On-chip RAM_7 (H'FEC000 to H'FEDFFF)* On-chip RAM_6 (H'FEE000 to H'FEFFFF)* On-chip RAM_5 (H'FF0000 to H'FF1FFF) On-chip RAM_4 (H'FF2000 to H'FF3FFF) On-chip RAM_3 (H'FF4000 to H'FF5FFF) On-chip RAM_2 (H'FF6000 to H'FF7FFF) On-chip RAM_1 (H'FF8000 to H'FF9FFF) On-chip RAM_0 (H'FFA000 to H'FFBFFF) Not supported by the H8S/24268R, H8S/24268, H8S/24265R, H8S/24265, H8S/24261R, H8S/24261, H8S/24248, H8S/24245, and H8S/24241 Groups. Although these bits are readable/writable, only 1 should be written to. 24.2 24.2.1 Operation Clock Division Mode When bits STC1 and STC0 in PLLCR are set to 11, a transition is made to clock division mode, and the system clock frequency is divided with respect to the oscillator frequency. Clock division mode is cancelled by clearing bits STC1 and STC0 to a value other than 11. The timings of transition and clearing depend on the STCS bit setting in SCKCR. For the operation at transition and clearing, see section 23.3, System-Clock PLL Circuit and Divider. If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored. If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters software standby mode. When software standby mode is cleared by an external or internal interrupt, clock division mode is restored. When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The same applies to a reset caused by watchdog timer overflow. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 1.00 Sep. 19, 2008 Page 1110 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes 24.2.2 (1) Sleep Mode Transition to Sleep Mode When the SLEEP instruction is executed while the SSBY bit is 0 in SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral functions do not stop. (2) Exiting Sleep Mode Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins. * Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. * Exiting Sleep Mode by RES Pin: Setting the RES pin level low selects the reset state. After the stipulated reset input duration, driving the RES pin high starts the CPU performing reset exception processing. * Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven low, a transition is made to hardware standby mode. Rev. 1.00 Sep. 19, 2008 Page 1111 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes 24.2.3 (1) Software Standby Mode Transition to Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip peripheral functions other than the SCI, IIC, and SSU, and the states of I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. (2) Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ15*), or by means of the RES pin or STBY pin. Setting the SSI bit in SSIER to 1 enables IRQ0 to IRQ15* to be used as software standby mode clearing sources. * Clearing with an Interrupt: When an NMI or IRQ0 to IRQ15* interrupt request signal is input, clock oscillation starts, and stable clocks are supplied to the entire LSI after the elapse of the time set in bits STS3 to STS0 in SBYCR. Then, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ15* interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ15* is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. Note: * IRQ8 to IRQ15 are not supported by the H8S/2424 group. * Clearing with the RES Pin: When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. * Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 1.00 Sep. 19, 2008 Page 1112 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes (3) Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS3 to STS0 in SBYCR should be set as described below. * Using a Crystal Resonator: Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time. Table 24.2 shows the standby times for operating frequencies and settings of bits STS3 to STS0. * Using an External Clock: A PLL circuit stabilization time is necessary. See table 24.2 to set the wait time. Table 24.2 Oscillation Stabilization Time Settings Standby STS3 STS2 STS1 STS0 Time 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Reserved Reserved Reserved Reserved Reserved 64 512 1024 2048 4096 16384 32765 65536 131072 262144 524288 * [MHz] 33 1.9 15.5 31.0 62.1 0.12 0.50 0.99 1.99 3.97 7.94 15.89 25 2.6 20.5 41.0 81.9 0.16 0.66 1.31 2.62 5.24 10.49 20.97 20 3.2 25.6 51.2 102.4 0.20 0.82 1.64 3.28 6.55 13.11 26.21 13 4.9 39.4 78.8 157.5 0.32 1.26 2.52 5.04 10.08 20.16 40.33 10 6.4 51.2 102.4 204.8 0.41 1.64 3.28 6.55 13.11 26.21 52.43 8 8.0 64.0 128.0 256.0 0.51 2.05 4.10 8.19 16.38 32.77 65.54 Unit s ms Note: * is the frequency divider output. Rev. 1.00 Sep. 19, 2008 Page 1113 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes (4) Software Standby Mode Application Example Figure 24.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, after an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), the NMIEG bit is set to 1 (rising edge specification). And after the SSBY bit is set to 1, a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator NMI NMIEG SSBY NMI exception handling NMIEG=1 SSBY=1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 24.2 Software Standby Mode Application Example Rev. 1.00 Sep. 19, 2008 Page 1114 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes 24.2.4 (1) Hardware Standby Mode Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while this LSI is in hardware standby mode. (2) Clearing Hardware Standby Mode Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (for details on the oscillation stabilization time, see table 24.2). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. (3) Hardware Standby Mode Timing Figure 24.3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 24.3 Hardware Standby Mode Timing Rev. 1.00 Sep. 19, 2008 Page 1115 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes (4) Hardware Standby Mode Timing when Power Is Supplied When entering hardware standby mode immediately after the power is supplied, the RES signal must be driven low for a given period with retaining the STBY signal high. After the RES signal is canceled, drive the STBY signal low. (1) Power supply RES (2) Reset period STBY (3) Hardware standby mode Figure 24.4 Hardware Standby Mode Timing when Power Is Supplied 24.2.5 Module Stop Function Module stop function can be set for individual on-chip peripheral modules. When an MSTP bit in MSTPCR, EXMSTPCR, or RMMSTPCR is set to 1, the corresponding module stops operation at the end of the bus cycle and a transition is made to module stop state. The CPU continues operating independently. When an MSTP bit is cleared to 0, the corresponding module stop state is cleared and the module starts operating at the end of the bus cycle. In module stop state, part of SCI registers and the internal state of SSU are reset but the internal states of the other modules are retained. After reset clearance, all modules other than the EXDMAC*, DMAC, DTC, and on-chip RAM are in module stop state. The module registers that are set in module stop state cannot be read or written to. The module-stop function for RAM is only effective for on-chip RAM. When an area of on-chip RAM is set up as an external address space by bits RAME and EXPE in SYSCR, the resulting external space is accessible regardless of the module-stop setting. Table 24.3 lists the kinds of operation in case of access to the on-chip RAM area. Note: * The EXDMAC is not supported by the H8S/2424 group. Rev. 1.00 Sep. 19, 2008 Page 1116 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes Table 24.3 Combinations of SYSCR Settings and Operation in Access to On-Chip RAM Register Settings RAME 1 EXPE X mstp 1 0 0 1 0 X X Target for Access Description On-chip RAM External address space This area is not readable/writable and access is prohibited. This area is not readable/writable and access is prohibited. 24.2.6 All Module Clocks Stop Mode When the ACSE bit in MSTPCRH is set to 1 and module stop mode is set for all the on-chip peripheral functions controlled by MSTPCR or EXMSTPCR (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF), or for all the on-chip peripheral functions except the 8-bit timer (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), executing a SLEEP instruction while the SSBY bit in SBYCR is cleared to 0 will cause all the on-chip peripheral functions (except the 8-bit timer and watchdog timer), the bus controller, and the I/O ports to stop operating, and a transition to be made to all module clocks stop mode at the end of the bus cycle. Operation or stopping of the 8-bit timer can be selected by means of the MSTP0 bit. To further reduce the current consumption in all module clocks stop mode, stop the modules controlled by RMMSTPCR (RMMSTPCR = H'FFFF). All module clocks stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15* pins), RES pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal program execution state via the exception handling state. All module clocks stop mode is not cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the relevant interrupt is designated as a DTC activation source. When the STBY pin is driven low, a transition is made to hardware standby mode. Note: * IRQ8 to IRQ15 are not supported by the H8S/2424 group. Rev. 1.00 Sep. 19, 2008 Page 1117 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes 24.3 Clock Output Control Output of the clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 24.4 shows the state of the pin in each processing state. Table 24.4 Pin State in Each Processing State Register Setting DDR 0 1 1 PSTOP X 0 1 Normal Operating State Sleep Mode High impedance output Fixed high High impedance output Fixed high Software Standby Mode High impedance Fixed high Fixed high Hardware Standby Mode High impedance High impedance High impedance All Module Clocks Stop Mode High impedance output Fixed high Rev. 1.00 Sep. 19, 2008 Page 1118 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes 24.4 SDRAM Clock Output Control Output of the SDRAM clock can be controlled by the SDPSTP bit in SCKCR. When the SDPSTP bit is set to 1, the SDRAM clock stops at the end of the bus cycle and the pin can be used as a general port. SDRAM clock output is enabled when the SDPSTP bit is cleared to 0 regardless of the DDR value. Table 24.5 shows the state of the SDRAM pin in each processing state. Note: The SDRAM interface is not supported by the H8S/2426 group and H8S/2424 group. Table 24.5 SDRAM Pin State in Each Processing State Register Setting SDPSTP 0 1 1 DDR x 0 1 Normal Operating State Sleep Mode SDRAM output High impedance PH1/CS5/RAS5 output SDRAM output High impedance H1/CS5/RAS5 output Software Standby Mode Fixed low High impedance H1/CS5/RAS5 output Hardware Standby Mode High impedance High impedance High impedance All Module Clocks Stop Mode SDRAM output High impedance H1/CS5/RAS5 output Note: SDRAM is not available in the H8S/2426 and H8S/2424 Groups. In these products, this pin functions as a general pin regardless of the SDPSTP bit setting. Rev. 1.00 Sep. 19, 2008 Page 1119 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes 24.5 24.5.1 Usage Notes I/O Port Status In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 24.5.2 Current Dissipation during Oscillation Stabilization Standby Period Current dissipation increases during the oscillation stabilization standby period. 24.5.3 EXDMAC, DMAC, and DTC Module Stop Depending on the operating status of the EXDMAC, DMAC, or DTC, the MSTP14 to MSTP13 and may not be set to 1. Setting of the EXDMAC, DMAC, or DTC module stop mode should be carried out only when the respective module is not activated. For details, see section 8, EXDMA Controller (EXDMAC), section 7, DMA Controller (DMAC), and section 9, Data Transfer Controller (DTC). Note: The EXDMAC is not supported by the H8S/2424 group. 24.5.4 On-Chip Peripheral Module Interrupts Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Note: The EXDMAC is not supported by the H8S/2424 group. 24.5.5 Writing to MSTPCR, EXMSTPCR, and RMMSTPCR MSTPCR, EXMSTPCR, and RMMSTPCR should only be written to by the CPU. Rev. 1.00 Sep. 19, 2008 Page 1120 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes 24.5.6 Notes on Clock Division Mode The following points should be noted in clock division mode. * Select the clock division ratio by the STC1 and STC0 bits so that the frequency of is within the operation guaranteed range of clock cycle time tcyc shown in the Electrical Characteristics. In other words, the frequency of must be 8 MHz or higher; be careful not so specify < 8 MHz. * All the on-chip peripheral modules operate on the . Therefore, note that the time processing of modules such as a timer and SCI differ before and after changing the clock division ratio. In addition, the wait time for clearing software standby mode differs by changing the clock division ratio. * Note that the frequency of will be changed by changing the clock division ratio. Rev. 1.00 Sep. 19, 2008 Page 1121 of 1270 REJ09B0466-0100 Section 24 Power-Down Modes Rev. 1.00 Sep. 19, 2008 Page 1122 of 1270 REJ09B0466-0100 Section 25 List of Registers Section 25 List of Registers The address list gives information on the on-chip register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * 2. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The access size is indicated. Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. For the registers of 16 or 32 bits, the MSB is described first. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, see the section on that on-chip peripheral module. Rev. 1.00 Sep. 19, 2008 Page 1123 of 1270 REJ09B0466-0100 Section 25 List of Registers 25.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Number of Bits Address 8 24 8 24 16 16 H'FC80 H'FC81 H'FC90 H'FC92 H'FC94 H'FC96 H'FC98 H'FCA0 H'FCA2 H'FCA4 H'FCA6 H'FCA8 H'FCAA H'FCAC H'FCAE H'FCB0 H'FCB1 H'BC00 to H'BFFF Data Width 16/32 16/32 16/32 16/32 16/32 16/32 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name DTC mode register A DTC source address register DTC mode register B DTC destination address register DTC transfer count register A DTC transfer count register B RAM module stop control register H RAM module stop control register L Interrupt priority register L Interrupt priority register M Interrupt priority register N DTC enable register I DTC control register A/D data register A_1 A/D data register B_1 A/D data register C_1 A/D data register D_1 A/D data register E_1 A/D data register F_1 A/D data register G_1 A/D data register H_1 A/D control/status register_1 A/D control register_1 Abbreviation MRA SAR MRB DAR CRA CRB Module DTC DTC DTC DTC DTC DTC SYSTEM SYSTEM INT INT INT DTC DTC A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 RMMSTPCRH 8 RMMSTPCRL 8 IPRL IPRM IPRN DTCERI DTCCR ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 16 16 16 8 8 16 16 16 16 16 16 16 16 8 8 Rev. 1.00 Sep. 19, 2008 Page 1124 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Timer start register_1 Timer synchronous register_1 Timer control register_6 Timer mode register_6 Timer I/O control register H_6 Timer I/O control register L_6 Timer interrupt enable register_6 Timer status register_6 Timer counter_6 Timer general register A_6 Timer general register B_6 Timer general register C_6 Timer general register D_6 Timer control register_7 Timer mode register_7 Timer I/O control register_7 Timer interrupt enable register_7 Timer status register_7 Timer counter_7 Timer general register A_7 Timer general register B_7 Timer control register_8 Timer mode register_8 Timer I/O control register_8 Timer interrupt enable register_8 Timer status register_8 Timer counter_8 Timer general register A_8 Timer general register B_8 Timer control register_9 Timer mode register_9 Timer I/O control register H_9 Abbreviation TSTR_1 TSYR_1 TCR_6 TMDR_6 TIORH_6 TIORL_6 TIER_6 TSR_6 TCNT_6 TGRA_6 TGRB_6 TGRC_6 TGRD_6 TCR_7 TMDR_7 TIOR_7 TIER_7 TSR_7 TCNT_7 TGRA_7 TGRB_7 TCR_8 TMDR_8 TIOR_8 TIER_8 TSR_8 TCNT_8 TGRA_8 TGRB_8 TCR_9 TMDR_9 TIORH_9 Number of Bits Address 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 H'FCC0 H'FCC1 H'FCD0 H'FCD1 H'FCD2 H'FCD3 H'FCD4 H'FCD5 H'FCD6 H'FCD8 H'FCDA H'FCDC H'FCDE H'FCE0 H'FCE1 H'FCE2 H'FCE4 H'FCE5 H'FCE6 H'FCE8 H'FCEA H'FCF0 H'FCF1 H'FCF2 H'FCF4 H'FCF5 H'FCF6 H'FCF8 H'FCFA H'FD00 H'FD01 H'FD02 Module TPU TPU TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_9 TPU_9 TPU_9 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1125 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Timer I/O control register L_9 Timer interrupt enable register_9 Timer status register_9 Timer counter_9 Timer general register A_9 Timer general register B_9 Timer general register C_9 Timer general register D_9 Timer control register_10 Timer mode register_10 Timer I/O control register_10 Timer interrupt enable register_10 Timer status register_10 Timer counter_10 Timer general register A_10 Timer general register B_10 Timer control register_11 Timer mode register_11 Timer I/O control register_11 Timer interrupt enable register_11 Timer status register_11 Timer counter_11 Timer general register A_11 Timer general register B_11 Port 1 open drain control register Port 2 open drain control register Port 5 open drain control register Port 6 open drain control register Port 8 open drain control register Port B open drain control register Port C open drain control register Port D open drain control register Abbreviation TIORL_9 TIER_9 TSR_9 TCNT_9 TGRA_9 TGRB_9 TGRC_9 TGRD_9 TCR_10 TMDR_10 TIOR_10 TIER_10 TSR_10 TCNT_10 TGRA_10 TGRB_10 TCR_11 TMDR_11 TIOR_11 TIER_11 TSR_11 TCNT_11 TGRA_11 TGRB_11 P1ODR P2ODR P5ODR P6ODR P8ODR PBODR PCODR PDODR Number of Bits Address 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 H'FD03 H'FD04 H'FD05 H'FD06 H'FD08 H'FD0A H'FD0C H'FD0E H'FD10 H'FD11 H'FD12 H'FD14 H'FD15 H'FD16 H'FD18 H'FD1A H'FD20 H'FD21 H'FD22 H'FD24 H'FD25 H'FD26 H'FD28 H'FD2A H'FD40 H'FD41 H'FD42 H'FD43 H'FD44 H'FD45 H'FD46 H'FD47 Module TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 PORT PORT PORT PORT PORT PORT PORT PORT Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1126 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Port E open drain control register Port F open drain control register Port G open drain control register Port H open drain control register Port J open drain control register I C bus control register A_0 I C bus control register B_0 I C bus mode register_0 I C bus interrupt enable register_0 I C bus status register_0 Slave address register_0 I C transfer data register_0 I C receive data register_0 I C bus control register A_1 I C bus control register B_1 I C bus mode register_1 I C bus interrupt enable register_1 I C bus status register_1 Slave address register_1 I C transfer data register_1 I C receive data register_1 I C bus control register A_2 I C bus control register B_2 I C bus mode register_2 I C bus interrupt enable register_2 I C bus status register_2 Slave address register_2 I C transfer data register_2 I C receive data register_2 I C bus control register A_3 I C bus control register B_3 I C bus mode register_3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Abbreviation PEODR PFODR PGODR PHODR PJODR ICCRA_0 ICCRB_0 ICMR_0 ICIER_0 ICSR_0 SAR_0 ICDRT_0 ICDRR_0 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 ICCRA_2 ICCRB_2 ICMR_2 ICIER_2 ICSR_2 SAR_2 ICDRT_2 ICDRR_2 ICCRA_3 ICCRB_3 ICMR_3 Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FD48 H'FD49 H'FD4A H'FD4B H'FD4C H'FD58 H'FD59 H'FD5A H'FD5B H'FD5C H'FD5D H'FD5E H'FD5F H'FD60 H'FD61 H'FD62 H'FD63 H'FD64 H'FD65 H'FD66 H'FD67 H'FD68 H'FD69 H'FD6A H'FD6B H'FD6C H'FD6D H'FD6E H'FD6F H'FD70 H'FD71 H'FD72 Module PORT PORT PORT PORT PORT IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_1 IIC2_1 IIC2_1 IIC2_1 IIC2_1 IIC2_1 IIC2_1 IIC2_1 IIC2_2 IIC2_2 IIC2_2 IIC2_2 IIC2_2 IIC2_2 IIC2_2 IIC2_2 IIC2_3 IIC2_3 IIC2_3 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1127 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name I C bus interrupt enable register_3 I C bus status register_3 Slave address register_3 I C transfer data register_3 I C receive data register_3 Serial expansion mode register_2 SS control register H SS control register L SS mode register SS enable register SS status register SS control register 2 SS transmit data register 0 SS transmit data register 1 SS transmit data register 2 SS transmit data register 3 SS receive data register 0 SS receive data register 1 SS receive data register 2 SS receive data register 3 EXDMA source address register_2 EXDMA destination address register_2 EXDMA transfer count register_2 EXDMA mode control register_2 EXDMA address control register_2 EXDMA source address register_3 2 2 2 2 Abbreviation ICIER_3 ICSR_3 SAR_3 ICDRT_3 ICDRR_3 SEMR_2 SSCRH SSCRL SSMR SSER SSSR SSCR2 SSTDR0 SSTDR1 SSTDR2 SSTDR3 SSRDR0 SSRDR1 SSRDR2 SSRDR3 EDSAR_2 EDDAR_2 EDTCR_2 EDMDR_2 EDACR_2 EDSAR_3 Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 32 32 32 16 16 32 H'FD73 H'FD74 H'FD75 H'FD76 H'FD77 H'FDA8 H'FDB0 H'FDB1 H'FDB2 H'FDB3 H'FDB4 H'FDB5 H'FDB6 H'FDB7 H'FDB8 H'FDB9 H'FDBA H'FDBB H'FDBC H'FDBD H'FDE0 H'FDE4 H'FDE8 H'FDEC H'FDEE H'FDF0 Module IIC2_3 IIC2_3 IIC2_3 IIC2_3 IIC2_3 SCI_2 SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU SSU Data Width 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 EXDMAC_ 16 3 2* EXDMAC_ 16 3 2* EXDMAC_ 16 3 2* EXDMAC_ 16 3 2* EXDMAC_ 16 3 2* EXDMAC_ 16 3 3* Rev. 1.00 Sep. 19, 2008 Page 1128 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name EXDMA destination address register_3 EXDMA transfer count register_3 EXDMA mode control register_3 EXDMA address control register_3 Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K IRQ pin select register Software standby release IRQ enable register IRQ sense control register H IRQ sense control register L IrDA control register_0 Port 1 data direction register Port 2 data direction register Port 3 data direction register Port 5 data direction register Port 6 data direction register Abbreviation EDDAR_3 EDTCR_3 EDMDR_3 EDACR_3 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK ITSR SSIER ISCRH ISCRL IrCR_0 P1DDR P2DDR P3DDR P5DDR P6DDR Number of Bits Address 32 32 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 H'FDF4 H'FDF8 H'FDFC H'FDFE H'FE00 H'FE02 H'FE04 H'FE06 H'FE08 H'FE0A H'FE0C H'FE0E H'FE10 H'FE12 H'FE14 H'FE16 H'FE18 H'FE1A H'FE1C H'FE1E H'FE20 H'FE21 H'FE22 H'FE24 H'FE25 Module Data Width Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 EXDMAC_ 16 3 3* EXDMAC_ 16 3 3* EXDMAC_ 16 3 3* EXDMAC_ 16 3 3* INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT IrDA PORT PORT PORT PORT PORT 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 Rev. 1.00 Sep. 19, 2008 Page 1129 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Port 8 data direction register Port A data direction register Port B data direction register Port C data direction register Port D data direction register Port E data direction register Port F data direction register Port G data direction register Port function control register 0 Port function control register 1 Port function control register 2 Port A pull-up MOS control register Port B pull-up MOS control register Port C pull-up MOS control register Port D pull-up MOS control register Port E pull-up MOS control register Port 3 open drain control register Port A open drain control register Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit data register_3 Serial status register_3 Receive data register_3 Smart card mode register_3 Serial mode register_4 Bit rate register_4 Serial control register_4 Transmit data register_4 Serial status register_4 Abbreviation P8DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PGDDR PFCR0 PFCR1 PFCR2 PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SCMR_3 SMR_4 BRR_4 SCR_4 TDR_4 SSR_4 Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE27 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE32 H'FE33 H'FE34 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3C H'FE3D H'FE40 H'FE41 H'FE42 H'FE43 H'FE44 H'FE45 H'FE46 H'FE48 H'FE49 H'FE4A H'FE4B H'FE4C Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1130 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Receive data register_4 Smart card mode register_4 Timer control register_3 Timer mode register_3 Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3 Timer control register_4 Timer mode register_4 Timer I/O control register_4 Timer interrupt enable register_4 Timer status register_4 Timer counter_4 Timer general register A_4 Timer general register B_4 Timer control register_5 Timer mode register_5 Timer I/O control register_5 Timer interrupt enable register_5 Timer status register_5 Timer counter_5 Timer general register A_5 Timer general register B_5 Abbreviation RDR_4 SCMR_4 TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 Number of Bits Address 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 H'FE4D H'FE4E H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE98 H'FE9A H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA8 H'FEAA Module SCI_4 SCI_4 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 Data Width 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1131 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Flash memory control register 1 Flash memory data block protect register Flash memory status register Bus width control register Access state control register Wait control register AH Wait control register AL Wait control register BH Wait control register BL Read strobe timing control register CS assertion period control register H CS assertion period control register L Abbreviation FLMCR1 DFPR FLMSTR ABWCR ASTCR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR CSACRH CSACRL Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 16 8 8 16 8 8 H'FEB0 H'FEB2 H'FEB3 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECF H'FED0 H'FED2 H'FED3 H'FED4 H'FED6 H'FED7 Module FLASH FLASH FLASH BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC Data Width 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Burst ROM interface control register BROMCRH H Burst ROM interface control register BROMCRL L Bus control register BCR Address/data multiplexed I/O control MPXCR register DRAM control register L DRAM access control register H DRAM access control register L Refresh control register Refresh timer counter Refresh time constant register DRAMCR DRACCRH DRACCRL REFCR RTCNT RTCOR Rev. 1.00 Sep. 19, 2008 Page 1132 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Memory address register_0AH Memory address register_0AL I/O address register_0A Transfer count register_0A Memory address register_0BH Memory address register_0BL I/O address register_0B Transfer count register_0B Memory address register_1AH Memory address register_1AL I/O address register_1A Transfer count register_1A Memory address register_1BH Memory address register_1BL I/O address register_1B Transfer count register_1B DMA write enable register DMA terminal control register DMA control register_0A DMA control register_0B DMA control register_1A DMA control register_1B DMA band control register H DMA band control register L DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC enable register F Abbreviation MAR_0AH MAR_0AL IOAR_0A ETCR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B DMABCRH DMABCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF Number of Bits Address 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEE0 H'FEE2 H'FEE4 H'FEE6 H'FEE8 H'FEEA H'FEEC H'FEEE H'FEF0 H'FEF2 H'FEF4 H'FEF6 H'FEF8 H'FEFA H'FEFC H'FEFE H'FF20 H'FF21 H'FF22 H'FF23 H'FF24 H'FF25 H'FF26 H'FF27 H'FF28 H'FF29 H'FF2A H'FF2B H'FF2C H'FF2D Module DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DTC DTC DTC DTC DTC DTC Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1133 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name DTC enable register G DTC enable register H DTC vector register Interrupt control register IRQ enable register IRQ status register Standby control register System clock control register System control register Mode control register Module stop control register H Module stop control register L Extension module stop control register H Extension module stop control register L PLL control register PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H* Next data register L* 1 Abbreviation DTCERG DTCERH DTVECR INTCR IER ISR SBYCR SCKCR SYSCR MDCR MSTPCRH MSTPCRL EXMSTPCRH EXMSTPCRL PLLCR PCR PMR NDERH NDERL PODRH PODRL NDRHH NDRLH NDRHL NDRLL Number of Bits Address 8 8 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF2E H'FF2F H'FF30 H'FF31 H'FF32 H'FF34 H'FF3A H'FF3B H'FF3D H'FF3E H'FF40 H'FF41 H'FF42 H'FF43 H'FF45 H'FF46 H'FF47 H'FF48 H'FF49 H'FF4A H'FF4B H'FF4C H'FF4D H'FF4E H'FF4F Module DTC DTC DTC INT INT INT SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM PPG PPG PPG PPG PPG PPG PPG PPG PPG PPG Data Width 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 Next data register H* Next data register L* 1 1 Rev. 1.00 Sep. 19, 2008 Page 1134 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Port 1 register Port 2 register Port 3 register Port 4 register Port 5 register Port 6 register Port 8 register Port 9 register Port A register Port B register Port C register Port D register Port E register Port F register Port G register Port 1 data register Port 2 data register Port 3 data register Port 5 data register Port 6 data register Port 8 data register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Abbreviation PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT8 PORT9 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR P5DR P6DR P8DR PADR PBDR PCDR PDDR PEDR PFDR PGDR Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF50 H'FF51 H'FF52 H'FF53 H'FF54 H'FF55 H'FF57 H'FF58 H'FF59 H'FF5A H'FF5B H'FF5C H'FF5D H'FF5E H'FF5F H'FF60 H'FF61 H'FF62 H'FF64 H'FF65 H'FF67 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1135 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Port H register Port J register Port H data register Port J data register Port H data direction register Port J data direction register Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 Abbreviation PORTH PORTJ PHDR PJDR PHDDR PJDDR SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 Number of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF75 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E Module PORT PORT PORT PORT PORT PORT SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1136 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name A/D data register A A/D data register B A/D data register C A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H A/D control/status register A/D control register D/A data register 2 D/A data register 3 D/A control register 23 Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 Timer counter control register_0 Timer counter control register_1 Abbreviation ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR DADR2 DADR3 DACR23 TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCCR_0 TCCR_1 Number of Bits Address 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF90 H'FF92 H'FF94 H'FF96 H'FF98 H'FF9A H'FF9C H'FF9E H'FFA0 H'FFA1 H'FFA8 H'FFA9 H'FFAA H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB Module A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 D/A D/A D/A TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR TMR Data Width 16 16 16 16 16 16 16 16 16 16 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1137 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Timer control/status register Abbreviation TCSR Number of Bits Address 8 H'FFBC* (Write) H'FFBC (Read) 2 Module WDT Data Width 16 Access States 2 Timer counter TCNT 8 H'FFBC* (Write) H'FFBD (Read) 2 WDT 16 2 Reset control/status register RSTCSR 8 H'FFBE* (Write) H'FFBF (Read) 2 WDT 16 2 Timer start register Timer synchronous register Port function control register 3 Port function control register 4 Port function control register 5 Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 TSTR TSYR PFCR3 PFCR4 PFCR5 TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 H'FFC0 H'FFC1 H'FFC8 H'FFC9 H'FFCA H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 H'FFDA H'FFDC H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE4 TPU TPU PORT PORT PORT TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_1 TPU_1 TPU_1 TPU_1 16 16 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 19, 2008 Page 1138 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Name Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Abbreviation TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 Number of Bits Address 8 16 16 16 8 8 8 8 8 16 16 16 H'FFE5 H'FFE6 H'FFE8 H'FFEA H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFFA Module TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 Notes: 1. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D. 2. For writing, see section 14.6.1, Notes on Register Access. 3. Not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 1139 of 1270 REJ09B0466-0100 Section 25 List of Registers 25.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Abbreviation Bit 7 MRA SAR SM1 MRB DAR CHNE CRA CRB RMMSTPCR H RMMSTPCRL MSTP39 USPLLCR IPRL IPRM IPRN DTCERL DTCCR DTCE7 SWDTE MSTP38 IPR14 IPR6 IPR14 IPR6 IPR14 IPR6 DTCE6 MSTP37 IPR13 IPR5 IPR13 IPR5 IPR13 IPR5 DTCE5 MSTP36 IPR12 IPR4 IPR12 IPR4 IPR12 IPR4 DTCE4 MSTP35 DTCE3 MSTP34 IPR10 IPR2 IPR10 IPR2 IPR10 IPR2 DTCE2 MSTP33 USSTC1 IPR9 IPR1 IPR9 IPR1 IPR9 IPR1 DTCE1 MSTP32 USSTC0 IPR8 IPR0 IPR8 IPR0 IPR8 IPR0 DTCE0 INTC MSTP47 Bit 6 SM0 DISEL MSTP46 Bit 5 DM1 CHNS MSTP45 Bit 4 DM0 MSTP44 Bit 3 MD1 MSTP43 Bit 2 MD0 MSTP42 Bit 1 DTS MSTP41 Bit 0 Sz MSTP40 SYSTEM Module DTC*1 Rev. 1.00 Sep. 19, 2008 Page 1140 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 ADDRA_1 AD9 AD1 ADDRB_1 AD9 AD1 ADDRC_1 AD9 AD1 ADDRD_1 AD9 AD1 ADDRE_1 AD9 AD1 ADDRF_1 AD9 AD1 ADDRG_1 AD9 AD1 ADDRH_1 AD9 AD1 ADCSR_1 ADCR_1 TSTR_1 TSYR_1 TCR_6 TMDR_6 TIORH_6 TIORL_6 TIER_6 TSR_6 TCNT_6 ADF TRGS1 CCLR2 IOB3 IOD3 TTGE Bit 15 Bit 7 TGRA_6 Bit 15 Bit 7 TGRB_6 Bit 15 Bit 7 Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 CCLR1 IOB2 IOD2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 5 AD7 AD7 AD7 AD7 AD7 AD7 AD7 AD7 ADST SCANE CST5 SYNC5 CCLR0 BFB IOB1 IOD1 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 4 AD6 AD6 AD6 AD6 AD6 AD6 AD6 AD6 EXCKS SCANS CST4 SYNC4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 3 AD5 AD5 AD5 AD5 AD5 AD5 AD5 AD5 CH3 CKS1 CST3 SYNC3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 2 AD4 AD4 AD4 AD4 AD4 AD4 AD4 AD4 CH2 CKS0 CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 1 AD3 AD3 AD3 AD3 AD3 AD3 AD3 AD3 CH1 Bit 0 AD2 AD2 AD2 AD2 AD2 AD2 AD2 AD2 CH0 Module A/D_1 ADSTCLR EXTRGS CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPU_6 TPU Rev. 1.00 Sep. 19, 2008 Page 1141 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 TGRC_6 Bit 15 Bit 7 TGRD_6 Bit 15 Bit 7 TCR_7 TMDR_7 TIOR_7 TIER_7 TSR_7 TCNT_7 IOB3 TTGE TCFD Bit 15 Bit 7 TGRA_7 Bit 15 Bit 7 TGRB_7 Bit 15 Bit 7 TCR_8 TMDR_8 TIOR_8 TIER_8 TSR_8 TCNT_8 IOB3 TTGE TCFD Bit 15 Bit 7 TGRA_8 Bit 15 Bit 7 TGRB_8 Bit 15 Bit 7 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPU_8 TPU_7 Module TPU_6 Rev. 1.00 Sep. 19, 2008 Page 1142 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 TCR_9 TMDR_9 TIORH_9 TIORL_9 TIER_9 TSR_9 TCNT_9 CCLR2 IOB3 IOD3 TTGE Bit 15 Bit 7 TGRA_9 Bit 15 Bit 7 TGRB_9 Bit 15 Bit 7 TGRC_9 Bit 15 Bit 7 TGRD_9 Bit 15 Bit 7 TCR_10 TMDR_10 TIOR_10 TIER_10 TSR_10 TCNT_10 IOB3 TTGE TCFD Bit 15 Bit 7 TGRA_10 Bit 15 Bit 7 TGRB_10 Bit 15 Bit 7 Bit 6 CCLR1 IOB2 IOD2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 5 CCLR0 BFB IOB1 IOD1 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPU_10 Module TPU_9 Rev. 1.00 Sep. 19, 2008 Page 1143 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 TCR_11 TMDR_11 TIOR_11 TIER_11 TSR_11 TCNT_11 IOB3 TTGE TCFD Bit 15 Bit 7 TGRA_11 Bit 15 Bit 7 TGRB_11 Bit 15 Bit 7 P1ODR P2ODR P5ODR P6ODR P8ODR PBODR PCODR PDODR PEODR PFODR PGODR PHODR PJODR ICCRA_0 ICCRB_0 ICMR_0 ICIER_0 ICSR_0 SAR_0 ICDRT_0 ICDRR_0 P17ODR P27ODR PB7ODR PC7ODR PD7ODR PE7ODR PF7ODR ICE BBSY TIE TDRE SVA6 ICDRT7 ICDRR7 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 P16ODR P26ODR PB6ODR PC6ODR PD6ODR PE6ODR PF6ODR PG6ODR RCVD SCP WAIT TEIE TEND SVA5 ICDRT6 ICDRR6 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 P15ODR P25ODR P65ODR P85ODR PB5ODR PC5ODR PD5ODR PE5ODR PF5ODR PG5ODR MST SDAO RIE RDRF SVA4 ICDRT5 ICDRR5 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 P14ODR P24ODR P64ODR P84ODR PB4ODR PC4ODR PD4ODR PE4ODR PF4ODR PG4ODR TRS SDAOP NAKIE NACKF SVA3 ICDRT4 ICDRR4 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 P13ODR P23ODR P53ODR P63ODR P83ODR PB3ODR PC3ODR PD3ODR PE3ODR PF3ODR PG3ODR PH3ODR CKS3 SCLO BCWP STIE STOP SVA2 ICDRT3 ICDRR3 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 P12ODR P22ODR P52ODR P62ODR P82ODR PB2ODR PC2ODR PD2ODR PE2ODR PF2ODR PG2ODR PH2ODR CKS2 BC2 ACKE AL SVA1 ICDRT2 ICDRR2 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 P11ODR P21ODR P51ODR P61ODR P81ODR PB1ODR PC1ODR PD1ODR PE1ODR PF1ODR PG1ODR PH1ODR PJ1ODR CKS1 IICRST BC1 ACKBR AAS SVA0 ICDRT1 ICDRR1 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 P10ODR P20ODR P50ODR P60ODR P80ODR PB0ODR PC0ODR PD0ODR PE0ODR PF0ODR PG0ODR PH0ODR PJ0ODR CKS0 BC0 ACKBT ADZ ICDRT0 ICDRR0 IIC2_0 PORT Module TPU_11 Rev. 1.00 Sep. 19, 2008 Page 1144 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 ICCRA_2 ICCRB_2 ICMR_2 ICIER_2 ICSR_2 SAR_2 ICDRT_2 ICDRR_2 ICCRA_3 ICCRB_3 ICMR_3 ICIER_3 ICSR_3 SAR_3 ICDRT_3 ICDRR_3 SEMR_2 SSCRH SSCRL SSMR SSER SSSR SSCR2 ICE BBSY TIE TDRE SVA6 ICDRT7 ICDRR7 ICE BBSY TIE TDRE SVA6 ICDRT7 ICDRR7 ICE BBSY TIE TDRE SVA6 ICDRT7 ICDRR7 SSE MSS MLS TE SDOS Bit 6 RCVD SCP WAIT TEIE TEND SVA5 ICDRT6 ICDRR6 RCVD SCP WAIT TEIE TEND SVA5 ICDRT6 ICDRR6 RCVD SCP WAIT TEIE TEND SVA5 ICDRT6 ICDRR6 BIDE SSUMS CPOS RE ORER SSCKOS Bit 5 MST SDAO RIE RDRF SVA4 ICDRT5 ICDRR5 MST SDAO RIE RDRF SVA4 ICDRT5 ICDRR5 MST SDAO RIE RDRF SVA4 ICDRT5 ICDRR5 SRES CPHS SCSOS Bit 4 TRS SDAOP NAKIE NACKF SVA3 ICDRT4 ICDRR4 TRS SDAOP NAKIE NACKF SVA3 ICDRT4 ICDRR4 TRS SDAOP NAKIE NACKF SVA3 ICDRT4 ICDRR4 SOL Bit 3 CKS3 SCLO BCWP STIE STOP SVA2 ICDRT3 ICDRR3 CKS3 SCLO BCWP STIE STOP SVA2 ICDRT3 ICDRR3 CKS3 SCLO BCWP STIE STOP SVA2 ICDRT3 ICDRR3 ABCS SOLP TEIE TEND Bit 2 CKS2 BC2 ACKE AL SVA1 ICDRT2 ICDRR2 CKS2 BC2 ACKE AL SVA1 ICDRT2 ICDRR2 CKS2 BC2 ACKE AL SVA1 ICDRT2 ICDRR2 ACS2 SCKS CKS2 TIE TDRE SSODTS Bit 1 CKS1 IICRST BC1 ACKBR AAS SVA0 ICDRT1 ICDRR1 CKS1 IICRST BC1 ACKBR AAS SVA0 ICDRT1 ICDRR1 CKS1 IICRST BC1 ACKBR AAS SVA0 ICDRT1 ICDRR1 ACS1 CSS1 DATS1 CKS1 RIE RDRF Bit 0 CKS0 BC0 ACKBT ADZ ICDRT0 ICDRR0 CKS0 BC0 ACKBT ADZ ICDRT0 ICDRR0 CKS0 BC0 ACKBT ADZ ICDRT0 ICDRR0 ACS0 CSS0 DATS0 CKS0 CEIE CE SCI_2 SSU IIC2_3 IIC2_2 Module IIC2_1 TENDSTS SCSATS Rev. 1.00 Sep. 19, 2008 Page 1145 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 SSTDR0 SSTDR1 SSTDR2 SSTDR3 SSRDR0 SSRDR1 SSRDR2 SSRDR3 EDSAR_2 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 31 Bit 23 Bit 15 Bit 7 EDDAR_2 Bit 31 Bit 23 Bit 15 Bit 7 EDTCR_2 Bit 31 Bit 23 Bit 15 Bit 7 EDMDR_2 EDA EDIE EDACR_2 SAT1 DAT1 EDSAR_3 Bit 31 Bit 23 Bit 15 Bit 7 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 30 Bit 22 Bit 14 Bit 6 Bit 30 Bit 22 Bit 14 Bit 6 Bit 30 Bit 22 Bit 14 Bit 6 BEF IRF SAT0 DAT0 Bit 30 Bit 22 Bit 14 Bit 6 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 29 Bit 21 Bit 13 Bit 5 Bit 29 Bit 21 Bit 13 Bit 5 Bit 29 Bit 21 Bit 13 Bit 5 EDRAKE TCEIE SARIE DARIE Bit 29 Bit 21 Bit 13 Bit 5 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 28 Bit 20 Bit 12 Bit 4 Bit 28 Bit 20 Bit 12 Bit 4 Bit 28 Bit 20 Bit 12 Bit 4 ETENDE SDIR SARA4 DARA4 Bit 28 Bit 20 Bit 12 Bit 4 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 27 Bit 19 Bit 11 Bit 3 Bit 27 Bit 19 Bit 11 Bit 3 Bit 27 Bit 19 Bit 11 Bit 3 EDREQS DTSIZE SARA3 DARA3 Bit 27 Bit 19 Bit 11 Bit 3 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 26 Bit 18 Bit 10 Bit 2 Bit 26 Bit 18 Bit 10 Bit 2 Bit 26 Bit 18 Bit 10 Bit 2 AMS BGUP SARA2 DARA2 Bit 26 Bit 18 Bit 10 Bit 2 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 25 Bit 17 Bit 9 Bit 1 Bit 25 Bit 17 Bit 9 Bit 1 Bit 25 Bit 17 Bit 9 Bit 1 MDS1 SARA1 DARA1 Bit 25 Bit 17 Bit 9 Bit 1 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 24 Bit 16 Bit 8 Bit 0 Bit 24 Bit 16 Bit 8 Bit 0 Bit 24 Bit 16 Bit 8 Bit 0 MDS0 SARA0 DARA0 Bit 24 Bit 16 Bit 8 Bit 0 EXDMAC_3*7 EXDMAC_2*7 Module SSU Rev. 1.00 Sep. 19, 2008 Page 1146 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 EDDAR_3 Bit 31 Bit 23 Bit 15 Bit 7 Bit 31 EDTCR_3 Bit 31 Bit 23 Bit 15 Bit 7 EDMDR_3 EDA EDIE EDACR_3 SAT1 DAT1 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI Bit 6 Bit 30 Bit 22 Bit 14 Bit 6 Bit 30 Bit 30 Bit 22 Bit 14 Bit 6 BEF IRF SAT0 DAT0 IPRA14 IPRA6 IPRB14 IPRB6 IPRC14 IPRC6 IPRD14 IPRD6 IPRE14 IPRE6 IPRF14 IPRF6 IPRG14 IPRG6 IPRH14 IPRH6 IPRI14 IPRI6 Bit 5 Bit 29 Bit 21 Bit 13 Bit 5 Bit 29 Bit 29 Bit 21 Bit 13 Bit 5 EDRAKE TCEIE SARIE DARIE IPRA13 IPRA5 IPRB13 IPRB5 IPRC13 IPRC5 IPRD13 IPRD5 IPRE13 IPRE5 IPRF13 IPRF5 IPRG13 IPRG5 IPRH13 IPRH5 IPRI13 IPRI5 Bit 4 Bit 28 Bit 20 Bit 12 Bit 4 Bit 28 Bit 28 Bit 20 Bit 12 Bit 4 ETENDE SDIR SARA4 DARA4 IPRA12 IPRA4 IPRB12 IPRB4 IPRC12 IPRC4 IPRD12 IPRD4 IPRE12 IPRE4 IPRF12 IPRF4 IPRG12 IPRG4 IPRH12 IPRH4 IPRI12 IPRI4 Bit 3 Bit 27 Bit 19 Bit 11 Bit 3 Bit 27 Bit 27 Bit 19 Bit 11 Bit 3 EDREQS DTSIZE SARA3 DARA3 Bit 2 Bit 26 Bit 18 Bit 10 Bit 2 Bit 26 Bit 26 Bit 18 Bit 10 Bit 2 AMS BGUP SARA2 DARA2 IPRA10 IPRA2 IPRB10 IPRB2 IPRC10 IPRC2 IPRD10 IPRD2 IPRE10 IPRE2 IPRF10 IPRF2 IPRG10 IPRG2 IPRH10 IPRH2 IPRI10 IPRI2 Bit 1 Bit 25 Bit 17 Bit 9 Bit 1 Bit 25 Bit 25 Bit 17 Bit 9 Bit 1 MDS1 SARA1 DARA1 IPRA9 IPRA1 IPRB9 IPRB1 IPRC9 IPRC1 IPRD9 IPRD1 IPRE9 IPRE1 IPRF9 IPRF1 IPRG9 IPRG1 IPRH9 IPRH1 IPRI9 IPRI1 Bit 0 Bit 24 Bit 16 Bit 8 Bit 0 Bit 24 Bit 24 Bit 16 Bit 8 Bit 0 MDS0 SARA0 DARA0 IPRA8 IPRA0 IPRB8 IPRB0 IPRC8 IPRC0 IPRD8 IPRD0 IPRE8 IPRE0 IPRF8 IPRF0 IPRG8 IPRG0 IPRH8 IPRH0 IPRI8 IPRI0 INT Module EXDMAC_3*7 Rev. 1.00 Sep. 19, 2008 Page 1147 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 IPRJ IPRK ITSR ITS15 ITS7 SSIER SSI15 SSI7 ISCRH IRQ15SC B IRQ11SC B ISCRL Bit 6 IPRJ14 IPRJ6 IPRK14 IPRK6 ITS14 ITS6 SSI14 SSI6 IRQ15SC A IRQ11SC A Bit 5 IPRJ13 IPRJ5 IPRK13 IPRK5 ITS13 ITS5 SSI13 SSI5 IRQ14SC B IRQ10SC B Bit 4 IPRJ12 IPRJ4 IPRK12 IPRK4 ITS4 SSI12 SSI4 Bit 3 ITS3 SSI11 SSI3 Bit 2 IPRJ10 IPRJ2 IPRK10 IPRK2 ITS2 SSI10 SSI2 Bit 1 IPRJ9 IPRJ1 IPRK9 IPRK1 ITS1 SSI9 SSI1 Bit 0 IPRJ8 IPRJ0 IPRK8 IPRK0 ITS8 ITS0 SSI8 SSI0 IRQ12SC A Module INT IRQ14SC IRQ13SC A B IRQ13SCA IRQ12SC B IRQ10SC IRQ9SCB IRQ9SCA A IRQ8SCB IRQ8SCA IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ4SCB IRQ4SCA IRQ0SCB IRQ0SCA P11DDR P21DDR P31DDR P51DDR P61DDR P81DDR PA1DDR PB1DDR PC1DDR PD1DDR PE1DDR PF1DDR PG1DDR CS1E A17E OES P10DDR P20DDR P30DDR P50DDR P60DDR P80DDR PA0DDR PB0DDR PC0DDR PD0DDR PE0DDR PF0DDR PG0DDR CS0E A16E IrDA PORT IrCR_0 P1DDR P2DDR P3DDR P5DDR P6DDR P8DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PGDDR PFCR0 PFCR1 PFCR2 IrE P17DDR P27DDR PA7DDR PB7DDR PC7DDR PD7DDR PE7DDR PF7DDR CS7E A23E IrCKS2 P16DDR P26DDR PA6DDR PB6DDR PC6DDR PD6DDR PE6DDR PF6DDR PG6DDR CS6E A22E IrCKS1 P15DDR P25DDR P35DDR P65DDR P85DDR PA5DDR PB5DDR PC5DDR PD5DDR PE5DDR PF5DDR PG5DDR CS5E A21E IrCKS0 P14DDR P24DDR P34DDR P64DDR P84DDR PA4DDR PB4DDR PC4DDR PD4DDR PE4DDR PF4DDR PG4DDR CS4E A20E IrTxINV P13DDR P23DDR P33DDR P53DDR P63DDR P83DDR PA3DDR PB3DDR PC3DDR PD3DDR PE3DDR PF3DDR PG3DDR CS3E A19E ASOE IrRxINV P12DDR P22DDR P32DDR P52DDR P62DDR P82DDR PA2DDR PB2DDR PC2DDR PD2DDR PE2DDR PF2DDR PG2DDR CS2E A18E LWROE Rev. 1.00 Sep. 19, 2008 Page 1148 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR SMR_3* SMR_3* BRR_3 SCR_3 TDR_3 SSR_3* SSR_3* RDR_3 SCMR_3 SMR_4* 4 4 4 Bit 6 PA6PCR PB6PCR PC6PCR PD6PCR PE6PCR PA6ODR CHR BLK Bit 6 RIE Bit 6 RDRF RDRF Bit 6 CHR BLK Bit 6 RIE Bit 6 RDRF RDRF Bit 6 CCLR1 IOB2 IOD2 Bit 5 PA5PCR PB5PCR PC5PCR PD5PCR PE5PCR P35ODR PA5ODR PE PE Bit 5 TE Bit 5 ORER ORER Bit 5 PE PE Bit 5 TE Bit 5 ORER ORER Bit 5 CCLR0 BFB IOB1 IOD1 Bit 4 PA4PCR PB4PCR PC4PCR PD4PCR PE4PCR P34ODR PA4ODR O/E O/E Bit 4 RE Bit 4 FER ERS Bit 4 O/E O/E Bit 4 RE Bit 4 FER ERS Bit 4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 3 PA3PCR PB3PCR PC3PCR PD3PCR PE3PCR P33ODR PA3ODR STOP BCP1 Bit 3 MPIE Bit 3 PER PER Bit 3 SDIR STOP BCP1 Bit 3 MPIE Bit 3 PER PER Bit 3 SDIR CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 2 PA2PCR PB2PCR PC2PCR PD2PCR PE2PCR P32ODR PA2ODR MP BCP0 Bit 2 TEIE Bit 2 TEND TEND Bit 2 SINV MP BCP0 Bit 2 TEIE Bit 2 TEND TEND Bit 2 SINV TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 1 PA1PCR PB1PCR PC1PCR PD1PCR PE1PCR P31ODR PA1ODR CKS1 CKS1 Bit 1 CKE1 Bit 1 MPB MPB Bit 1 CKS1 CKS1 Bit 1 CKE1 Bit 1 MPB MPB Bit 1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 0 PA0PCR PB0PCR PC0PCR PD0PCR PE0PCR P30ODR PA0ODR CKS0 CKS0 Bit 0 CKE0 Bit 0 MPBT MPBT Bit 0 SMIF CKS0 CKS0 Bit 0 CKE0 Bit 0 MPBT MPBT Bit 0 SMIF TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Module PORT PA7PCR PB7PCR PC7PCR PD7PCR PE7PCR PA7ODR C/A GM Bit 7 TIE Bit 7 TDRE TDRE Bit 7 BCP2 C/A GM Bit 7 TIE Bit 7 4 SCI_3, Smartcard interface_3 5 5 SCI_4, Smartcard interface_4 SMR_4*5 BRR_4 SCR_4 TDR_4 SSR_4* SSR_4* RDR_4 SCMR_4 TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TDRE TDRE Bit 7 BCP2 CCLR2 IOB3 IOD3 TTGE 5 TPU_3 Rev. 1.00 Sep. 19, 2008 Page 1149 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 TCNT_3 Bit 15 Bit 7 TGRA_3 Bit 15 Bit 7 TGRB_3 Bit 15 Bit 7 TGRC_3 Bit 15 Bit 7 TGRD_3 Bit 15 Bit 7 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 IOB3 TTGE TCFD Bit 15 Bit 7 TGRA_4 Bit 15 Bit 7 TGRB_4 Bit 15 Bit 7 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 IOB3 TTGE TCFD Bit 15 Bit 7 TGRA_5 Bit 15 Bit 7 TGRB_5 Bit 15 Bit 7 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPU_5 TPU_4 Module TPU_3 Rev. 1.00 Sep. 19, 2008 Page 1150 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 FLMCR1 Bit 6 CBIDB Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module FMCMDE FLASH N DFPR FLMSTR ABWCR ASTCR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR CSACRH CSACRL BROMCRH BROMCRL BCR ABW7 AST7 RDN7 CSXH7 CSXT7 BSRM0 BSRM1 BRLE ABW6 AST6 W72 W52 W32 W12 RDN6 CSXH6 CSXT6 BSTS02 BSTS12 BREQOE RAST RCDM CMIE CBRM Bit 6 Bit 6 FMERSF ABW5 AST5 W71 W51 W31 W11 RDN5 CSXH5 CSXT5 BSTS01 BSTS11 DDS TPC1 RCW1 RLW1 Bit 5 Bit 5 FMERCF ABW4 AST4 W70 W50 W30 W10 RDN4 CSXH4 CSXT4 BSTS00 BSTS10 IDLC CAST EDDS TPC0 RCW0 RLW0 Bit 4 Bit 4 FMPRSF ABW3 AST3 RDN3 CSXH3 CSXT3 ICIS1 SDWCD CKSPE SLFRF Bit 3 Bit 3 FMPRCF ABW2 AST2 W62 W42 W22 W02 RDN2 CSXH2 CSXT2 ICIS0 ICIS2 RMTS2 MXC2 RTCK2 TPCS2 Bit 2 Bit 2 ABW1 AST1 W61 W41 W21 W01 RDN1 CSXH1 CSXT1 BSWD01 BSWD11 WDBE RMTS1 MXC1 RCD1 RDXC1 RTCK1 TPCS1 Bit 1 Bit 1 FMDBPT0 FMRDY ABW0 AST0 W60 W40 W20 W00 RDN0 CSXH0 CSXT0 BSWD00 BSWD10 WAITE ADDEX RMTS0 MXC0 RCD0 RDXC0 RTCK0 TPCS0 Bit 0 Bit 0 BSC MPXCR DRAMCR MPXE OEE BE DRACCR DRMI REFCR CMF RFSHE RTCNT RTCOR Bit 7 Bit 7 Rev. 1.00 Sep. 19, 2008 Page 1151 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 MAR_0AH Bit 15 Bit 7 MAR_0AL Bit 15 Bit 7 IOAR_0A Bit 15 Bit 7 ETCR_0A Bit 15 Bit 7 MAR_0BH Bit 15 Bit 7 MAR_0BL Bit 15 Bit 7 IOAR_0B Bit 15 Bit 7 ETCR_0B Bit 15 Bit 7 MAR_1AH Bit 15 Bit 7 MAR_1AL Bit 15 Bit 7 IOAR_1A Bit 15 Bit 7 ETCR_1A Bit 15 Bit 7 MAR_1BH Bit 7 MAR_1BL Bit 15 Bit 7 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 6 Bit 14 Bit 6 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 5 Bit 13 Bit 5 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 4 Bit 12 Bit 4 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 3 Bit 11 Bit 3 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 2 Bit 10 Bit 2 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 1 Bit 9 Bit 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 0 Bit 8 Bit 0 Module DMAC Rev. 1.00 Sep. 19, 2008 Page 1152 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 IOARV1B Bit 15 Bit 7 ETCR_1B Bit 15 Bit 7 DMAWER DMATCR DMACR_0A* DMACR_0A* DMACR_0B* 2 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 DTID SAID DTID DAID DTID SAID DTID DAID FAE0 FAE0 DTE1A DTE1 DTCEA6 DTCEB6 DTCEC6 DTCED6 DTCEE6 DTCEF6 DTCEG6 DTCEH6 DTCEI6 DTVEC6 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 TEE1 RPE SAIDE RPE DAIDE RPE SAIDE RPE DAIDE SAE1 DTE0B DTME0 DTCEA5 DTCEB5 DTCEC5 DTCED5 DTCEE5 DTCEF5 DTCEG5 DTCEH5 DTCEI5 DTVEC5 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 TEE0 DTDIR BLKDIR DTDIR DTDIR BLKDIR DTDIR SAE0 DTE0A DTE0 DTCEA4 DTCEB4 DTCEC4 DTCED4 DTCEE4 DTCEF4 DTCEG4 DTCEH4 DTCEI4 DTVEC4 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 WE1B DTF3 BLKE DTF3 DTF3 DTF3 BLKE DTF3 DTF3 DTA1B DTA1 DTIE1B DTIE1B DTCEA3 DTCEB3 DTCEC3 DTCED3 DTCEE3 DTCEF3 DTCEG3 DTCEH3 DTCEI3 DTVEC3 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 WE1A DTF2 DTF2 DTF2 DTF2 DTF2 DTF2 DTA1A DTIE1A DTIE1A DTCEA2 DTCEB2 DTCEC2 DTCED2 DTCEE2 DTCEF2 DTCEG2 DTCEH2 DTCEI2 DTVEC2 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 WE0B DTF1 DTF1 DTF1 DTF1 DTF1 DTF1 DTA0B DTA0 DTIE0B DTIE0B DTCEA1 DTCEB1 DTCEC1 DTCED1 DTCEE1 DTCEF1 DTCEG1 DTCEH1 DTCEI1 DTVEC1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 WE0A DTF0 DTF0 DTF0 DTF0 DTF0 DTF0 DTA0A DTIE0A DTIE0A DTCEA0 DTCEB0 DTCEC0 DTCED0 DTCEE0 DTCEF0 DTCEG0 DTCEH0 DTCEI0 DTVEC0 Module DMAC DTSZ DTSZ DTSZ 3 2 DMACR_0B*3 DMACR_1A*2 DTSZ DMACR_1A* DMACR_1B* DMACR_1B* DMABCRH* DMABCRH* DMABCRL* 2 3 DTSZ DTSZ FAE1 FAE1 DTE1B DTME1 DTCEA7 DTCEB7 DTCEC7 DTCED7 DTCEE7 DTCEF7 DTCEG7 DTCEH7 DTCEI7 DTVEC7 2 3 3 2 DMABCRL*3 DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTCERH DTCERI DTVECR DTC Rev. 1.00 Sep. 19, 2008 Page 1153 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 INTCR IER IRQ15E IRQ7E ISR IRQ15F IRQ7F SBYCR SCKCR SYSCR MDCR MSTPCRH MSTPCRL SSBY PSTOP ACSE MSTP7 Bit 6 IRQ14E IRQ6E IRQ14F IRQ6F OPE MSTP14 MSTP6 MSTP30 MSTP22 G3CMS0 G2INV NDER14 NDER6 POD14 POD6 NDR14 NDR6 NDRL14 P16 P26 P46 P96 Bit 5 INTM1 IRQ13E IRQ5E IRQ13F IRQ5F SDPSTP MACS MSTP13 MSTP5 MSTP29 MSTP21 G2CMS1 G1INV NDER13 NDER5 POD13 POD5 NDR13 NDR5 NDRL13 P15 P25 P35 P45 P65 P85 P95 Bit 4 INTM0 IRQ12E IRQ4E IRQ12F IRQ4F MSTP12 MSTP4 MSTP28 MSTP20 G2CMS0 G0INV NDER12 NDER4 POD12 POD4 NDR12 NDR4 NDRL12 P14 P24 P34 P44 P64 P84 P94 Bit 3 NMIEG IRQ11E IRQ3E IRQ11F IRQ3F STS3 STCS FLSHE MSTP11 MSTP3 MSTP27 MSTP19 G1CMS1 G3NOV NDER11 NDER3 POD11 POD3 NDR11 NDR3 NDR11 P13 P23 P33 P43 P53 P63 P83 P93 Bit 2 IRQ10E IRQ2E IRQ10F IRQ2F STS2 MDS2 MSTP10 MSTP2 MSTP26 MSTP18 G1CMS0 G2NOV NDER10 NDER2 POD10 POD2 NDR10 NDR2 NDR10 P12 P22 P32 P42 P52 P62 P82 P92 Bit 1 IRQ9E IRQ1E IRQ9F IRQ1F STS1 EXPE MDS1 MSTP9 MSTP1 MSTP25 MSTP17 STC1 G0CMS1 G1NOV NDER9 NDER1 POD9 POD1 NDR9 NDR1 NDR9 P11 P21 P31 P41 P51 P61 P81 P91 Bit 0 IRQ8E IRQ0E IRQ8F IRQ0F STS0 RAME MDS0 MSTP8 MSTP0 MSTP24 MSTP16 STC0 G0CMS0 G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 NDR8 P10 P20 P30 P40 P50 P60 P80 P90 PORT PPG SYSTEM Module INT EXMSTPCRH MSTP31 EXMSTPCRL MSTP23 PLLCR PCR PMR NDERH NDERL PODRH PODRL NDRHH*6 NDRLH*6 NDRHL*6 NDRLL*6 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT8 PORT9 G3CMS1 G3INV NDER15 NDER7 POD15 POD7 NDR15 NDR7 NDRL15 P17 P27 P47 P97 Rev. 1.00 Sep. 19, 2008 Page 1154 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR P5DR P6DR P8DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PORTH PORTJ PHDR PJDR PHDDR PJDDR SMR_0* SMR_0* BRR_0 SCR_0 TDR_0 4 Bit 6 PA6 PB6 PC6 PD6 PE6 PF6 PG6 P16DR P26DR PA6DR PB6DR PC6DR PD6DR PE6DR PF6DR PG6DR CHR BLK Bit 6 RIE Bit 6 Bit 5 PA5 PB5 PC5 PD5 PE5 PF5 PG5 P15DR P25DR P35DR P65DR P85DR PA5DR PB5DR PC5DR PD5DR PE5DR PF5DR PG5DR PE PE Bit 5 TE Bit 5 Bit 4 PA4 PB4 PC4 PD4 PE4 PF4 PG4 P14DR P24DR P34DR P64DR P84DR PA4DR PB4DR PC4DR PD4DR PE4DR PF4DR PG4DR O/E O/E Bit 4 RE Bit 4 Bit 3 PA3 PB3 PC3 PD3 PE3 PF3 PG3 P13DR P23DR P33DR P53DR P63DR P83DR PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR PG3DR PH3 PH3DR PH3DDR STOP BCP1 Bit 3 MPIE Bit 3 Bit 2 PA2 PB2 PC2 PD2 PE2 PF2 PG2 P12DR P22DR P32DR P52DR P62DR P82DR PA2DR PB2DR PC2DR PD2DR PE2DR PF2DR PG2DR PH2 PJ2 PH2DR PH2DDR MP BCP0 Bit 2 TEIE Bit 2 Bit 1 PA1 PB1 PC1 PD1 PE1 PF1 PG1 P11DR P21DR P31DR P51DR P61DR P81DR PA1DR PB1DR PC1DR PD1DR PE1DR PF1DR PG1DR PH1 PJ1 PH1DR PJ1DR PH1DDR PJ1DDR CKS1 CKS1 Bit 1 CKE1 Bit 1 Bit 0 PA0 PB0 PC0 PD0 PE0 PF0 PG0 P10DR P20DR P30DR P50DR P60DR P80DR PA0DR PB0DR PC0DR PD0DR PE0DR PF0DR PG0DR PH0 PJ0 PH0DR PJ0DR PH0DDR PJ0DDR CKS0 CKS0 Bit 0 CKE0 Bit 0 Module PORT PA7 PB7 PC7 PD7 PE7 PF7 P17DR P27DR PA7DR PB7DR PC7DR PD7DR PE7DR PF7DR C/A GM Bit 7 TIE Bit 7 SCI_0, Smart card interface_0 5 Rev. 1.00 Sep. 19, 2008 Page 1155 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 SSR_0* 4 Bit 6 RDRF RDRF Bit 6 CHR BLK Bit 6 RIE Bit 6 RDRF RDRF Bit 6 CHR BLK Bit 6 RIE Bit 6 RDRF RDRF Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 Bit 5 ORER ORER Bit 5 PE PE Bit 5 TE Bit 5 ORER ORER Bit 5 PE PE Bit 5 TE Bit 5 ORER ORER Bit 5 AD7 AD7 AD7 AD7 Bit 4 FER ERS Bit 4 O/E O/E Bit 4 RE Bit 4 FER ERS Bit 4 O/E O/E Bit 4 RE Bit 4 FER ERS Bit 4 AD6 AD6 AD6 AD6 Bit 3 PER PER Bit 3 SDIR STOP BCP1 Bit 3 MPIE Bit 3 PER PER Bit 3 SDIR STOP BCP1 Bit 3 MPIE Bit 3 PER PER Bit 3 SDIR AD5 AD5 AD5 AD5 Bit 2 TEND TEND Bit 2 SINV MP BCP0 Bit 2 TEIE Bit 2 TEND TEND Bit 2 SINV MP BCP0 Bit 2 TEIE Bit 2 TEND TEND Bit 2 SINV AD4 AD4 AD4 AD4 Bit 1 MPB MPB Bit 1 CKS1 CKS1 Bit 1 CKE1 Bit 1 MPB MPB Bit 1 CKS1 CKS1 Bit 1 CKE1 Bit 1 MPB MPB Bit 1 AD3 AD3 AD3 AD3 Bit 0 MPBT MPBT Bit 0 SMIF CKS0 CKS0 Bit 0 CKE0 Bit 0 MPBT MPBT Bit 0 SMIF CKS0 CKS0 Bit 0 CKE0 Bit 0 MPBT MPBT Bit 0 SMIF AD2 AD2 AD2 AD2 Module SCI_0, Smart card interface_0 TDRE TDRE Bit 7 BCP2 C/A GM Bit 7 TIE Bit 7 TDRE TDRE Bit 7 BCP2 C/A GM Bit 7 TIE Bit 7 SSR_0*5 RDR_0 SCMR_0 SMR_1* SMR_1* BRR_1 SCR_1 TDR_1 SSR_1*4 SSR_1*5 RDR_1 SCMR_1 SMR_2* SMR_2* BRR_2 SCR_2 TDR_2 SSR_2* SSR_2* RDR_2 SCMR_2 ADDRA 4 4 4 SCI_1, Smart card interface_1 5 SCI_2, Smart card interface_2 5 TDRE TDRE Bit 7 BCP2 AD9 AD1 5 A/D_0 ADDRB AD9 AD1 ADDRC AD9 AD1 ADDRD AD9 AD1 Rev. 1.00 Sep. 19, 2008 Page 1156 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 ADDRE AD9 AD1 ADDRF AD9 AD1 ADDRG AD9 AD1 ADDRH AD9 AD1 ADCSR ADCR DADR2 DADR3 DACR23 TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCCR0 TCCR1 TCSR TCNT RSTCSR TSTR TSYR ADF TRGS1 Bit 7 Bit 7 DAOE1 CMIEB CMIEB CMFB CMFB Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 OVF Bit 7 WOVF Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 Bit 6 Bit 6 DAOE0 CMIEA CMIEA CMFA CMFA Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 WT/IT Bit 6 RSTE Bit 5 AD7 AD7 AD7 AD7 ADST SCANE Bit 5 Bit 5 DAE OVIE OVIE OVF OVF Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 TME Bit 5 CST5 SYNC5 Bit 4 AD6 AD6 AD6 AD6 SCANS Bit 4 Bit 4 CCLR1 CCLR1 ADTE Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 CST4 SYNC4 Bit 3 AD5 AD5 AD5 AD5 CH3 CKS1 Bit 3 Bit 3 CCLR0 CCLR0 OS3 OS3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 TMRIS TMRIS Bit 3 CST3 SYNC3 Bit 2 AD4 AD4 AD4 AD4 CH2 CKS0 Bit 2 Bit 2 CKS2 CKS2 OS2 OS2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 CKS2 Bit 2 CST2 SYNC2 Bit 1 AD3 AD3 AD3 AD3 CH1 Bit 1 Bit 1 CKS1 CKS1 OS1 OS1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 ICKS1 ICKS1 CKS1 Bit 1 CST1 SYNC1 Bit 0 AD2 AD2 AD2 AD2 CH0 Bit 0 Bit 0 CKS0 CKS0 OS0 OS0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 ICKS0 ICKS0 CKS0 Bit 0 CST0 SYNC0 TPU 8-bit TMR WDT TMR_0 TMR_1 D/A Module A/D_0 Rev. 1.00 Sep. 19, 2008 Page 1157 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 PFCR3 PFCR4 PFCR5 TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 WAITS SSO0S1 CCLR2 IOB3 IOD3 TTGE Bit 15 Bit 7 TGRA_0 Bit 15 Bit 7 TGRB_0 Bit 15 Bit 7 TGRC_0 Bit 15 Bit 7 TGRD_0 Bit 15 Bit 7 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 IOB3 TTGE TCFD Bit 15 Bit 7 TGRA_1 Bit 15 Bit 7 TGRB_1 Bit 15 Bit 7 Bit 6 PPGS BREQS SSO0S0 CCLR1 IOB2 IOD2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 5 TPUS BACKS SSI0S1 CCLR0 BFB IOB1 IOD1 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 4 TMRS Bit 3 Bit 2 Bit 1 RXD4S SCS0S1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 0 SCK4S SCS0S0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPU_1 TPU_0 Module PORT BREQOS ADTRG0S TXD4S SSI0S0 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 SSCK0S1 SSCK0S0 CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Rev. 1.00 Sep. 19, 2008 Page 1158 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation Bit 7 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 IOB3 TTGE TCFD Bit 15 Bit 7 TGRA_2 Bit 15 Bit 7 TGRB_2 Bit 15 Bit 7 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Module TPU_2 Notes: 1. Loaded in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 2. For short address mode 3. For full address mode 4. For normal mode 5. For smart card interface mode 6. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D. 7. Not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 1159 of 1270 REJ09B0466-0100 Section 25 List of Registers 25.3 Register Register States in Each Operating Mode HighReset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Speed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU A/D_1 DTC INT SYSTEM Module DTC Clock Stop Standby Abbreviation MRA SAR MRB DAR CRA RMMSTPCRH RMMSTPCRL USPLLCR IPRL IPRM IPRN DTCERI DTCCR ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 TSTRB TSYRB Rev. 1.00 Sep. 19, 2008 Page 1160 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation TCR_6 TMDR_6 TIORH_6 TIORL_6 TIER_6 TSR_6 TCNT_6 TGRA_6 TGRB_6 TGRC_6 TGRD_6 TCR_7 TMDR_7 TIOR_7 TIER_7 TSR_7 TCNT_7 TGRA_7 TGRB_7 TCR_8 TMDR_8 TIOR_8 TIER_8 TSR_8 TCNT_8 TGRA_8 TGRB_8 TCR_9 TMDR_9 TIORH_9 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_9 TPU_8 TPU_7 Module TPU_6 Clock Stop Standby Rev. 1.00 Sep. 19, 2008 Page 1161 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation TIORL_9 TIER_9 TSR_9 TCNT_9 TGRA_9 TGRB_9 TGRC_9 TGRD_9 TCR_10 TMDR_10 TIOR_10 TIER_10 TSR_10 TCNT_10 TGRA_10 TGRB_10 TCR_11 TMDR_11 TIOR_11 TIER_11 TSR_11 TCNT_11 TGRA_11 TGRB_11 P1ODR P2ODR P5ODR P6ODR P8ODR PBODR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PORT TPU_11 TPU_10 Module TPU_9 Clock Stop Standby Rev. 1.00 Sep. 19, 2008 Page 1162 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation PCODR PDODR PEODR PFODR PGODR PHODR PJODR ICCRA_0 ICCRB_0 ICMR_0 ICIER_0 ICSR_0 SAR_0 ICDRT_0 ICDRR_0 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 ICCRA_2 ICCRB_2 ICMR_2 ICIER_2 ICSR_2 SAR_2 ICDRT_2 ICDRR_2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IIC2_2 IIC2_1 IIC2_0 Module PORT Clock Stop Standby Rev. 1.00 Sep. 19, 2008 Page 1163 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation ICCRA_3 ICCRB_3 ICMR_3 ICIER_3 ICSR_3 SAR_3 ICDRT_3 ICDRR_3 SEMR_2 SSCRH SSCRL SSMR SSER SSSR SSCR2 SSTDR0 SSTDR1 SSTDR2 SSTDR3 SSRDR0 SSRDR1 SSRDR2 SSRDR3 EDSAR_2 EDDAR_2 EDTCR_2 EDMDR_2 EDACR_2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized EXDMAC_2* SCI_2 SSU Module IIC2_3 Clock Stop Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 1.00 Sep. 19, 2008 Page 1164 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation EDSAR_3 EDDAR_3 EDTCR_3 EDMDR_3 EDACR_3 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK ITSR SSIER ISCRH ISCRL IrCR_0 P1DDR P2DDR P3DDR P5DDR P6DDR P8DDR PADDR PBDDR PCDDR PDDDR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IrDA PORT INT Module EXDMAC_3* Clock Stop Standby Rev. 1.00 Sep. 19, 2008 Page 1165 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation PEDDR PFDDR PGDDR PFCR0 PFCR1 PFCR2 PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SCMR_3 SMR_4 BRR_4 SCR_4 TDR_4 SSR_4 RDR_4 SCMR_4 TCR_3 TMDR_3 TIORH_3 TIORL_3 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_3 SCI_4 SCI_3 Module PORT Clock Stop Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 1.00 Sep. 19, 2008 Page 1166 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 FLMCR1 DFPR FLMSTR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized FLASH TPU_5 TPU_4 Module TPU_3 Clock Stop Standby Rev. 1.00 Sep. 19, 2008 Page 1167 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation ABWCR ASTCR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR CSACRH CSACRL BROMCRH BROMCRL BCR MPXCR DRAMCR DRACCRH DRACCRL REFCR RTCNT RTCOR MAR_0AH MAR_0AL IOAR_0A ETCR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B MAR_1AH MAR_1AL IOAR_1A Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized DMAC BSC Module BSC Clock Stop Standby Rev. 1.00 Sep. 19, 2008 Page 1168 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B DMABCRH DMABCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTCERH DTVECR INTCR IER ISR SBYCR SCKCR SYSCR MDCR MSTPCRH Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SYSTEM INT DTC Module DMAC Clock Stop Standby Rev. 1.00 Sep. 19, 2008 Page 1169 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation MSTPCRL EXMSTPCRH EXMSTPCRL PLLCR PCR PMR NDERH NDERL PODRH PODRL NDRHH NDRLH NDRHL NDRLL PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT8 PORT9 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PORT PPG Module SYSTEM Clock Stop Standby Rev. 1.00 Sep. 19, 2008 Page 1170 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation P3DR P5DR P6DR P8DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PORTH PHDR PJDR PHDDR PJDDR SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_1 SCI_0 Module PORT Clock Stop Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 1.00 Sep. 19, 2008 Page 1171 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR DADR2 DADR3 DACR23 TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_0 TMR_1 D/A A/D_0 Module SCI_2 Clock Stop Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 1.00 Sep. 19, 2008 Page 1172 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation TCCR_0 TCCR_1 TCSR TCNT RSTCSR TSTR TSYR PFCR3 PFCR4 PFCR5 TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_1 TPU_0 PORT TPU WDT Module TMR Clock Stop Standby Rev. 1.00 Sep. 19, 2008 Page 1173 of 1270 REJ09B0466-0100 Section 25 List of Registers Register Abbreviation TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed Clock Division Sleep Module Stop All Module Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module TPU_2 Clock Stop Standby Note: * Not supported by the H8S/2424 Group. Rev. 1.00 Sep. 19, 2008 Page 1174 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Section 26 Electrical Characteristics 26.1 Electrical Characteristics for H8S/2426 Group and H8S/2426R Group Absolute Maximum Ratings 26.1.1 Table 26.1 lists the absolute maximum ratings. Table 26.1 Absolute Maximum Ratings Item Power supply voltage Symbol VCC PLLVCC Input voltage (except ports 4, 9, and 2, P32 Vin to P35, P50 and P51, and PJ0 to PJ2) Input voltage (ports 2, P50 and P51, P32 to P35, and PJ0 to PJ2) Input voltage (ports 4 and 9) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Vin Vin Vref AVCC VAN Topr -0.3 to VCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 Regular specifications: -20 to +75* Wide-range specifications: -40 to +85* Storage temperature Caution: Note: * Tstg -55 to +125 V V V V V V C C C Value -0.3 to +4.3 Unit V Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Ranges of operating temperature when flash memory is programmed/erased: Regular specifications: 0 to +75C Wide-range specifications: 0 to +85C Rev. 1.00 Sep. 19, 2008 Page 1175 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.1.2 DC Characteristics Table 26.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min. Typ. Max. VCC x 0.7 Test Unit Conditions V V V Schmitt Ports 1 and 2, VCC x 0.2 VT- 2 trigger input P32 to P35* , + VT voltage P50 to P53*2, + - 2 2 ports 6* and 8* , VT - VT VCC x 0.07 2 PA4 to PA7* , 2 ports B* and C*2, 2 2 PF1* , PF2* , 2 2 PH2* , PH3* , 2 2 PJ0* , PJ1* Input high voltage STBY, MD2 to MD0 RES, NMI, FWE EXTAL P14 to P17* , P24 to P26*6, port 3, 3 P50 to P53* , ports 6 and 8*3, 3 ports A to J* Ports 4 and 9 Input low voltage RES, STBY, MD2 to MD0, EMLE NMI, EXTAL Ports 3, 5, and 6, port 8, 3 ports A to J* , 5 P14 to P17* , 6 P24 to P26* Ports 4 and 9 VIL 5 VIH VCC x 0.9 VCC x 0.9 VCC x 0.7 2.2 VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 V V V V 2.2 -0.3 AVCC +0.3 VCC x 0.1 V V -0.3 -0.3 VCC x 0.2 VCC x 0.2 V V -0.3 AVCC x 0.2 V Rev. 1.00 Sep. 19, 2008 Page 1176 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item Output high All output pins voltage Symbol VOH Min. VCC - 0.3 VCC - 0.5 VCC - 0.8 Typ. Max. 0.4 0.4 Test Unit Conditions V V V V V IOH = -200 A IOH = -1 mA IOH = -2 mA IOL = 4.0 mA IOL = 8.0 mA Output low voltage All output pins P26 and P27* , P32 to P35*4, P50 and P51*4 RES STBY, NMI, MD2 to MD0 Ports 4 and 9 4 VOL Input leakage current |Iin| 10.0 1.0 1.0 A A A Vin = 0.5 to VCC -0.5 V Vin = 0.5 to AVCC -0.5 V Notes: Pins of port 2, P32 to P35, P50 and P51, and PJ0 to PJ2 are 5-V tolerant. 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. When used as IRQ, TIOC, TCLK, TMRI, SCL, or SDA. 3. When used as other than IRQ, TIOC, TCLK, TMRI, SCL, or SDA. 4. When used as SCL or SDA. 5. When used as SSO, SSI, SSCK, or SCS. 6. When used as RxD, WAIT, or ADTRG1. Rev. 1.00 Sep. 19, 2008 Page 1177 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Table 26.3 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Three-state Ports 1 to 3, leakage current P50 to P53, (off state) ports 6 and 8, ports A to I Input pull-up MOS current Input capacitance Ports A to E Symbol | ITSI | Min. Typ. Max. 1.0 Unit A Test Conditions Vin = 0.5 to VCC -0.5 V -Ip 10 300 A VCC = 3.0 to 3.6 V Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C RES NMI All input pins except RES and NMI Cin 30 30 18 pF pF pF Supply current*2 Normal operation ICC*4 Sleep mode Standby mode* 3 55 (3.3 V) 35 (3.3 V) 20 80 0.5 (3.3 V) 0.01 0.5 (3.3 V) 0.01 75 45 2.0 5.0 6.0 5.0 0.8 20 mA mA A A mA A mA A V V ms/V f = 33 MHz f = 33 MHz Ta 50C 50C < Ta When channel 1 is in use When channel 1 is in use Analog power supply current During A/D and D/A conversion Idle AICC Reference power supply current During A/D and D/A conversion Idle AICC RAM standby voltage VCC start voltage*5 VCC rising slope * 5 VRAM VCC start SVCC 2.5 Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. Rev. 1.00 Sep. 19, 2008 Page 1178 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 2. Current consumption values are for VIHmin = VCC -0.2 V and VILmax = 0.2 V with all output pins unloaded and all input pull-up MOSs in the off state. 3. The values are for VRAM VCC < 3.0 V, VIHmin = VCC x 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 32 (mA) + 1.3 (mA/(MHz)) x f (normal operation) ICCmax = 18 (mA) + 0.8 (mA/(MHz)) x f (sleep mode) 5. Applied when RES is low at power-on. Table 26.4 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) Symbol All output pins IOL except the ICC pins ICC output pins Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: Note: * Total of all output pins All output pins Total of all output pins IOL IOL -IOH -IOH Min. Typ. Max. 4.0 8.0 80 2.0 40 Unit mA mA mA mA mA To protect the LSI's reliability, do not exceed the output current values in table 26.30. When the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. Rev. 1.00 Sep. 19, 2008 Page 1179 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.1.3 AC Characteristics The following shows the timings of the clock, control signals, bus, DMAC, EXDMAC, and onchip peripheral functions. For the AC characteristic test conditions, see figure 26.1. (1) Clock Timing Table 26.5 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Clock cycle time Clock pulse high width Clock pulse low width Clock rising time Clock falling time Reset oscillation settling time (crystal) Software standby oscillation settling time (crystal) External clock output delay settling time Clock phase difference* Clock pulse high width (SDRAM)* Clock pulse low width (SDRAM)* Clock rising time (SDRAM)* Clock falling time (SDRAM)* Note: * Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT tcdif tSDCH tSDCL tsdcr tsdcf Min. 30.3 10 10 15 5 15 1/4 x tcyc -3 9 9 Max. 125 5 5 1/4 x tcyc +3 5 5 Unit ns ns ns ns ns ms ms ms ns ns ns ns ns Figure 26.5(1) Figure 26.5(2) Figure 26.5(1) Figure 26.4 Figure 26.4 Figure 26.4 Figure 26.4 Figure 26.4 Test Conditions Figure 26.3 Figure 26.3 Supported only by the H8S/2426R Group. Rev. 1.00 Sep. 19, 2008 Page 1180 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 3V RL C=50pF: Ports A to J (except for PH1 when SDRAM is in use.) C=30pF: Ports 1 to 3, P50 to P52, Ports 6 and 8, and PH1 when SDRAM is in use. LSI output pin RL=2.4k RH=12k I/O timing test level 1.5V: (Vcc=3.0 to 3.6V) C RH Note: * Not supported by the H8S/2426 Group. Figure 26.1 Output Load Circuit (2) Control Signal Timing Table 26.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 2 150 10 200 150 10 200 Max. ns Unit ns ms ns Figure 26.7 Test Conditions Figure 26.6 Rev. 1.00 Sep. 19, 2008 Page 1181 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics (3) Bus Timing Table 26.7 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Address delay time Address setup time 1 Address setup time 2 Address setup time 3 Address setup time 4 Address hold time 1 Address hold time 2 Address hold time 3 CS delay time 1 CS delay time 2 CS delay time 3 AS delay time RD delay time 1 RD delay time 2 Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 Read data access time 6 Read data access time 7 Symbol Min. tAD tAS1 tAS2 tAS3 tAS4 tAH1 tAH2 tAH3 tCSD1 tCSD2 tCSD3 tASD tRSD1 tRSD2 tRDS1 tRDS2 tRDH1 tRDH2 tAC1 tAC2 tAC3 tAC4 tAC5 tAC6 tAC7 Max. 20 Test Unit Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figures 26.8 to 26.23, Figures 26.34 and 26.35 0.5 x tcyc -13 1.0 x tcyc -13 1.5 x tcyc -13 2.0 x tcyc -13 0.5 x tcyc -8 1.0 x tcyc -8 1.5 x tcyc -8 15 15 0 0 15 15 20 15 15 15 1.0 x tcyc - 25 ns 1.5 x tcyc - 25 ns 2.0 x tcyc - 25 ns 2.5 x tcyc - 25 ns 1.0 x tcyc - 25 ns 2.0 x tcyc - 25 ns 4.0 x tcyc - 25 ns Rev. 1.00 Sep. 19, 2008 Page 1182 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item Read data access time 8 Counter address read data access time 1 Counter address read data access time 2 Counter address read data access time 3 Counter address read data access time 4 Counter address read data access time 5 Counter address read data access time 6 Multiplexed address delay time Multiplexed address setup time 1 Multiplexed address setup time 2 Multiplexed address hold time AH delay time Symbol Min. tAC8 tAA1 tAA2 tAA3 tAA4 tAA5 tAA6 tMAD tMAS1 tMAS2 tMAH tAHD Max. Test Unit Conditions Figures 26.8 to 26.23, Figures 26.34 and 26.35 3.0 x tcyc - 25 ns 1.0 x tcyc - 25 ns 1.5 x tcyc - 25 ns 2.0 x tcyc - 25 ns 2.5 x tcyc - 25 ns 3.0 x tcyc - 25 ns 4.0 x tcyc - 25 ns 20 ns ns ns ns ns 0.5 x tcyc - 15 1.5 x tcyc - 15 1.0 x tcyc - 15 15 Rev. 1.00 Sep. 19, 2008 Page 1183 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Table 26.8 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time 1 Write data setup time 2 Write data setup time 3 Write data hold time 1 Write data hold time 2 Write data hold time 3 Write command setup time 1 Write command setup time 2 Write command hold time 1 Write command hold time 2 Read command setup time 1 Read command setup time 2 Read command hold time CAS delay time 1 CAS delay time 2 CAS setup time 1 CAS setup time 2 CAS pulse width 1 CAS pulse width 2 CAS precharge time 1 CAS precharge time 2 Symbol tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS1 tWDS2 tWDS3 tWDH1 tWDH2 tWDH3 tWCS1 tWCS2 tWCH1 tWCH2 tRCS1 tRCS2 tRCH tCASD1 tCASD2 tCSR1 tCSR2 tCASW1 tCASW2 tCPW1 tCPW2 Min. 1.0 x tcyc -13 1.5 x tcyc -13 0.5 x tcyc -15 1.0 x tcyc -15 1.5 x tcyc -15 0.5 x tcyc -13 1.0 x tcyc -13 1.5 x tcyc -13 0.5 x tcyc -10 1.0 x tcyc -10 0.5 x tcyc -10 1.0 x tcyc -10 1.5 x tcyc -10 2.0 x tcyc -10 0.5 x tcyc -10 0.5 x tcyc -10 1.5 x tcyc -10 1.0 x tcyc -20 1.5 x tcyc -20 1.0 x tcyc -20 1.5 x tcyc -20 Max. 15 15 23 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 26.8 to 26.23, Figures 26.34 and 26.35 Rev. 1.00 Sep. 19, 2008 Page 1184 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item OE delay time 1*1 OE delay time 2*1 Symbol tOED1 tOED1B tOED2 tOED2B tPCH1 tPCH2 tRPS1 tRPS2 tWTS tWTH tBREQS tBACD tBZD tBRQOD 2 Min. 1.0 x tcyc -20 1.5 x tcyc -20 2.5 x tcyc -20 3.0 x tcyc -20 25 1 30 15 0 2 Max. 15 19 15 19 15 40 25 16.5 16.5 16.5 16.5 19 31.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 26.8 to 26.23, Figures 26.34 and 26.35 Precharge time 1 Precharge time 2 Self-refresh precharge time 1 Self-refresh precharge time 2 WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time Address delay time 2* CS delay time 4* 2 2 Figures 26.22 and 26.23 Figures 26.10, 26.16, and 27.35 Figure 26.24 Figure 26.25 Figure 26.26 Figure 26.26 Figure 26.26 Figures 26.27 and 26.28 Figure 26.26 Figure 26.26 Figure 26.26 Figure 26.26 tAD2 tCSD4 tDQMD DQM delay time* 2 CKE delay time* * 3 tCKED tCKEDB tRDS3 tRDH3 2 Read data setup time 3*2 Read data hold time 3* 2 Write data delay time 2* Write data hold time 4* 2 tWDD tWDH4 Notes: 1. tOED1, and tOED2 correspond to the OE-A, tOED1B, and tOED2B correspond to the OE-B. 2. Supported only by the H8S/2426R Group. 3. tCKED corresponds to the CKE-A, tCKEDB corresponds to the CKE-B. Rev. 1.00 Sep. 19, 2008 Page 1185 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics (4) DMAC and EXDMAC Timing Table 26.9 DMAC and EXDMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 EDREQ setup time EDREQ hold time ETEND delay time EDACK delay time 1 EDACK delay time 2 EDRAK delay time Symbol tDRQS tDRQH tTED tDACD1 tDACD2 tEDRQS tEDRQH tETED tEDACD1 tEDACD2 tEDRKD Min. 25 10 25 10 Max. 18 18 18 18 18 18 18 ns Figure 26.33 ns ns Figure 26.31 Figures 26.29 and 26.30 ns Figure 26.32 ns Figure 26.31 Figures 26.29 and 26.30 Unit ns Test Conditions Figure 26.32 Rev. 1.00 Sep. 19, 2008 Page 1186 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules Table 26.10 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item I/O ports Output data delay time Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock Single-edge pulse width specification Both-edge specification 8-bit timer Timer output delay time Symbol Min. tPWD tPRS tPRH tPOD tTOCD tTICS tTCKWH tTCKWL tTMOD 25 25 25 25 1.5 2.5 25 25 1.5 2.5 4 6 tSCKW tSCKr tSCKf tTXD tRXS tRXH 0.4 40 40 Max. 40 40 40 40 40 0.6 1.5 1.5 40 ns ns ns Figure 26.45 tScyc tcyc Unit ns ns ns ns ns ns ns tcyc tcyc ns ns ns tcyc tcyc ns tcyc Figure 26.43 Figure 26.44 Figure 26.40 Figure 26.42 Figure 26.41 Figure 26.39 Figure 26.37 Figure 26.38 Test Conditions Figure 26.36 Timer clock input setup time tTCKS Timer reset input setup time tTMRS Timer clock input setup time tTMCS Timer clock Single-edge pulse width specification Both-edge specification WDT SCI Overflow output delay time Input clock cycle Asynchronous Synchronous tTMCWH tTMCWL tWOVD tScyc Input clock pulse width Input clock rising time Input clock falling time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) Rev. 1.00 Sep. 19, 2008 Page 1187 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item A/D converter IIC2 Trigger input setup time SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input falling time SCL, SDA input spike pulse removal time SDA input bus free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load SCL, SDA falling time SSU* Clock cycle Master Slave Clock high pulse width Clock low pulse width Clock rising time Clock falling time Data input setup time Data input hold time SCS setup time Master Slave Master Slave Master Slave Master Slave Master Slave Symbol Min. tTRGS tSCL tSCLH tSCLL tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tSf tSUcyc tHI tLO tRISE tFALL tSU tH tLEAD 30 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns pF ns tcyc ns Test Conditions Figure 26.46 Figure 26.47 12 tcyc +600 3 tcyc +300 5 tcyc +300 5 tcyc 3 tcyc 3 tcyc 1 tcyc +20 0 0 4 4 80 80 80 80 25 30 10 10 2.5 2.5 300 1 tcyc 400 300 256 256 20 20 Figures 26.49 to 26.52 ns ns ns ns ns tcyc Rev. 1.00 Sep. 19, 2008 Page 1188 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item SSU* SCS hold time Data output delay time Data output hold time Master Slave Master Slave Master Slave Symbol Min. tLAG tOD tOH tTD tSA tREL 2.5 2.5 0 0 2.5 2.5 Max. 40 40 1 1 Unit tcyc ns Test Conditions Figures 26.49 to 26.52 ns Continuous Master transmit delay time Slave Slave access time Slave out release time Note * tcyc tcyc tcyc Figures 26.51 and 26.52 SSU: Synchronous serial communication unit 26.1.4 A/D Conversion Characteristics Table 26.11 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Min. 10 4.0* Typ. 10 Max. 10 15 5 5.5 5.5 5.5 0.5 6.0 Unit Bit s pF k LSB LSB LSB LSB LSB For 40 states at ADCLK = 10 MHz. Rev. 1.00 Sep. 19, 2008 Page 1189 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.1.5 D/A Conversion Characteristics Table 26.12 D/A Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Resolution Conversion time Absolute accuracy Min. 8 Typ. 8 2.0 Max. 8 10 3.0 2.0 Unit Bit s LSB LSB 15 pF capacitive load 2 M resistive load 4 M resistive load Test Conditions Rev. 1.00 Sep. 19, 2008 Page 1190 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.1.6 Flash Memory Characteristics Table 26.13 Flash Memory Characteristics Conditions: VCC = AVCC = 3.0 to 3.6V, VSS = AVSS = 0V, Ta= 0C to + 75C Test Symbol conditions Applicable area Standard value Min. 2 Unit Max. s Times Item Programming and erase 1 count* Programming time (per 4 bytes) Erase time (per 1 block) Typ. 3 Programming ROM 100* Data flash area* 3 TBD* 150 300* 300 300* 3 3 Programming ROM Data flash area* 3 3.6 V ms Programming ROM Data flash area* 3 Programming and erase voltage Read voltage Programming ROM 3.0 Data flash area* 3 Programming ROM 3.0 Data flash area* 3 3.6 V Access state Programming ROM 1 Data flash area* 3 75 75 State 2 Programming and erase temperature - Programming ROM 0 Data flash area* 3 C 0 Rev. 1.00 Sep. 19, 2008 Page 1191 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Notes: 1. When programming is to be performed multiple times on a system, reduce the effective number of programming operations by shifting the writing addresses in sequence and so on until the remaining blank area is as small as possible and only then erasing the entire block once. For example, if sets of 16 bytes are being programmed, erasing the block once after programming the maximum number of sets (256) minimizes the effective number of programming operations. We recommend keeping information on the number of times erasure is performed for each block, and setting up the limit on the number of times. 2. If an erase error occurs during erasure, execute the clear status command and then the erase command at least 3 times until the erase does not recur. *1. Determination of the number of times for programming /erasure operations. Number of times programming / erasure is performed in each block. When the number of times for programming / erasure operations is n (n = 100), data can be erased n times in each block. For example, if programming of 4 bytes is done 1024 times, each at a different address in a 4kbyte per block, and the block is then erased, this counts as programming / erasure one time. However, programming of any location in a block multiple times is not possible (overwriting is prohibited). *2. This is the number of times for which all electrical characteristics are guaranteed. *3 Values for the data flush are in planning. Rev. 1.00 Sep. 19, 2008 Page 1192 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.2 26.2.1 Electrical Characteristics for H8S/2424 Group Absolute Maximum Ratings Table 26.14 lists the absolute maximum ratings. Table 26.14 Absolute Maximum Ratings Item Power supply voltage Symbol VCC PLLVCC Input voltage (except ports 4, 9, and 2, P32 Vin to P35, P50 and P51, and P81 and P83) Input voltage (port 2, P50 and P51, P32 to Vin P35, and P81 and P83) Input voltage (ports 4 and 9) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Vin Vref AVCC VAN Topr -0.3 to VCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 Regular specifications: -20 to +75* Wide-range specifications: -40 to +85* Storage temperature Caution: Note: * Tstg -55 to +125 V V V V V V C C C Value -0.3 to +4.3 Unit V Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Ranges of operating temperature when flash memory is programmed/erased: Regular specifications: 0 to +75C Wide-range specifications: 0 to +85C Rev. 1.00 Sep. 19, 2008 Page 1193 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.2.2 DC Characteristics Table 26.15 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Schmitt Ports 1 and 2, trigger input P32 to P35*2, voltage P50 to P53*2, 2 port 8* , PA4 to 2 2 PA7* , ports B* 2 2 and C* , PF1* , 2 2 PF2* , P81* 2 and P83* Input high voltage STBY, MD2 to MD0 RES, NMI, EMLE EXTAL P14 to P17* , P24 to P26*6, port 3, 3 P50 to P53* , 3 port 8* , ports A to G*3 Ports 4 and 9 Input low voltage RES, STBY, MD2 to MD0, EMLE NMI, EXTAL Ports 3, 5, and 6, port 8, ports A to J*3, P14 to P17*5, 6 P24 to P26* Ports 4 and 9 VIL 5 Symbol VT- VT + + - Min. VCC x 0.2 VCC x 0.07 Typ. Max. VCC x 0.7 Test Unit Conditions V V V VT - VT VIH VCC x 0.9 VCC +0.3 V VCC x 0.7 2.2 VCC +0.3 VCC +0.3 V V 2.2 -0.3 AVCC +0.3 VCC x 0.1 V V -0.3 -0.3 VCC x 0.2 VCC x 0.2 V V -0.3 AVCC x 0.2 V Rev. 1.00 Sep. 19, 2008 Page 1194 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item Output high All output pins voltage Symbol VOH Min. VCC - 0.3 VCC - 0.5 VCC - 0.8 Typ. Max. 0.4 0.4 Test Unit Conditions V V V V V IOH = -200 A IOH = -1 mA IOH = -2 mA IOL = 4.0 mA IOL = 8.0 mA Output low voltage All output pins P26 and P27* P32 to P35*4, P50 and P51*4 RES STBY, NMI, MD2 to MD0 Port 4, Port 9 4 VOL Input leakage current |Iin| 10.0 1.0 1.0 A A A Vin = 0.5 to VCC -0.5 V Vin = 0.5 to AVCC -0.5 V Notes: Pins of port 2, P32 to P35, P50 and P51, and P81 and P83 are 5-V tolerant. 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. When used as IRQ, TIOC, TCLK, TMRI, SCL, or SDA. 3. When used as other than IRQ, TIOC, TCLK, TMRI, SCL, or SDA. 4. When used as SCL or SDA. 5. When used as SSO, SSI, SSCK, or SCS. 6. When used as RxD, WAIT, or ADTRG1. Rev. 1.00 Sep. 19, 2008 Page 1195 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Table 26.16 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Three-state leakage current (off state) Input pull-up MOS current Input capacitance Ports 1 to 3, P50 to P53, ports 6 and 8, ports A to J Ports A to E Symbol Min. | ITSI | Typ. Max. 1.0 Unit A Test Conditions Vin = 0.5 to VCC -0.5 V -Ip 10 300 A VCC = 3.0 to 3.6 V Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C RES NMI All input pins except RES and NMI Cin 30 30 18 pF pF pF Current consumption*2 Normal operation ICC*4 Sleep mode Standby mode* 3 55 (3.3 V) 35 (3.3 V) 20 80 1.0 (3.3 V) 0.01 0.5 (3.3 V) 0.01 75 45 2.0 5.0 6.0 5.0 0.8 20 mA mA A A mA A mA A V V ms/V f = 33 MHz f = 33 MHz Ta 50C 50C < Ta When channel 1 is in use When channel 1 is in use Analog power supply current During A/D and D/A conversion Idling AICC Reference power supply current During A/D and D/A conversion Idling AICC RAM standby voltage VCC start voltage*5 VCC rising slope * 5 VRAM VCC start SVCC 2.5 Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. Rev. 1.00 Sep. 19, 2008 Page 1196 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 2. Current consumption values are for VIHmin = VCC -0.2 V and VILmax = 0.2 V with all output pins unloaded and all input pull-up MOSs in the off state. 3. The values are for VRAM VCC < 3.0 V, VIHmin = VCC x 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 32 (mA) + 1.3 (mA/(MHz)) x f (normal operation) ICCmax = 18 (mA) + 0.8 (mA/(MHz)) x f (sleep mode) 5. Applied when RES is low at power-on. Table 26.17 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) Symbol All output pins IOL except the ICC pins ICC output pins Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: Note: * Total of all output pins All output pins Total of all output pins IOL IOL -IOH -IOH Min. Typ. Max. 2.0 8.0 80 2.0 40 Unit mA mA mA mA mA To protect the LSI's reliability, do not exceed the output current values in table 26.29. When the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. Rev. 1.00 Sep. 19, 2008 Page 1197 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.2.3 AC Characteristics The following shows the timings of the clock, control signals, bus, DMAC, and on-chip peripheral functions. For the AC characteristic test conditions, see figure 26.1. (1) Clock Timing Table 26.18 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Clock cycle time Clock pulse high width Clock pulse low width Clock rising time Clock falling time Reset oscillation settling time (crystal) Software standby oscillation settling time (crystal) External clock output delay settling time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT Min. 30.3 10 10 15 5 15 Max. 125 5 5 Unit ns ns ns ns ns ms ms ms Figure 26.5(1) Figure 26.5(2) Figure 26.5(1) Test Conditions Figure 26.3 Figure 26.3 Rev. 1.00 Sep. 19, 2008 Page 1198 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 3V RL C=50pF: Ports A to G C=30pF: Ports 1 to 3, P50 to P53, and Port8 LSI output pin RL=2.4k RH=12k I/O timing test level1.5V: (Vcc=3.0 to 3.6V) C RH Figure 26.2 Output Load Circuit (2) Control Signal Timing Table 26.19 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 2 150 10 200 150 10 200 Max. ns Unit ns ms ns Figure 26.7 Test Conditions Figure 26.6 Rev. 1.00 Sep. 19, 2008 Page 1199 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics (3) Bus Timing Table 26.20 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Address delay time Address setup time 1 Address setup time 2 Address setup time 3 Address setup time 4 Address hold time 1 Address hold time 2 Address hold time 3 CS delay time 1 CS delay time 2 CS delay time 3 AS delay time RD delay time 1 RD delay time 2 Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 Read data access time 6 Read data access time 7 Read data access time 8 Symbol tAD tAS1 tAS2 tAS3 tAS4 tAH1 tAH2 tAH3 tCSD1 tCSD2 tCSD3 tASD tRSD1 tRSD2 tRDS1 tRDS2 tRDH1 tRDH2 tAC1 tAC2 tAC3 tAC4 tAC5 tAC6 tAC7 tAC8 Min. 0.5 x tcyc -13 1.0 x tcyc -13 1.5 x tcyc -13 2.0 x tcyc -13 0.5 x tcyc -8 1.0 x tcyc -8 1.5 x tcyc -8 15 15 0 0 Max. 20 15 15 20 15 15 15 1.0 x tcyc - 25 1.5 x tcyc - 25 2.0 x tcyc - 25 2.5 x tcyc - 25 1.0 x tcyc - 25 2.0 x tcyc - 25 4.0 x tcyc - 25 3.0 x tcyc - 25 1.0 x tcyc - 25 1.5 x tcyc - 25 2.0 x tcyc - 25 2.5 x tcyc - 25 3.0 x tcyc - 25 4.0 x tcyc - 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 26.8 to 26.23, Figures 26.34 and 26.35 Counter address read data access time 1 tAA1 Counter address read data access time 2 tAA2 Counter address read data access time 3 tAA3 Counter address read data access time 4 tAA4 Counter address read data access time 5 tAA5 Counter address read data access time 6 tAA6 Rev. 1.00 Sep. 19, 2008 Page 1200 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item Multiplexed address delay time Multiplexed address setup time 1 Multiplexed address setup time 2 Multiplexed address hold time AH delay time Symbol tMAD tMAS1 tMAS2 tMAH tAHD Min. 0.5 x tcyc - 15 1.5 x tcyc - 15 1.0 x tcyc - 15 Max. 20 15 Unit ns ns ns ns ns Test Conditions Figures 26.8 to 26.23, Figures 26.34 and 26.35 Rev. 1.00 Sep. 19, 2008 Page 1201 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Table 26.21 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time 1 Write data setup time 2 Write data setup time 3 Write data hold time 1 Write data hold time 2 Write data hold time 3 Write command setup time 1 Write command setup time 2 Write command hold time 1 Write command hold time 2 Read command setup time 1 Read command setup time 2 Read command hold time CAS delay time 1 CAS delay time 2 CAS setup time 1 CAS setup time 2 CAS pulse width 1 CAS pulse width 2 CAS precharge time 1 CAS precharge time 2 OE delay time 1* OE delay time 2* Symbol tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS1 tWDS2 tWDS3 tWDH1 tWDH2 tWDH3 tWCS1 tWCS2 tWCH1 tWCH2 tRCS1 tRCS2 tRCH tCASD1 tCASD2 tCSR1 tCSR2 tCASW1 tCASW2 tCPW1 tCPW2 tOED1 tOED1B tOED2 tOED2B Min. 1.0 x tcyc -13 1.5 x tcyc -13 0.5 x tcyc -15 1.0 x tcyc -15 1.5 x tcyc -15 0.5 x tcyc -13 1.0 x tcyc -13 1.5 x tcyc -13 0.5 x tcyc -10 1.0 x tcyc -10 0.5 x tcyc -10 1.0 x tcyc -10 1.5 x tcyc -10 2.0 x tcyc -10 0.5 x tcyc -10 0.5 x tcyc -10 1.5 x tcyc -10 1.0 x tcyc -20 1.5 x tcyc -20 1.0 x tcyc -20 1.5 x tcyc -20 Max. 15 15 23 15 15 15 19 15 19 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 26.8 to 26.23, Figures 26.34 and 26.35 Rev. 1.00 Sep. 19, 2008 Page 1202 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item Precharge time 1 Precharge time 2 Symbol tPCH1 tPCH2 Min. 1.0 x tcyc -20 1.5 x tcyc -20 2.5 x tcyc -20 3.0 x tcyc -20 25 1 30 Max. 15 40 25 Unit ns ns Test Conditions Figures 26.8 to 26.23, Figures 26.34 and 26.35 Figures 26.22 and 26.23 Figures 26.10, 26.16, and 26.35 Figure 26.24 Self-refresh precharge time 1 Self-refresh precharge time 2 WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time tRPS1 tRPS2 tWTS tWTH tBREQS tBACD tBZD tBRQOD ns ns ns ns ns ns ns ns Figure 26.25 Note: * tOED1 and tOED2.correspond to OE-A, and tOED1B and tOED2B.correspond to OE-B. (4) DMAC Timing Table 26.22 DMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol tDRQS tDRQH tTED tDACD1 tDACD2 Min. 25 10 Max. 18 18 18 Figure 26.31 Figures 26.29 and 26.30 Unit ns Test Conditions Figure 26.32 Rev. 1.00 Sep. 19, 2008 Page 1203 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules Table 26.23 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item I/O ports Output data delay time Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock Single-edge pulse width specification Both-edge specification 8-bit timer Timer output delay time Symbol Min. tPWD tPRS tPRH tPOD tTOCD tTICS tTCKWH tTCKWL tTMOD 25 25 25 25 1.5 2.5 25 25 1.5 2.5 4 6 tSCKW tSCKr tSCKf tTXD tRXS tRXH 0.4 40 40 Max. 40 40 40 40 40 0.6 1.5 1.5 40 ns ns ns Figure 26.45 tScyc tcyc Unit ns ns ns ns ns ns ns tcyc tcyc ns ns ns tcyc tcyc ns tcyc Figure 26.43 Figure 26.44 Figure 26.40 Figure 26.42 Figure 26.41 Figure 26.39 Figure 26.37 Figure 26.38 Test Conditions Figure 26.36 Timer clock input setup time tTCKS Timer reset input setup time tTMRS Timer clock input setup time tTMCS Timer clock Single-edge pulse width specification Both-edge specification WDT SCI Overflow output delay time Input clock cycle Asynchronous Synchronous tTMCWH tTMCWL tWOVD tScyc Input clock pulse width Input clock rising time Input clock falling time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) Rev. 1.00 Sep. 19, 2008 Page 1204 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item A/D converter IIC2 Trigger input setup time SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA Input falling time Symbol Min. tTRGS tSCL tSCLH tSCLL tSf 30 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns pF ns tcyc ns Test Conditions Figure 26.46 Figure 26.47 12 tcyc +600 3 tcyc +300 5 tcyc +300 5 tcyc 3 tcyc 3 tcyc 1 tcyc +20 0 0 4 4 300 1 tcyc 400 300 256 256 20 20 SCL, SDA Input spike pulse tSP removal time SDA input bus free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load SCL, SDA falling time SSU* Clock cycle Master Slave Clock high pulse width Clock low pulse width Clock rising time Clock falling time Data input setup time Data input hold time SCS setup time Master Slave Master Slave Master Slave tLEAD tH Master Slave Master Slave tRISE tFALL tSU tLO tHI tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tSf tSUcyc Figures 26.49 to 26.52 80 80 80 80 25 30 10 10 2.5 2.5 ns ns ns ns ns tcyc Rev. 1.00 Sep. 19, 2008 Page 1205 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Item SSU* SCS hold time Data output delay time Data output hold time Master Slave Master Slave Master Slave Symbol Min. tLAG tOD tOH tTD tSA tREL 2.5 2.5 0 0 2.5 2.5 Max. 40 40 1 1 Unit tcyc ns Test Conditions Figures 26.49 to 26.52 ns Continuous Master transmit delay time Slave Slave access time Slave out release time Note * tcyc tcyc tcyc Figures 26.51 and 26.52 SSU: Synchronous serial communication unit 26.2.4 A/D Conversion Characteristics Table 26.24 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Min. 10 4.0* Typ. 10 Max. 10 15 5 5.5 5.5 5.5 0.5 6.0 Unit Bit s pF k LSB LSB LSB LSB LSB For 40 states at ADCLK = 10 MHz. Rev. 1.00 Sep. 19, 2008 Page 1206 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.2.5 D/A Conversion Characteristics Table 26.25 D/A Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Resolution Conversion time Absolute accuracy Min. 8 Typ. 8 2.0 Max. 8 10 3.0 2.0 Unit Bit s LSB LSB 15 pF capacitive load 2 M resistive load 4 M resistive load Test Conditions Rev. 1.00 Sep. 19, 2008 Page 1207 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.2.6 Flash Memory Characteristics Table 26.27 Flash Memory Characteristics Conditions: VCC = AVCC = 3.0 to 3.6V, VSS = AVSS = 0V, Ta= 0C to + 75C Test Symbol conditions Applicable area Standard value Min. 2 Unit Max. s Times Item Programming and erase 1 count* Programming time (per 4 bytes) Erase time (per 1 block) Typ. 3 Programming ROM 100* Data flash area* 3 TBD* 150 300* 300 300* 3 3 Programming ROM Data flash area* 3 3.6 V ms Programming ROM Data flash area* 3 Programming and erase voltage Read voltage Programming ROM 3.0 Data flash area* 3 Programming ROM 3.0 Data flash area* 3 3.6 V Access state Programming ROM 1 Data flash area* 3 75 75 State 2 Programming and erase temperature - Programming ROM 0 Data flash area* 3 C 0 Rev. 1.00 Sep. 19, 2008 Page 1208 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Notes: 1. In the system where multiple programming are executed, erase once so as to effectively diminish the programming times after having written with leaving the blank area as least as possible by shifting writing address one by one. For example, if 16 bytes per 1 set is being programmed, erase once after maximum 256 sets of programming has been done, which diminish the effective programming times. Keep the information of the times of erasure and set up the limitation times is recommended. 2. If an erase error is occurred, execute the clear status command -> erase command for at least 3 times until no erase error is occurred. *1. Determination of the number of times the programming /erase operation. Number of times the programming / erase performed in each block. When the number of times the programming / erase is n times (n = 100), data can be erased n times in each block. For example, if 4 bytes programming is done 1024 times, each at a different address in a 4-kbyte per block, and then the block is erased, number of times the programming / erase can be one time. However, programming cannot be done multiple times in the block (overwriting is prohibited). *2. Number of times that ensures all the electrical characteristics. *3 As for the data flush is under planning. Rev. 1.00 Sep. 19, 2008 Page 1209 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.3 26.3.1 Timing Charts Clock Timing The clock timings are shown below. tcyc tCH tCL tCr tCf Figure 26.3 System Clock Timing tcyc tCH tCr tsdcr SDRAM tCf tCL tcdif tsdcf tSDCH tSDCL Figure 26.4 SDRAM Timing Rev. 1.00 Sep. 19, 2008 Page 1210 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 Figure 26.5 (1) Oscillation Settling Timing Oscillator NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down state) Oscillation stabilization time tOSC2 SLEEP instruction Figure 26.5 (2) Oscillation Settling Timing Rev. 1.00 Sep. 19, 2008 Page 1211 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.3.2 Control Signal Timing The control signal timings are shown below. tRESS RES tRESW tRESS Figure 26.6 Reset Input Timing tNMIS tNMIH NMI tNMIW tIRQW IRQi (i = 0 to 15)* tIRQS tIRQH IRQ (edge input) tIRQS IRQ (level input) Note: * SSIER setting is necessary to clear software standby mode. Figure 26.7 Interrupt Input Timing Rev. 1.00 Sep. 19, 2008 Page 1212 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.3.3 Bus Timing The bus timings are shown below. T1 tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 AS tAS1 RD Read (RDNn = 1) D15 to D0 tAS1 RD Read (RDNn = 0) D15 to D0 tAS1 HWR, LWR Write D15 to D0 tDACD1 DACK0, DACK1 tEDACD1 EDACK2, EDACK3 tEDACD2 tDACD2 tWDD tWSW1 tWDH1 tWRD2 tWRD2 tAH1 tAC2 tAA3 tRDS2 tRDH2 tRSD1 tRSD2 tAC5 tAA2 tRDS1 tRDH1 tRSD1 tRSD1 tASD tASD tAH1 T2 Figure 26.8 Basic Bus Timing: Two-State Access Rev. 1.00 Sep. 19, 2008 Page 1213 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics T1 tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 AS tAS1 RD Read (RDNn = 1) D15 to D0 tAS1 RD Read (RDNn = 0) D15 to D0 tAS2 HWR, LWR Write D15 to D0 tWDD tRSD1 tRSD1 tASD T2 T3 tASD tAH1 tRSD1 tAC6 tAA4 tRDS1 tRDH1 tRSD2 tAC4 tAA5 tWRD2 tWRD1 tWDS1 tWSW2 tRDS2 tRDH2 tAH1 tWDH1 tDACD1 DACK0, DACK1 tEDACD1 EDACK2, EDACK3 tDACD2 tEDACD2 Figure 26.9 Basic Bus Timing: Three-State Access Rev. 1.00 Sep. 19, 2008 Page 1214 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics T1 T2 Tw T3 A23 to A0 CS7 to CS0 AS RD Read (RDNn = 1) D15 to D0 RD Read (RDNn = 0) D15 to D0 HWR, LWR Write D15 to D0 tWTS tWTH WAIT tWTS tWTH Figure 26.10 Basic Bus Timing: Three-State Access, One Wait Rev. 1.00 Sep. 19, 2008 Page 1215 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Th tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD AS tAS3 RD Read (RDNn = 1) D15 to D0 tAS3 RD Read (RDNn = 0) D15 to D0 tAS3 HWR, LWR Write D15 to D0 tWDD tWDS2 T1 T2 Tt tASD tAH1 tRSD1 tRSD1 tAH3 tAC5 tRDS1 tRDH1 tRSD1 tRSD2 tAH2 tAC2 tRDS2 tRDH2 tWRD2 tWRD2 tAH3 tWSW1 tWDH3 tDACD1 DACK0, DACK1 tEDACD1 EDACK2, EDACK3 tDACD2 tEDACD2 Figure 26.11 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) Rev. 1.00 Sep. 19, 2008 Page 1216 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Th tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD AS tAS3 RD Read (RDNn = 1) D15 to D0 tAS3 RD Read (RDNn = 0) D15 to D0 tAS4 HWR, LWR Write D15 to D0 tDACD1 DACK0, DACK1 tEDACD1 EDACK2, EDACK3 tWDD T1 T2 T3 Tt tASD tAH1 tRSD1 tRSD1 tAH3 tAC6 tRDS1 tRDH1 tRSD1 tRSD2 tAH2 tAC4 tRDS2 tRDH2 tWRD2 tWRD1 tWDS3 tWSW2 tAH3 tWDH3 tDACD2 tEDACD2 Figure 26.12 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) Rev. 1.00 Sep. 19, 2008 Page 1217 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics T1 T2 T1 T1 A23 to A6, A0 tAD A5 to A1 CS7 to CS0 AS tRSD2 RD Read D15 to D0 tAA1 tRDS2 tRDH2 HWR, LWR Figure 26.13 Burst ROM Access Timing: One-State Burst Access Rev. 1.00 Sep. 19, 2008 Page 1218 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics T1 T2 T3 T1 T2 A23 to A6, A0 tAD A5 to A1 CS7 to CS0 tAS1 AS tASD tASD tRSD2 RD Read D15 to D0 tAA3 tRDS2 tRDH2 tAH1 HWR, LWR Figure 26.14 Burst ROM Access Timing: Two-State Burst Access Rev. 1.00 Sep. 19, 2008 Page 1219 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Tp tAD A23 to A0 tAS3 RAS5 to RAS2 tPCH2 UCAS Tr Tc1 Tc2 tAD tAH1 tCSD2 tAS2 tCASD1 tAH2 tCSD3 tCASD1 tCASW1 LCAS tOED1/ tOED1B tOED1/ tOED1B tAC1 OE, RD Read HWR tAC4 D15 to D0 tAA3 tRDS2 tRDH2 OE, RD tWRD2 Write HWR tWDD D15 to D0 tWCS1 tWCH1 tWRD2 tWDS1 tWDH2 AS tDACD1 DACK0, DACK1 tEDACD1 EDACK2, EDACK3 tEDACD2 tDACD2 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Figure 26.15 DRAM Access Timing: Two-State Access Rev. 1.00 Sep. 19, 2008 Page 1220 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Tp Tr Tc1 Tcw Tcwp Tc2 A23 to A0 RAS5 to RAS2 UCAS, LCAS OE, RD Read HWR D15 to D0 UCAS, LCAS OE, RD Write HWR D15 to D0 AS WAIT tWTS tWTH tWTS tWTH DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Tcw : Wait cycle inserted by programmable wait function Tcwp: Wait cycle inserted by pin wait function Figure 26.16 DRAM Access Timing: Two-State Access, One Wait Rev. 1.00 Sep. 19, 2008 Page 1221 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 A23 to A0 RAS5 to RAS2 tCPW1 UCAS LCAS OE, RD Read HWR tAC3 D15 to D0 OE, RD Write HWR tRCH tRCS1 D15 to D0 AS tDACD1 DACK0, DACK1 tEDACD1 EDACK2, EDACK3 tEDACD2 tDACD2 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Figure 26.17 DRAM Access Timing: Two-State Burst Access Rev. 1.00 Sep. 19, 2008 Page 1222 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Tp tAD A23 to A0 tAS2 RAS5 to RAS2 tPCH1 Tr Tc1 Tc2 Tc3 tAD tAH2 tCSD1 tAS3 tAH3 tCASD2 tCASW2 tCSD3 tCASD1 UCAS LCAS tOED2/ tOED2B tAC2 tOED1/ tOED1B OE, RD HWR tAC7 D15 to D0 Read tAA5 tRDS2 tRDH2 OE, RD HWR tWRD2 tWCS2 tWCH2 tWRD2 Write tWDD D15 to D0 tWDS2 tWDH3 AS DACK0, DACK1 tDACD1 tDACD2 tEDACD1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 tEDACD2 Figure 26.18 DRAM Access Timing: Three-State Access (RAST = 1) Rev. 1.00 Sep. 19, 2008 Page 1223 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 A23 to A0 RAS5 to RAS0 tCPW2 UCAS LCAS OE, RD Read HWR tAC8 D15 to D0 OE, RD Write HWR tRCH tRCS2 D15 to D0 AS DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 1 and EDDS = 1 RAS timing: when RAST = 1 Figure 26.19 DRAM Access Timing: Three-State Burst Access Rev. 1.00 Sep. 19, 2008 Page 1224 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics TRp TRr TRc1 TRc2 tCSD1 RAS5 to RAS2 tCSD2 tCSR1 tCASD1 UCAS, LCAS tCASD1 OE Figure 26.20 CAS-Before-RAS Refresh Timing TRp tCSD1 RAS5 to RAS2 tCASD1 tCSD2 tCSR2 tCASD1 TRrw TRr TRc1 TRcw TRc2 UCAS, LCAS OE Figure 26.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Rev. 1.00 Sep. 19, 2008 Page 1225 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Self-refresh TRp tCSD2 RAS5 to RAS2 tCASD1 UCAS, LCAS tCASD1 tCSD2 TRr TRc TRc TRp DRAM access Tp Tr tRPS2 OE Figure 26.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) Self-refresh TRp tCSD2 RAS5 to RAS2 tCASD1 UCAS, LCAS tCSD2 tRPS1 tCASD1 TRr TRc TRc TRp DRAM access Tp Tr OE Figure 26.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) Rev. 1.00 Sep. 19, 2008 Page 1226 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics tBREQS BREQ tBACD BACK tBZD A23 to A0 tBZD tBACD tBREQS CS7 to CS0 (RAS5 to RAS2) D15 to D0 AS, RD HWR, LWR UCAS, LCAS, OE Figure 26.24 External Bus Release Timing BACK tBRQOD BREQO tBRQOD Figure 26.25 External Bus Request Output Timing Rev. 1.00 Sep. 19, 2008 Page 1227 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Tp Tr Tc1 Tw Tc2 SDRAM tAD2 Address bus Precharge-sel tCSD4 tCSD4 tCSD4 CAS WE CKE DQMU, DQML Data bus tCSD4 tCSD4 RAS tCSD4 Read tDQMD tDQMD High tRDS3 tRDH3 tCSD4 RAS tCSD4 tCSD4 CAS tCSD4 WE Write CKE High tDQMD DQMU, DQML tWDD Data bus tWDH4 tDQMD tCSD4 tCSD4 tCSD4 tCSD4 Figure 26.26 Synchronous DRAM Basic Access Timing (CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 1228 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics TRp TRr Software standby TRr2 SDRAM Address bus Precharge-sel RAS CAS WE tCKED/ tCKEDB CKE tCKED/ tCKEDB Figure 26.27 Synchronous DRAM Self-Refresh Timing Rev. 1.00 Sep. 19, 2008 Page 1229 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Tp Tr Tc1 Tc2 TRr Ttp2 SDRAM Address bus Precharge-sel RAS CAS WE tCKED/ tCKEDB tCKED/ tCKEDB CKE DQMU, DQML Data bus DACK or EDACK Figure 26.28 Read Data: Two-State Expansion (CAS Latency 2) Rev. 1.00 Sep. 19, 2008 Page 1230 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.3.4 DMAC and EXDMAC Timing The DMAC and EXDMAC timings are shown below. T1 T2 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tEDACD1 EDACK0 to EDACK3 tEDACD2 tDACD2 Figure 26.29 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access Rev. 1.00 Sep. 19, 2008 Page 1231 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics T1 T2 T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tEDACD1 EDACK2, EDACK3 tEDACD2 tDACD2 Figure 26.30 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access Rev. 1.00 Sep. 19, 2008 Page 1232 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics T1 tTED TEND0, TEND1 tETED ETEND2, ETEND3 T2 or T3 tTED tETED Figure 26.31 DMAC and EXDMAC, TEND/ETEND Output Timing tDRQS tDRQH DREQ0, DREQ1 tEDRQS tDERQH EDREQ2, EDREQ3 Figure 26.32 DMAC and EXDMAC, DREQ/EDREQ Input Timing tEDRKD EDRAK2, EDRAK3 tEDRKD Figure 26.33 EXDMAC, EDRAK Output Timing Rev. 1.00 Sep. 19, 2008 Page 1233 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Tma1 Tma2 T1 T2 tAD A23 to A0 tCSD1 CS7, CS6 tAHD AH tRSD1 tRSD2 RD Read (RDNn=0) tAC2 tAA6 tMAD tMAS1 tMAH tRDS2 tRDH2 D15 to D0 A15 to A0 D15 toD0 tWRD2 tWRD2 HWR, LWR Write tMAD tWDD tWSW tWDH1 D15 to D0 A15 to A0 D15 toD0 tDACD1 tDACD2 DACK0, DACK1 tEDACD1 tEDACD2 EDACK2, EDACK3 Figure 26.34 Multiplexed Bus Timing: Data Two-State Access Rev. 1.00 Sep. 19, 2008 Page 1234 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics Tma1 Tmaw Tma2 T1 T2 Tw T3 tAD A23 to A0 tCSD1 CS7, CS6 tAHD AH tRSD1 RD tRSD2 Read (RDNn=0) D15 to D0 tMAD tMAS2 tMAH A15 to A0 tWRD1 tRDS2 tRDH2 D15 to D0 tWRD2 HWR, LWR Write D15 to D0 tMAD A15 to A0 tWDD tWDS1 D15 to D0 tWTS tWTH tWTS tWTH tWDH1 WAIT Figure 26.35 Multiplexed Bus Timing: Data Three-State Access, One Wait (With address wait: when ADDEX = 1) Rev. 1.00 Sep. 19, 2008 Page 1235 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics 26.3.5 Timing of On-Chip Peripheral Modules The on-chip peripheral module timings are shown below. T1 tPRS tPRH Ports 1 to 6, 8, 9, A to H (read) tPWD Ports 1 to 3, 6, 8, P53 to P50, ports A to H (write) T2 Figure 26.36 I/O Port Input/Output Timing tPOD PO15 to PO0 Figure 26.37 PPG Output Timing Rev. 1.00 Sep. 19, 2008 Page 1236 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA11, TIOCB0 to TIOCB11, TIOCC0, TIOCC3, TIOCC6, TIOCC9, TIOCD0, TIOCD3, TIOCD6, and TIOCD9 Figure 26.38 TPU Input/Output Timing tTCKS TCLKA to TCLKH tTCKWL tTCKWH tTCKS Figure 26.39 TPU Clock Input Timing Rev. 1.00 Sep. 19, 2008 Page 1237 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics tTMOD TMO0, TMO1 Figure 26.40 8-Bit Timer Output Timing tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS Figure 26.41 8-Bit Timer Clock Input Timing tTMRS TMRI0, TMRI1 Figure 26.42 8-Bit Timer Reset Input Timing Rev. 1.00 Sep. 19, 2008 Page 1238 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics tWOVD WDTOVF tWOVD Figure 26.43 WDT Output Timing tSCKW SCK0 to SCK4 tScyc tSCKr tSCKf Figure 26.44 SCK Clock Input Timing SCK0 to SCK4 tTXD TxD0 to TxD4 (transmit data) tRXS tRXH RxD0 to RxD4 (receive data) Figure 26.45 SCI Input/Output Timing: Synchronous Mode tTRGS ADTRG0, ADTRG1 Figure 26.46 A/D Converter External Trigger Input Timing Rev. 1.00 Sep. 19, 2008 Page 1239 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics VIH SDA0 to SDA1 tBUF tSTAH VIL tSCLH tSTAS tSP tSTOS SCL0 to SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS P* Note: S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 26.47 I2C Bus Interface 2 Input/Output Timing (Option) P tCTXD CTx (transmit data) tCRXS CRx (receive data) tCRXH Figure 26.48 RCAN-ET Input/Output Timing Rev. 1.00 Sep. 19, 2008 Page 1240 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics SCS (output) tTD tLEAD SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tSU tH tOD tSUcyc tHI tFALL tRISE tLAG Figure 26.49 SSU Timing (Master, CPHS = 1) SCS (output) tTD tLEAD SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tSU tH tOD tSUcyc tHI tFALL tRISE tLAG Figure 26.50 SSU Timing (Master, CPHS = 0) Rev. 1.00 Sep. 19, 2008 Page 1241 of 1270 REJ09B0466-0100 Section 26 Electrical Characteristics SCS (input) tLEAD SSCK (input) CPOS = 1 tHI tFALL tRISE tLAG tTD tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tSU SSI (output) tOH tOD tSUcyc tH tREL tSA Figure 26.51 SSU Timing (Slave, CPHS = 1) SCS (input) tLEAD SSCK (input) CPOS = 1 tHI tFALL tRISE tLAG tTD tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tSU SSI (output) tSA tOH tOD tSUcyc tH tREL Figure 26.52 SSU Timing (Slave, CPHS = 0) Rev. 1.00 Sep. 19, 2008 Page 1242 of 1270 REJ09B0466-0100 Appendix Appendix A. Port States in Each Processing State Port States in Each Processing State (H8S/2426R Group and H8S/2426 Group) MCU Operating Mode Reset 1, 2, 4, 7 1, 2, 4, 7 1, 2, 4, 7 T T T Hardware Standby Software Standby Mode Mode T T T Keep Keep [WAIT-B input] T [Other than the above] Keep P24 to P20 P34 to P30 P35/OE-B/ 1 CKE-B* 1, 2, 4, 7 1, 2, 4, 7 1, 2, 4, 7 T T T T T T Keep Keep [OE-B, CKE-B output, OPE = 0] T [OE-B output, OPE = 1] H [CKE-B output, OPE = 1] L [Other than the above] Keep Port 4 P53 P52/BACK-B 1, 2, 4, 7 1, 2, 4, 7 1, 2, 4, 7 T T T T T T T Keep [BACK-B output] BACK-B [Other than the above] Keep T Keep [BACK-B output] BACK-B [Other than the above] Keep Input port I/O port [BACK-B output] BACK-B [Other than the above] I/O port Bus Release State Keep Keep [WAIT-B input] T [Other than the above] Keep Keep Keep [OE-B, CKE-B output, OPE = 0] T [Other than the above] Keep Program Execution State Sleep Mode I/O port I/O port [WAIT-B input] WAIT-B [Other than the above] I/O port I/O port I/O port [OE-B, CKE-B output, OPE = 0] OE-B, CKE-B [Other than the above] I/O port Table A.1 Port Name Pin Name Port 1 P27 to P26 P25/WAIT Rev. 1.00 Sep. 19, 2008 Page 1243 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name P51/BREQ-B MCU Operating Mode Reset 1, 2, 4, 7 T Hardware Standby Software Standby Mode Mode T [BREQ-B input] T [Other than the above] Keep Bus Release State [BREQ-B input] BREQ-B [Other than the above] Keep Program Execution State Sleep Mode [BREQ-B input] BREQ-B [Other than the above] I/O port P50/BREQO-B 1, 2, 4, 7 T T [BREQO-B output] BREQO-B [Other than the above] Keep [BREQO-B output] [BREQO-B output] BREQO-B BREQO-B [Other than the above] Keep Keep Keep T Keep [Other than the above] I/O port I/O port I/O port Input port Input port Port 6 Port 8 P97 to P96 P95/DA3 1, 2, 4, 7 1, 2, 4, 7 1, 2, 4, 7 1, 2, 4, 7 T T T T T T T T Keep Keep T [DAOE3 = 1] Keep [DAOE3 = 0] T P94/DA2 1, 2, 4, 7 T T [DAOE2 = 1] Keep [DAOE2 = 0] T Keep Input port P93 to P90 PA7/A23 PA6/A22 PA5/A21 1, 2, 4, 7 1, 2, 4, 7 T T T T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep T [Address output] T [Other than the above] Keep Input port [Address output] A23 to A21 [Other than the above] I/O port Rev. 1.00 Sep. 19, 2008 Page 1244 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name PA4/A20 PA3/A19 PA2/A18 PA1/A17 MCU Operating Mode Reset 1, 2 L Hardware Standby Software Standby Mode Mode T [OPE = 0] T [OPE = 1] Keep Bus Release State T Program Execution State Sleep Mode [Address output] A20 to A16 3, 4, 7 PA0/A16 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [Address output] T [Other than the above] Keep [Address output] A20 to A16 [Other than the above] I/O port Port B 1, 2 L T [OPE = 0] T [OPE = 1] Keep T [Address output] A15 to A8 3, 4, 7 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [Address output] T [Other than the above] Keep [Address output] A15 to A8 [Other than the above] I/O port Rev. 1.00 Sep. 19, 2008 Page 1245 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name Port C MCU Operating Mode Reset 1, 2 L Hardware Standby Software Standby Mode Mode T [OPE = 0] T [OPE = 1] Keep Bus Release State T Program Execution State Sleep Mode [Address output] A7 to A0 3, 4, 7 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [Address output] T [Other than the above] Keep [Address output] A7 to A0 [Other than the above] I/O port Port D 1, 2, 4 3, 5, 7 T T T T T [Data bus] T [Other than the above] Keep T [Data bus] T [Other than the above] Keep Keep T D15 to D8 [Data bus] D15 to D8 [Other than the above] I/O port I/O port D7 to D0 Port E 1, 8-bit 2, bus 4 16-bit bus T T T T Keep T Rev. 1.00 Sep. 19, 2008 Page 1246 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name Port E MCU Operating Mode Reset 3, 8-bit 7 bus 16-bit bus T T Hardware Standby Software Standby Mode Mode T T Keep [Data bus] T [Other than the above] Keep Bus Release State Keep [Data bus] T [Other than the above] Keep [Clock output] Clock output [Other than the above] Keep [AS output] T [Other than the above] Keep Program Execution State Sleep Mode I/O port [Data bus] D7 to D0 [Other than the above] I/O port [Clock output] Clock output [Other than the above] Input port [AS output] AS [Other than the above] I/O port PF7/ 1, 2, 4 3, 7 Clock output T T [Clock output] H [Other than the above] Keep PF6/AS/AH 1, 2, 4 3, 7 H T T [AS output, OPE = 0] T [AS output, OPE = 1] H [Other than the above] Keep PF5/RD PF4/HWR 1, 2, 4 H T [OPE = 0] T [OPE = 1] H T RD, HWR 3, 7 T [RD, HWR output, OPE = 0] T [RD, HWR output, OPE = 1] H [Other than the above] Keep [RD, HWR output] T [Other than the above] Keep [RD, HWR output] RD, HWR [Other than the above] I/O port Rev. 1.00 Sep. 19, 2008 Page 1247 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name PF3/LWR MCU Operating Mode Reset 1, 2, 4 3, 7 H T Hardware Standby Software Standby Mode Mode T [LWR output, OPE = 0] T [LWR output, OPE = 1] H [Other than the above] Keep Bus Release State [LWR output] T [Other than the above] Keep Program Execution State Sleep Mode [LWR output] LWR [Other than the above] I/O port PF2/LCAS/ 1 DQML* 1, 2, 4, 7 T T [LCAS, DQML output, OPE = 0] T [LCAS, DQML output, OPE = 1] H [Other than the above] Keep [LCAS, DQML output] T [Other than the above] Keep [LCAS, DQML output] LCAS, DQML [Other than the above] I/O port PF1/UCAS/ 1 DQMU* 1, 2, 4, 7 T T [UCAS, DQMU output, OPE = 0] T [UCAS, DQMU output, OPE = 1] H [Other than the above] Keep [UCAS, DQMU output] T [Other than the above] Keep [UCAS, DQMU output] UCAS [Other than the above] I/O port PF0/WAIT-A 1, 2, 4, 7 T T [WAIT-A input] T [Other than the above] Keep [WAIT-A input] T [Other than the above] Keep [BREQ-A input] BREQ-A [Other than the above] Keep [WAIT-A input] WAIT-A [Other than the above] I/O port [BREQ-A input] BREQ-A [Other than the above] I/O port PG6/BREQ-A 1, 2, 4, 7 T T [BREQ-A input] T [Other than the above] Keep Rev. 1.00 Sep. 19, 2008 Page 1248 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name PG5/BACK-A MCU Operating Mode Reset 1, 2, 4, 7 T Hardware Standby Software Standby Mode Mode T [BACK-A output] BACK-A [Other than the above] Keep Bus Release State [BACK-A output] BACK-A [Other than the above] Keep Program Execution State Sleep Mode [BACK-A output] BACK-A [Other than the above] I/O port [BREQO-A output] BREQO-A [Other than the above] I/O port [CS output] CS [Other than the above] I/O port PG4/BREQO-A 1, 2, 4, 7 T T [BREQO-A output] [BREQO-A output] BREQO-A BREQO-A [Other than the above] Keep [Other than the above] Keep [CS output] T [Other than the above] Keep PG3/CS3/ 1 RAS3/CAS* PG2/CS2/ 1 RAS2/RAS* PG1/CS1 1, 2, 4, 7 T T [CS output, OPE = 0] T [CS output, OPE = 1] H [Other than the above] Keep PG0/CS0 1, 2 3, 4, 7 H T T [CS output, OPE = 0] T [CS output, OPE = 1] H [Other than the above] Keep [CS output] T [Other than the above] Keep [CS output] CS [Other than the above] I/O port Rev. 1.00 Sep. 19, 2008 Page 1249 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name PH3/OE-A/ 1 CKE-A* /CS7 MCU Operating Mode Reset 1, 2, 4, 7 T Hardware Standby Software Standby Mode Mode T [OE-A, CS, CKE-A output, OPE = 0] T [OE-A output, OPE = 1] H [CS output, OPE = 1] H [CKE-A output, OPE = 1] L [Other than the above] Keep Bus Release State [OE-A, CS, CKE-A output] T [Other than the above] Keep Program Execution State Sleep Mode [OE-A, CKE-A output] OE-A, CKE-A [CS output] CS [Other than the above] I/O port PH2/CS6 1, 2, 4, 7 T T [CS output, OPE = 0] T [CS output, OPE = 1] H [Other than the above] Keep [CS output] T [Other than the above] Keep [CS output] CS [Other than the above] I/O port PH1/CS5/ RAS5 1 SDRAM* 1, 2, 4, 7 [SDPST [SDPSTP [SDPSTP = 0] L P = 0] = 0] Clock L [SDPSTP = 1, output [SDPSTP CS output, OPE = 0] = 1] T T [SDPSTP = 1, CS output, OPE = 1] H [Other than the above] Keep [SDPSTP = 0] Clock output [SDPSTP = 1, CS output] T [Other than the above] Keep [SDPSTP = 0] Clock output [SDPSTP = 1, CS output] CS [Other than the above] Keep Rev. 1.00 Sep. 19, 2008 Page 1250 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name PH0/CS4/ 1 RAS4/WE* MCU Operating Mode Reset 1, 2, 4, 7 T Hardware Standby Software Standby Mode Mode T [CS output, OPE = 0] T [CS output, OPE = 1] H [Other than the above] Keep Bus Release State [CS output] T [Other than the above] Keep Program Execution State Sleep Mode [CS output] CS [Other than the above] I/O port PJ2 PJ1 to PJ0 WDTOVF 1, 2, 4, 7 1, 2, 4, 7 1, 2, 4, 7 T T H T T H T Keep H T Keep H Input port I/O port H* 2 [Legend] H: High-level L: Low-level Keep: Input ports become high-impedance, and output ports retain their state. T: High-impedance DDR: Data direction register OPE: Output port enable Notes: 1. Not supported by the H8S/2426 Group. 2. Low output if a watchdog timer overflow occurs when WT/IT is set to 1. Rev. 1.00 Sep. 19, 2008 Page 1251 of 1270 REJ09B0466-0100 Appendix Table A.2 Port Name Pin Name Port 1 P27, P26 P25/WAIT-B Port States in Each Processing State (H8S/2424 Group) MCU Operating Mode 1, 2, 4, 7 1, 2, 4, 7 1, 2, 4, 7 Hardware Standby Mode T T T Software Bus Release Standby Mode State Keep Keep [WAIT-B input] T Keep Keep [WAIT-B input] T Program Execution State Sleep Mode I/O port I/O port [WAIT-B input] WAIT-B [Other than the above] I/O port I/O port I/O port [OE-B output] OE [Other than the above] I/O port Reset T T T [Other than the [Other than the above] above] Keep Keep P24 to P20 P34 to P30 P35/OE-B 1, 2, 4, 7 1, 2, 4, 7 1, 2, 4, 7 T T T T T T Keep Keep [OE-B output, OPE = 0] T [OE-B output, OPE = 1] H [Other than the above] Keep Port 4 P53 1, 2, 4, 7 1, 2, 4, 7 T T T T T T T Keep [BACK-B output] T T Keep [BACK-B output] BACK-B Keep Keep [OE-B output] T [Other than the above] Keep Input port I/O port [BACK-B output] BACK-B [Other than the above] I/O port [BREQ-B input] BREQ-B [Other than the above] I/O port P52/BACK-B 1, 2, 4, 7 [Other than the [Other than the above] Keep above] Keep P51/BREQ-B 1, 2, 4, 7 T T [BREQ-B input] [BREQ-B input] BREQ-B T [Other than the [Other than the above] above] Keep Keep Rev. 1.00 Sep. 19, 2008 Page 1252 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name P50/ BREQO-B MCU Operating Mode 1, 2, 4, 7 Reset T Hardware Standby Mode T Software Bus Release Standby Mode State [BREQO-B output] BREQO-B [BREQO-B output] BREQO-B Program Execution State Sleep Mode [BREQO-B output] BREQO-B [Other than the above] I/O port I/O port Input port [Other than the [Other than the above] above] Keep Keep Port 8 P95/DA3 1, 2, 4, 7 1, 2, 4, 7 T T T T Keep [DAOE3 = 1] Keep [DAOE3 = 0] T P94/DA2 1, 2, 4, 7 T T [DAOE2 = 1] Keep [DAOE2 = 0] T PA7/A23/CS7 1, 2, 4, 7 T T [CS output, OPE = 0] T [CS output, OPE = 1] H [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [CS output] T [Address output] T [Other than the above] Keep Keep Keep Keep Input port [CS output] CS [Address output] A23 [Other than the above] I/O port Rev. 1.00 Sep. 19, 2008 Page 1253 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name PA6/A22 PA5/A21 MCU Operating Mode 1, 2, 4, 7 Reset T Hardware Standby Mode T Software Bus Release Standby Mode State [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [Address output] T [Other than the above] Keep Program Execution State Sleep Mode [Address output] A22 to A21 [Other than the above] I/O port PA4/A20 PA3/A19 PA2/A18 PA1/A17 1, 2 L T [OPE = 0] T [OPE = 1] Keep T [Address output] A20 to A16 3, 4, 7 PA0/A16 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [Address output] T [Other than the above] Keep [Address output] A20 to A16 [Other than the above] I/O port Rev. 1.00 Sep. 19, 2008 Page 1254 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name Port B MCU Operating Mode 1, 2 Reset L Hardware Standby Mode T Software Bus Release Standby Mode State [OPE = 0] T [OPE = 1] Keep T Program Execution State Sleep Mode [Address output] A15 to A8 4 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [Address output] T [Other than the above] Keep [Address output] A15 to A8 [Other than the above] I/O port 3, 7 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [Address output] T [Other than the above] Keep [Address output] A15 to A8 [Other than the above] I/O port Rev. 1.00 Sep. 19, 2008 Page 1255 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name Port C MCU Operating Mode 1, 2 Reset L Hardware Standby Mode T Software Bus Release Standby Mode State [OPE = 0] T [OPE = 1] Keep T Program Execution State Sleep Mode [Address output] A7 to A0 4 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [Address output] T [Other than the above] Keep [Address output] A7 to A0 [Other than the above] I/O port 3, 7 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep [Address output] T [Other than the above] Keep [Address output] A7 to A0 [Other than the above] I/O port Port D 1, 2, 4 3, 7 T T T T T [Data bus] T T [Data bus] T D15 to D8 [Data bus] D15 to D8 [Other than the above] I/O port [Other than the [Other than the above] above] Keep Keep Rev. 1.00 Sep. 19, 2008 Page 1256 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name Port E MCU Operating Mode 1, 2, 4 8-bit bus 16-bit bus 8-bit bus 16-bit bus Reset T T T T Hardware Standby Mode T T T T Software Bus Release Standby Mode State Keep T Keep [Data bus] T Keep T Keep [Data bus] T Program Execution State Sleep Mode I/O port D7 to D0 I/O port [Data bus] D7 to D0 [Other than the above] I/O port [Clock output] Clock output [Other than the above] Input port [AS output] AS [Other than the above] I/O port 3, 7 [Other than the [Other than the above] above] Keep Keep PF7/ 1, 2, 4 3, 7 Clock output T T [Clock output] H [Clock output] Clock output [Other than the [Other than the above] above] Keep Keep PF6/AS 1, 2, 4 3, 7 H T T [AS output, OPE = 0] T [AS output, OPE = 1] H [Other than the above] Keep PF5/RD PF4/HWR 3, 7 T 1, 2, 4 H T [OPE = 0] T [OPE = 1] H [RD, HWR output, OPE = 0] T [RD, HWR output, OPE = 1] H [Other than the above] Keep T [AS output] T [Other than the above] Keep RD, HWR [RD, HWR output] [RD, HWR output] T RD, HWR [Other than the above] [Other than the Keep above] I/O port Rev. 1.00 Sep. 19, 2008 Page 1257 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name PF3/LWR MCU Operating Mode 1, 2, 4 3, 7 Reset H T Hardware Standby Mode T Software Bus Release Standby Mode State [LWR output, OPE = 0] T [LWR output, OPE = 1] H [Other than the above] Keep [LWR output] T [Other than the above] Keep Program Execution State Sleep Mode [LWR output] LWR [Other than the above] I/O port PF2/LCAS/ CS6 1, 2, 4, 7 T T [LCAS output, OPE = 0] T [LCAS output, OPE = 1] H [CS output, OPE = 1] T [CS output, OPE = 1] H [Other than the above] Keep [LCAS output] T [CS output] T [Other than the above] Keep [LCAS output] LCAS [CS output] CS [Other than the above] I/O port PF1/UCAS/C 1, 2, 4, 7 S5 T T [UCAS output, OPE = 0] T [UCAS output, OPE = 1] H [CS output, OPE = 1] T [CS output, OPE = 1] H [Other than the above] Keep [UCAS output] T [CS output] T [Other than the above] Keep [UCAS output] UCAS [CS output] CS [Other than the above] I/O port Rev. 1.00 Sep. 19, 2008 Page 1258 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name PF0/WAITA/OE-A MCU Operating Mode 1, 2, 4, 7 Reset T Hardware Standby Mode T Software Bus Release Standby Mode State [WAIT-A input] T [OE-A output] T [OE-A output, OPE = 1] H [Other than the above] Keep [WAIT-A input] T [OE-A output, OPE = 0] T [Other than the above] Keep Program Execution State Sleep Mode [WAIT-A input] WAIT-A [OE-A output, OPE = 0] OE-A [Other than the above] I/O port PG6/BREQ-A 1, 2, 4, 7 T T [BREQ-A input] [BREQ-A input] BREQ-A T [Other than the [Other than the above] above] Keep Keep [BREQ-A input] BREQ-A [Other than the above] I/O port [BACK-A output] BACK-A [Other than the above] I/O port [BREQO-A output] BREQO-A [CS4 output] CS4 [Other than the above] I/O port PG5/BACK-A 1, 2, 4, 7 T T [BACK-A output] BACK-A [BACK-A output] BACK-A [Other than the [Other than the above] Keep above] Keep [BREQO-A output] BREQO-A [CS4 output] T [Other than the above] Keep PG4/ BREQO-A/ CS4 1, 2, 4, 7 T T [BREQO-A output] BREQO-A [CS4 output, OPE = 0] T [CS4 output, OPE = 1] H [Other than the above] Keep Rev. 1.00 Sep. 19, 2008 Page 1259 of 1270 REJ09B0466-0100 Appendix Port Name Pin Name PG3/CS3 PG2/CS2 PG1/CS1 MCU Operating Mode 1, 2, 4, 7 Reset T Hardware Standby Mode T Software Bus Release Standby Mode State [CS output, OPE = 0] T [CS output, OPE = 1] H [Other than the above] Keep [CS output] T [Other than the above] Keep Program Execution State Sleep Mode [CS output] CS [Other than the above] I/O port PG0/CS0 1, 2 3, 4, 7 H T T [CS output, OPE = 0] T [CS output, OPE = 1] H [Other than the above] Keep [CS output] T [Other than the above] Keep [CS output] CS [Other than the above] I/O port [Legend] H: High-level L: Low-level Keep: Input ports become high-impedance, and output ports retain their state. T: High-impedance DDR: Data direction register OPE: Output port enable Rev. 1.00 Sep. 19, 2008 Page 1260 of 1270 REJ09B0466-0100 Appendix B. Product Code Lineup Type Code Flash memory version R4F24269R* R4F24268R R4F24265R ROM-less version R4S24262R* R4S24261R R4F24269* R4F24268 R4F24265 ROM-less version R4S24262* R4S24261 R4F24249* R4F24248 R4F24245 ROM-less version R4S24242* R4S24241 Mark Code Package code R4F24269VRFQV* PLQP0144KA-K R4F24268VRFQV R4F24265VRFQV R4S24262VRFQV* R4S24261VRFQV R4F24269VFQV* R4F24268VFQV R4F24265VFQV R4S24262VFQV* R4S24261VFQV R4F24249VFQV* R4F24248VFQV R4F24245VFQV R4S24242VFQV* R4S24241VFQV PLQP0120LA-A Product Type H8S/2426R Group H8S/2426 Group Flash memory version H8S/2424 Group Flash memory version Note: * In planning Rev. 1.00 Sep. 19, 2008 Page 1261 of 1270 REJ09B0466-0100 Appendix C. Package Dimensions RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g JEITA Package Code P-LQFP144-20x20-0.50 HD *1 108 D 73 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 109 72 bp b1 c1 HE E c Reference Dimension in Millimeters Symbol *2 Terminal cross section A2 A 1 ZD 36 Index mark F ZE 144 37 L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 *3 e y bp x Detail F Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.17 0.22 0.27 0.20 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.10 1.25 1.25 0.35 0.5 0.65 1.0 Figure C.1 Package Dimensions (LQFP2020-144) Rev. 1.00 Sep. 19, 2008 Page 1262 of 1270 REJ09B0466-0100 A1 c Appendix JEITA Package Code P-TFLGA145-9x9-0.65 RENESAS Code PTLG0145JB-A Previous Code MASS[Typ.] 0.15g wSA D wSB x4 v y1 S S A yS e A ZD N M L K J H G F E D ZE Reference Symbol e E Dimension in Millimeters B Min Nom 9.0 9.0 Max D E v w A A1 e 1 2 3 4 5 6 7 b 8 9 10 11 12 13 xn S A B 0.15 0.20 1.2 C B A 0.65 0.30 0.35 0.40 0.08 0.1 0.20 b x y y1 SD SE ZD ZE 0.6 0.6 Figure C.2 Package Dimensions (TFLGA-145) Rev. 1.00 Sep. 19, 2008 Page 1263 of 1270 REJ09B0466-0100 Appendix JEITA Package Code P-LQFP120-14x14-0.40 RENESAS Code PLQP0120LA-A Previous Code 120P6R-A / FP-120B / FP-120BV MASS[Typ.] 0.7g HD *1 D 90 61 91 60 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 HE E c1 *2 c Reference Dimension in Millimeters Symbol Terminal cross section 120 1 ZD 30 Index mark F A2 ZE 31 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 A1 L L1 y e *3 bp x Detail F Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.13 0.18 0.23 0.16 0.09 0.145 0.20 0.125 0 8 0.4 0.07 0.08 1.2 1.2 0.35 0.5 0.65 1.0 A Figure C.3 Package Dimensions (LQFP1414-120) Rev. 1.00 Sep. 19, 2008 Page 1264 of 1270 REJ09B0466-0100 c Index Numerics 16-Bit counter mode ............................... 814 16-Bit timer pulse unit (TPU)................. 673 8-Bit timer (TMR) .................................. 797 Bus controller (BSC)............................... 145 Bus release .............................................. 305 C A A/D conversion accuracy........................ 982 A/D converter ......................................... 955 A/D converter activation......................... 754 Absolute accuracy................................... 982 Absolute address....................................... 71 Acknowledge .............................. 6, 921, 938 Activation by external request ................ 339 Activation by software.................... 482, 485 Address mode ......................................... 409 Address space ........................................... 49 Addressing modes..................................... 69 Advanced mode ........................................ 47 Arithmetic operations ......................... 58, 61 Asynchronous mode ............................... 869 Auto request mode.................................. 413 Cascaded connection............................... 814 Cascaded operation ................................. 735 Chain transfer.......................................... 481 Chain transfer when counter = 0 ............. 488 Clock pulse generator ........................... 1091 Clock synchronous communication mode............................ 1030 Clocked synchronous mode .................... 887 CMI......................................................... 125 CMIA ...................................................... 815 CMIA0 .................................................... 127 CMIA1 .................................................... 127 CMIB ...................................................... 815 CMIB0 .................................................... 127 CMIB1 .................................................... 127 Communications protocol ..................... 1067 Compare match count mode ................... 814 Condition field .......................................... 68 Condition-code register (CCR) ................. 53 CPU operating modes ............................... 45 Cycle steal mode ..................................... 414 B Basic timing............................................ 190 Bcc...................................................... 58, 66 Bit manipulation instructions.................... 64 Bit rate .................................................... 859 Block data transfer instructions ................ 68 Block transfer mode................ 359, 417, 480 Branch instructions ................................... 66 Break....................................................... 915 Buffer operation...................................... 731 Burst mode...................................... 368, 415 Burst ROM interface............................... 274 Bus arbitration ........................................ 302 D Data direction register............................. 493 Data register............................................ 493 Data size and data alignment .................. 188 Data transfer controller (DTC)................ 461 Data transfer instructions .......................... 60 DMA controller (DMAC) ....................... 307 DMTEND0A .......................................... 127 DMTEND0B........................................... 127 Rev. 1.00 Sep. 19, 2008 Page 1265 of 1270 REJ09B0466-0100 DMTEND1A .......................................... 127 DMTEND1B .......................................... 127 DRAM interface ............................. 202, 216 DTC vector table .................................... 471 Dual address mode.................................. 409 I I/O port states in each processing state............................. 1243 I/O ports .................................................. 493 I2C bus format......................................... 937 I2C bus interface (IIC)............................. 921 Idle cycle................................................. 277 Idle mode ................................................ 345 IICI0................................................ 129, 130 IICI1................................................ 129, 130 Immediate ................................................. 72 Input capture function ............................. 727 Input pull-up MOS.................................. 493 Instruction set............................................ 58 Interrupt control modes........................... 132 Interrupt exception handling ..................... 97 Interrupt exception handling vector table.............................................. 125 Interrupt mask bit...................................... 53 interrupt mask level .................................. 52 Interrupt priority register (IPR)............... 103 Interrupt sources ..................................... 387 Interval timer mode................................. 829 IrDA operation........................................ 908 IRQ0 ....................................................... 125 E Effective address extension ...................... 68 Ending DMA transfer ............................. 454 ERI0........................................................ 912 ERI1........................................................ 128 ERI2........................................................ 128 ERI3........................................................ 128 ERI4........................................................ 128 Exception handling ................................... 91 Exception handling vector table ............... 92 EXDMA controller (EXDMAC) ............ 393 EXDMTEND2........................................ 127 EXDMTEND3........................................ 127 Extended register (EXR) .......................... 52 Extension of chip select (CS) assertion period............................... 201, 214 External request mode ............................ 413 F Flash memory ....................................... 1041 Framing error.......................................... 876 Full-scale error........................................ 982 L List of registers ..................................... 1123 Logic operations instructions.................... 63 G General call address................................ 935 General registers ....................................... 51 M Mark state ............................................... 915 MCU operating modes.............................. 79 Memory indirect ....................................... 72 Multi-channel operation.......................... 381 Multiply-accumulate register (MAC) ....... 54 Rev. 1.00 Sep. 19, 2008 Page 1266 of 1270 REJ09B0466-0100 N NMI ........................................................ 142 NMI interrupt.......................................... 123 Nonlinearity error ................................... 982 Non-overlapping pulse output ................ 788 Normal mode ...................... 45, 46, 355, 478 Normal transfer mode ............................. 416 Q Quantization error ................................... 982 R RAM ..................................................... 1039 Read strobe (RD) timing ......... 199, 213, 214 Register addresses................................. 1124 Register bits .......................................... 1140 Register direct ........................................... 70 Register Field............................................ 68 Register indirect ........................................ 70 Register indirect with displacement .......... 70 Register indirect with post-increment ....... 71 Register indirect with pre-decrement ........ 71 Register information ............................... 471 Register states in each operating mode ............................. 1160 Registers ABWCR.............................................. 152 ADCSR ............................................... 963 ASTCR................................................ 152 BCR .................................................... 164 BROMCR ........................................... 163 BRR .................................................... 859 CRA .................................................... 466 CRB .................................................... 466 CSACR ............................................... 161 DACR ................................................. 992 DADR ................................................. 992 DAR.................................................... 465 DMABCR ........................................... 323 DMACR.............................................. 315 DMATCR ........................................... 336 DMAWER .......................................... 334 DRACCR ............................................ 175 DRAMCR ........................................... 167 DTCER ............................................... 467 DTVECR ............................................ 467 EDACR............................................... 404 Rev. 1.00 Sep. 19, 2008 Page 1267 of 1270 REJ09B0466-0100 O Offset error ............................................. 982 On-board programming ........................ 1048 On-board programming mode .............. 1048 Open-drain control register..................... 493 Operation field.......................................... 68 Output trigger ......................................... 781 Overflow................................................. 828 Overrun error .......................................... 876 OVI ......................................................... 815 OVI0 ....................................................... 127 OVI1 ....................................................... 127 P Package dimensions.............................. 1262 Parity error.............................................. 876 Phase counting mode .............................. 743 PLL circuit............................................ 1098 Port function control register 2 ............... 667 Port register............................................. 493 Product code lineup .............................. 1261 Program counter (PC) ............................... 52 Program-counter relative .......................... 72 Programmable pulse generator ............... 773 Programmer mode ................................ 1063 Pull-up MOS control register.................. 493 Pulse output .................................... 808, 809 PWM modes ........................................... 737 EDDAR .............................................. 397 EDMDR.............................................. 399 EDSAR............................................... 396 EDTCR............................................... 397 ETCR.................................................. 313 EXMSTPCR ..................................... 1108 ICCRA................................................ 926 ICCRB ................................................ 928 ICDRR................................................ 936 ICDRS ................................................ 936 ICDRT ................................................ 936 ICIER.................................................. 931 ICMR.................................................. 929 ICSR ................................................... 933 IER...................................................... 110 INTCR ................................................ 107 IOAR .................................................. 313 IPR...................................................... 108 IrCR .................................................... 866 ISCR ................................................... 112 ISR...................................................... 118 ITSR ................................................... 119 MAR................................................... 312 MDCR .................................................. 80 MRA................................................... 463 MRB ........................................... 465, 468 MSTPCR .......................................... 1107 NDER ................................................. 776 NDR.................................................... 778 P1DDR ............................................... 502 P1DR .................................................. 503 P2DDR ............................................... 528 P2DR .................................................. 529 P3DDR ............................................... 549 P3DR .................................................. 550 P3ODR ............................................... 551 P5DDR ............................................... 557 P5DR .................................................. 557 P6DDR ............................................... 566 P6DR .................................................. 567 Rev. 1.00 Sep. 19, 2008 Page 1268 of 1270 REJ09B0466-0100 P8DDR................................................ 572 P8DR................................................... 573 PADDR............................................... 588 PADR.................................................. 589 PAODR............................................... 590 PAPCR................................................ 590 PBDDR ............................................... 601 PBDR.................................................. 602 PBPCR................................................ 603 PCDDR ............................................... 613 PCDR.................................................. 614 PCPCR................................................ 615 PCR..................................................... 781 PDDDR............................................... 625 PDDR.................................................. 626 PDPCR................................................ 627 PEDDR ............................................... 629 PEDR .................................................. 630 PEPCR ................................................ 631 PFDDR ............................................... 634 PFDR .................................................. 635 PGDDR............................................... 647 PGDR.................................................. 648 PHDDR............................................... 654 PHDR.................................................. 656 PLLCR.............................................. 1094 PMR.................................................... 782 PODR.................................................. 777 PORT1 ................................................ 503 PORT2 ................................................ 529 PORT3 ................................................ 550 PORT4 ................................................ 555 PORT5 ................................................ 558 PORT6 ................................................ 567 PORT8 ................................................ 573 PORT9 ................................................ 584 PORTA ............................................... 589 PORTB ............................................... 602 PORTC ............................................... 614 PORTD ............................................... 626 PORTE ............................................... 630 PORTF................................................ 635 PORTG ............................................... 648 PORTH ............................................... 656 RDNCR .............................................. 159 RDR.................................................... 840 REFCR ............................................... 178 RMMSTPCR .................................... 1109 RSR..................................................... 840 RSTCSR ............................................. 827 RTCNT ............................................... 181 RTCOR............................................... 181 SAR .................................................... 465 SBYCR ............................................. 1105 SCKCR ............................................. 1092 SCMR ................................................. 858 SCR..................................................... 845 SEMR ................................................. 867 SMR............................................ 841, 858 SSCR2 .............................................. 1010 SSCRH ............................................. 1002 SSCRL.............................................. 1004 SSER................................................. 1006 SSIER ................................................. 122 SSMR ............................................... 1005 SSR ..................................................... 850 SSRDR ............................................. 1013 SSSR................................................. 1007 SSTDR.............................................. 1012 SSTRSR............................................ 1013 SYSCR ................................................. 80 TCNT.................................................. 800 TCORA............................................... 800 TCORB............................................... 800 TCR .................................... 688, 801, 802 TCSR .................................................. 825 TDR .................................................... 841 TGR .................................... 709, 717, 731 TIER ................................................... 712 TIOR................................................... 694 TMDR................................................. 693 TSR ..................................................... 714 TSTR........................................... 717, 719 TSYR .......................................... 718, 720 WTCR................................................. 153 Repeat area function ............................... 418 Repeat mode ................................... 348, 479 Reset ......................................................... 94 Reset exception handling .......................... 94 Resolution ............................................... 982 RXI0 ....................................................... 912 RXI1 ....................................................... 128 RXI2 ....................................................... 128 RXI3 ....................................................... 128 RXI4 ....................................................... 128 S Sample-and-hold circuit.......................... 978 Scan mode............................................... 974 Sequential mode...................................... 342 Serial communication interface .............. 835 Serial communication interface specification ........................... 1064 Shift instructions ....................................... 63 Single address mode ............................... 410 Single address mode ............................... 352 Single mode ............................................ 972 Slave address........................................... 938 Slave-address .......................................... 921 Software activation ................................. 490 SSU mode ............................................. 1018 stack pointer (SP)...................................... 51 Stack status after exception handling...... 100 Start condition......................................... 938 Stop condition ......................................... 938 SWDTEND............................................. 482 Synchronous DRAM interface................ 243 Synchronous operation............................ 728 Rev. 1.00 Sep. 19, 2008 Page 1269 of 1270 REJ09B0466-0100 Synchronous serial communication unit (SSU) ..................... 999 System control instructions ...................... 67 T TCI0V..................................................... 126 TCI1U............................................. 751, 752 TCI1V............................................. 751, 752 TCI2U............................................. 751, 752 TCI2V............................................. 751, 752 TCI3V............................................. 751, 752 TCI4U............................................. 751, 752 TCI4V............................................. 751, 752 TCI5U............................................. 751, 752 TCI5V............................................. 751, 752 TCNT incrementation timing ................. 810 TEI0........................................................ 912 TEI1........................................................ 128 TEI2........................................................ 128 TEI3........................................................ 128 TEI4........................................................ 128 TGI0A ............................................ 751, 752 TGI0B............................................. 751, 752 TGI0C............................................. 751, 752 TGI0D ............................................ 751, 752 TGI1A ............................................ 751, 752 TGI1B............................................. 751, 752 TGI2A ............................................ 751, 752 TGI2B............................................. 751, 752 TGI3A ............................................ 751, 752 TGI3B............................................. 751, 752 TGI3C............................................. 751, 752 TGI3D ............................................ 751, 752 TGI4A............................................. 751, 752 TGI4B ............................................. 751, 752 TGI5A............................................. 751, 752 TGI5B ............................................. 751, 752 Toggle output.................................. 726, 819 Trace Bit ................................................... 52 Trace exception handling.................... 97, 99 Transfer clock ....................................... 1014 Transfer mode ......................................... 339 Transfer rate............................................ 927 Trap instruction exception handling ......... 98 TRAPA instruction ............................. 72, 98 TXI0........................................................ 912 TXI1........................................................ 128 TXI2........................................................ 128 TXI3........................................................ 128 TXI4........................................................ 128 V Valid strobes ........................................... 189 Vector number for the software activation interrupt ................... 467 W Wait control .................................... 198, 212 Watchdog timer (WDT).......................... 823 Waveform output by compare match...... 725 WOVI ..................................................... 831 Write data buffer..................................... 297 Write data buffer function....................... 380 Rev. 1.00 Sep. 19, 2008 Page 1270 of 1270 REJ09B0466-0100 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2426, H8S/2426R, H8S/2424 Group Publication Date: Rev.1.00, Sep. 19, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.2 H8S/2426, H8S/2426R, H8S/2424 Group Hardware Manual |
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